JPH03192730A - Manufacture of thin film transistor array of active matrix diaplay - Google Patents

Manufacture of thin film transistor array of active matrix diaplay

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Publication number
JPH03192730A
JPH03192730A JP1333973A JP33397389A JPH03192730A JP H03192730 A JPH03192730 A JP H03192730A JP 1333973 A JP1333973 A JP 1333973A JP 33397389 A JP33397389 A JP 33397389A JP H03192730 A JPH03192730 A JP H03192730A
Authority
JP
Japan
Prior art keywords
resist
gate
transparent conductive
mask
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1333973A
Other languages
Japanese (ja)
Other versions
JP2846682B2 (en
Inventor
Norio Nakatani
中谷 紀夫
Terushi Sasaki
昭史 佐々木
Keizo Yoshizako
吉迫 圭三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP33397389A priority Critical patent/JP2846682B2/en
Publication of JPH03192730A publication Critical patent/JPH03192730A/en
Application granted granted Critical
Publication of JP2846682B2 publication Critical patent/JP2846682B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To enable an active matrix display in high opening ratio and high precision to be manufactured by a method wherein semiconductor films and a transparent conductive film are patterned by selfmatching process using the rear exposure while a drain wiring is liftoff formed using resist for the display electrode patterning process. CONSTITUTION:Multiple gate wirings 20 comprising an opaque metal are formed on a transparent substrate 1; after laminately forming a phototransmitting gate insulating film 3, transparent conductive films S4, S5 are formed into films; resist R1 in inverse pattern of the gate wirings 20 are left by the rear exposure using the gate wirings 20 as masks on the surfaces of the transparent films S4, S5 coated with the resist R1. Next, the transparent conductive films S4, S5 are patterned to be isolated along the gate wirings 20 using the remaining resist R1 as a mask to be coated with resist R2 repeatedly; resist 3 on the positions excluding the drain wiring position is left by exposure process; a conductive transparent film C6 is patterned to be isolated along the drain wiring using the resist R3 as a mask. Through these procedures, a semiconductor film 4 and the transparent conductive film C6 can be formed in offset state with high precision respectively on the gate electrode 2 and the gate wirings 20.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はアクティブマトリクス表示装置の薄膜トランジ
スタアレーの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a thin film transistor array for an active matrix display device.

(ロ)従来の技術 近年、マトリクス配置された多数の画素単位の表示電極
毎にスイッチングトランジスタとして働く薄膜トランジ
スタ(以下TPTと称する)を結合し、このTPTを駆
動回路をしたアクティブマトリクス表示装置が開発され
ている。この装置は各表示電極にTPTを介して画素情
報を供給し、この画素情報に応じた電界、電流、または
電力によって、表示電極上に装備された液晶層、EL層
あるいはEC層に光学的変化を与え、可視表示を可能と
するものである[特公昭62−6674号公報]。
(b) Conventional technology In recent years, active matrix display devices have been developed in which thin film transistors (hereinafter referred to as TPTs) functioning as switching transistors are connected to each display electrode of a large number of pixels arranged in a matrix, and these TPTs are used as drive circuits. ing. This device supplies pixel information to each display electrode via TPT, and optical changes occur in the liquid crystal layer, EL layer, or EC layer provided on the display electrode by electric field, current, or power according to this pixel information. [Japanese Patent Publication No. 62-6674].

特に、現在ではポケッタブルTV用デイスプレィとして
、上述の液晶層を用いたアクティブマトリクス型液晶表
示装置が注目を集めている。
In particular, active matrix liquid crystal display devices using the above-mentioned liquid crystal layer are currently attracting attention as displays for portable TVs.

第4図(a)に従来のアクティブマトリクス型液晶表示
装置に於けるTPTアレーの画素単位の平面図を示し、
同図(b)にTFT位置のA−A線断面図を示す。
FIG. 4(a) shows a plan view of each pixel of a TPT array in a conventional active matrix liquid crystal display device.
FIG. 5B shows a cross-sectional view taken along line A-A of the TFT position.

これらの同図のTPTは、液晶セルの一方の絶縁基板1
上に形成され、ゲートライン20の一部をなすゲート電
極2、基板全面に設けられたゲート絶縁膜3、局在した
半導体膜4、該半導体膜4のソース並びにドレイン位置
の夫々にオーミックコンタクトを構成する不純物半導体
膜5,5、ソース電極7並びにドレイン電極8の積層体
からなる所謂逆スタガータイプをなし、このソース電極
7に画素単位の表示電極6が結合されている。
These TPTs in the same figure are attached to one insulating substrate 1 of the liquid crystal cell.
Ohmic contacts are formed on the gate electrode 2 forming a part of the gate line 20, the gate insulating film 3 provided on the entire surface of the substrate, the localized semiconductor film 4, and the source and drain positions of the semiconductor film 4. It has a so-called inverted stagger type structure consisting of a stacked structure of impurity semiconductor films 5, 5, a source electrode 7, and a drain electrode 8, and a display electrode 6 for each pixel is connected to this source electrode 7.

このような従来のアクティブマトリクス表示装置のTP
Tアレーの製造方法を工程順に以下に概説する。
TP of such a conventional active matrix display device
The method for manufacturing the T-array will be outlined below in order of steps.

(1)、絶縁基板1上に配線用金属膜を成膜しフォトマ
スク及びフォトレジストを用いてゲート電極2を備える
ゲートライン20を形成する工程。
(1) Step of forming a wiring metal film on the insulating substrate 1 and forming the gate line 20 including the gate electrode 2 using a photomask and photoresist.

(2)、P−CVDI置等を用いて、ゲート絶縁膜3、
非単結晶の半導体膜4、非単結晶の不純物半導体膜5を
順次成膜する工程。
(2) Using a P-CVDI device etc., the gate insulating film 3,
Step of sequentially forming a non-single crystal semiconductor film 4 and a non-single crystal impurity semiconductor film 5.

(3)、7オトマスク及びフォトレジストを用いて上記
半導体膜4と不純物半導体膜5のエツチングを行う工程
(3) Step 7 of etching the semiconductor film 4 and the impurity semiconductor film 5 using an otmask and a photoresist.

(4)、透明導電膜を成膜し7オトマスク及びフォトレ
ジストを用いて表示電極6を形成する工程。
(4) Step of forming a transparent conductive film and forming display electrodes 6 using an otomask and a photoresist.

(5)、配線用金属膜の成膜を行い、7オトマスク及び
フォトレジストを用いてソース電極7、並びにドレイン
電極8を備えるドレインライン80を形成する工程。
(5) A step of forming a metal film for wiring and forming a drain line 80 including a source electrode 7 and a drain electrode 8 using a 7-oto mask and a photoresist.

(6)、上記画電極7.8間のチャンネル位置の上記不
純物半導体膜5をエツチングする工程。
(6) Etching the impurity semiconductor film 5 at the channel position between the picture electrodes 7 and 8.

(ハ)発明が解決しようとする課題 上述の如きアクティブマトリクス表示装置のTPTアレ
ーの製造方法によれば、TPTのパターンの加工精度は
フォトマスクと露光装置の能力で決まる。
(c) Problems to be Solved by the Invention According to the method of manufacturing a TPT array for an active matrix display device as described above, the processing accuracy of the TPT pattern is determined by the capabilities of the photomask and the exposure device.

一般的に現在の7オトマスクのピッチ誤差は±1μm、
露光装置のアライメント誤差は±1μmであるので、上
述の従来の製造方法によれば、±2μmのすなわち0〜
4μmのパターン位置のシフトが発生し、この位置シフ
トを見込んだ余裕のあるパターン設計が必要であった。
Generally, the pitch error of the current 7 otomasks is ±1μm,
Since the alignment error of the exposure device is ±1 μm, according to the conventional manufacturing method described above, the alignment error is ±2 μm, that is, 0 to 0.
A shift in the pattern position of 4 μm occurred, and a pattern design with sufficient margin to account for this position shift was required.

そのため、画素寸法が30μm〜50μm角程度の高画
素集積の例えば、ハイビジョン対応の超高精細液晶表示
装置の如き表示装置を作製する場合には画素占有面積率
が大幅に低下するという不都合が生じていた。即ち、画
素占有面積が低下するという事は、表示画面が全体とし
て暗くなり、表示品位が低下する欠点を招くことになる
Therefore, when manufacturing a display device with a high pixel density, such as an ultra-high-definition liquid crystal display device compatible with high-definition television, with a pixel size of about 30 μm to 50 μm square, there is a problem that the pixel occupation area ratio is significantly reduced. Ta. That is, a reduction in the pixel occupation area results in the disadvantage that the display screen becomes darker as a whole and the display quality deteriorates.

(ニ)課題を解決するための手段 本発明のアクティブマトリクス表示装置のTPTアレー
の製造方法は、透光性基板上に不透明金属からなる複数
本のゲート配線を形成し、透光性のゲート絶縁膜を積層
形成した後、透明導電膜を成膜し、該透明導電膜上面に
レジストを塗布した状態で、上記ゲート配線をマスクと
した背面露光により該ゲート配線の反転パターンをなす
レジストを残存させ、該残存レジストをマスクに上記透
明導電膜をゲート配線に沿って分離するパターニング処
理を行い、続いて再度レジストを塗布し、露光処理によ
りドレイン配線位置以外のレジストを残存させ、該残存
レジストをマスクに透明導電膜をドレイン配線に沿って
分離するパターニング処理を行うことにより、画業単位
の透明導電膜からなる多数の表示電極を得るものである
(d) Means for Solving the Problems The method for manufacturing a TPT array of an active matrix display device of the present invention is to form a plurality of gate wirings made of opaque metal on a transparent substrate, and to insulate the transparent gates. After the films are laminated, a transparent conductive film is formed, and with a resist applied to the upper surface of the transparent conductive film, a resist forming an inverted pattern of the gate wiring is left by back exposure using the gate wiring as a mask. Using the remaining resist as a mask, a patterning process is performed to separate the transparent conductive film along the gate wiring, and then a resist is applied again, and an exposure process is performed to leave the resist at areas other than the drain wiring position, and the remaining resist is masked. By performing a patterning process to separate the transparent conductive film along the drain wiring, a large number of display electrodes made of the transparent conductive film in picture units are obtained.

(ホ)作用 本発明のアクティブマトリクス表示装置のTPTアレー
の製造方法によれば、半導体膜のエツチングレジストと
透明導電膜のエツチングレジストとを背面露光を用いて
ゲート電極を備えるゲート配線に自己整合的に形成する
ため、半導体膜はゲート電極上に、また透明導電膜はゲ
ート配線にオフセット状態に高精度に形成される。
(E) Function According to the method for manufacturing a TPT array of an active matrix display device of the present invention, the etching resist of the semiconductor film and the etching resist of the transparent conductive film are self-aligned to the gate wiring including the gate electrode using back exposure. Therefore, the semiconductor film is formed on the gate electrode and the transparent conductive film is formed offset from the gate wiring with high precision.

くべ)実施例 第1図に本発明の製造方法によって得られるアクティブ
マトリクス表示装置のTPTアレーの画素単位の平面図
を示す。
Embodiment FIG. 1 shows a plan view of a pixel unit of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention.

第1図のTPTアレーの製造方法をそのB−B線に沿っ
た第2図(i)〜(偏)の製造工程図に従って、以下に
説明する。
A method for manufacturing the TPT array shown in FIG. 1 will be described below with reference to manufacturing process diagrams shown in FIGS. 2(i) to (partial) along line B-B.

(1)、同図(i)の第1工程 ガラスからなる透光性基板1上にCrあるいはTa等か
らなるゲート電極部2が局部的に備えられたゲートライ
ン20をフォトマスクを用いて所定の形状に形成する。
(1) First step in Figure (i) A gate line 20 locally provided with a gate electrode portion 2 made of Cr, Ta, etc. is formed on a transparent substrate 1 made of glass using a photomask. Form into the shape of.

該ゲートライン20は画素間を横方向に延在する如く複
数本形成され、各ゲートライン20のゲート電極部2は
画業毎のTPT構成位置に配置される。なお、該ゲート
ライン20の表面を陽極酸化することでゲートの短絡事
故を回避できる。
A plurality of gate lines 20 are formed so as to extend horizontally between pixels, and the gate electrode portion 2 of each gate line 20 is arranged at a TPT configuration position for each image processing. Note that by anodizing the surface of the gate line 20, it is possible to avoid a gate short-circuit accident.

(2)、同図(ii )の第2工程 シリコン窒化膜あるいはシリコン酸化膜からなるゲート
絶縁膜3、アモルファスシリコン半導体膜S4、燐ドー
プのアモルファスシリコン不純物半導体膜S5をP−C
VD装置等を用いて順次成膜する。
(2) In the second step of the same figure (ii), the gate insulating film 3 made of a silicon nitride film or silicon oxide film, the amorphous silicon semiconductor film S4, and the phosphorus-doped amorphous silicon impurity semiconductor film S5 are P-C.
Films are sequentially formed using a VD device or the like.

(3)、同図(ii )の第3工程 ポジレジストを塗布し、背面露光によりゲート電極部2
を備えたゲートライン20位置以外のレジストを感光し
、続いて該レジストを再度7オトマスクを用いて表面側
から通常の露光を行い、ゲート電極部2上にアイランド
状にレジストR1を残存させ、該残存レジス)R1をマ
スクに上記半導体膜S4と不純物半導体膜S5をパター
ニングし、TPTの半導体膜4とこれに同パターンで積
層した不純物半導体膜S5’を得る。
(3), 3rd step of the same figure (ii) Applying a positive resist and exposing the gate electrode part 2 by back exposure.
The resist other than the gate line 20 position is exposed to light, and then the resist is exposed to normal light again from the front side using a 7-oto mask to leave the resist R1 in an island shape on the gate electrode portion 2. The semiconductor film S4 and the impurity semiconductor film S5 are patterned using the remaining resist (residual resist) R1 as a mask to obtain a TPT semiconductor film 4 and an impurity semiconductor film S5' laminated thereon in the same pattern.

(4)、同図(iv)の第4工程 ITOからなる透明導電膜をスパッタリング等の方法で
全面に成膜し、ネガレジストを塗布した後、背面露光に
よりゲート電極部2を備えたゲートライン20の反転パ
ターンをなすレジストR2を形成し、透明導電膜をパタ
ーニングする。尚、上記の反転パターン形成は、ポジレ
ジストのイメージリバーサル法でも作製可能である。
(4), 4th step in the same figure (iv) After forming a transparent conductive film made of ITO on the entire surface by a method such as sputtering and applying a negative resist, the gate line with the gate electrode part 2 is formed by back exposure. A resist R2 having a reverse pattern of 20 is formed, and the transparent conductive film is patterned. Note that the above-mentioned reversal pattern formation can also be produced by an image reversal method using a positive resist.

この結果、透明導電膜は複数本のゲートライン20・・
・間隔より若干狭い幅をもって横方向に帯状に延在する
複数本の透明導電膜C6・・・に分割される。
As a result, the transparent conductive film has multiple gate lines 20...
- It is divided into a plurality of transparent conductive films C6 extending horizontally in a band shape with a width slightly narrower than the interval.

(5)、同図(v)の第5工程 レジストを塗布し、7オトマスクにより11数本のドレ
インライン80・・・の反転パターンのレジス)R3を
形成して、複数本の各透明導電膜C6・・・を夫々パタ
ーニングすることにより、単位画素毎の多数の表示電極
6.6・・・を形成する。この時の表示電極6.6・・
・の形成は、同図に示す如く、1μmのオーバーエツチ
ングが生じるようにエツチングする。
(5) The fifth step resist shown in FIG. By patterning C6, . . ., a large number of display electrodes 6, 6, . . . for each unit pixel are formed. Display electrode 6.6 at this time...
To form ., as shown in the same figure, etching is performed so that over-etching of 1 μm occurs.

(6)、同図(vi)の第6エ程 チタンやアルミなどの第2金属をスパッタリング等の方
法で成膜し、レジストを塗布し、さらにこれをフォトマ
スクを用いて露光し、残存レジストR4をマスクに、第
2金属をパターニングすることにより、上記不純物半導
体膜S5’上と上記表示電極6上とに跨って接合してこ
れらを結線する多数の配線であるソース電極7.7・・
・、並びに上記不純物半導体膜S5’上に接合するドレ
イン電極8・・・を備える複数本のドレインライン80
・・・を得る。このように、不純物半導体膜S5’上で
画電極7.8を同時にパターニング形成することでチャ
ンネル寸法精度を得るのが好ましい。
(6) In the 6th step of the same figure (vi), a second metal such as titanium or aluminum is formed by a method such as sputtering, a resist is applied, and this is further exposed using a photomask to remove the remaining resist. By patterning the second metal using R4 as a mask, source electrodes 7, 7, .
, and a plurality of drain lines 80 including drain electrodes 8 bonded onto the impurity semiconductor film S5'.
...obtain... In this way, it is preferable to obtain channel dimensional accuracy by simultaneously patterning and forming the picture electrodes 7.8 on the impurity semiconductor film S5'.

(7)、同図(vii )の第7エ程 上記第6エ程の結果露出した各TPTのチャネル部の不
純物半導体膜S5’をエツチングによって除去して、半
導体膜4に対するドレイン電極部8、並びにソース電極
7のオーミックコンタクトを実現する不純物半導体膜5
.5を形成する。
(7) In the seventh step of the same figure (vii), the impurity semiconductor film S5' in the channel part of each TPT exposed as a result of the sixth step is removed by etching, and the drain electrode part 8 with respect to the semiconductor film 4 is removed. Also, an impurity semiconductor film 5 that realizes ohmic contact with the source electrode 7
.. form 5.

但し、この不純物半導体膜5.5は、必ずしも必要でな
く、半導体膜4と画電極7.8との直接接合でもTPT
のスイッチング動作に支障のない接合状態が得られるな
ら、不純物半導体膜5.5を省略してもよい。この場合
には、前述の第2工程での不純物半導体膜S5の成膜が
不要となる。
However, this impurity semiconductor film 5.5 is not necessarily necessary, and even if the semiconductor film 4 and the picture electrode 7.8 are directly bonded, TPT
The impurity semiconductor film 5.5 may be omitted if a junction state that does not impede the switching operation can be obtained. In this case, it becomes unnecessary to form the impurity semiconductor film S5 in the second step described above.

以上の本発明実施例方法の工程により、7オトマスクの
使用枚数を削減して、フォトマスクの使用によるパター
ン位置のシフトの発生を抑制しているので、第1図の平
面図に示した様に、各表示電極6・・・が第6図(a)
の平面図の従来の表示電極6・・・より精度よく拡大さ
れたアクティブマトリクス表示装置のTPTアレーを作
成することができる。
Through the steps of the method according to the embodiment of the present invention described above, the number of 7-otomasks used is reduced and the occurrence of pattern position shift due to the use of photomasks is suppressed, so that as shown in the plan view of FIG. , each display electrode 6... is shown in FIG. 6(a).
A TPT array of an active matrix display device that is enlarged with higher precision can be created using the conventional display electrode 6 shown in the plan view.

更に、本発明方法の他の実施例の工程を第3図に示す。Furthermore, the steps of another embodiment of the method of the present invention are shown in FIG.

同図(i)、(vii )は夫々前述の第2図(ii)
、(vii)の本発明の実施例工程に対応しており、該
実施例の他の工程は第2図の他の工程に準じるので、こ
こでは省略する。
Figures (i) and (vii) are the same as Figure 2 (ii) above, respectively.
, (vii) corresponds to the steps of the embodiment of the present invention, and the other steps of this embodiment are similar to the other steps shown in FIG. 2, so their description will be omitted here.

第3図(i)は第2工程を示しており、まず、シリコン
窒化膜あるいはシリコン酸化膜からなるゲート絶縁膜3
、アモルファスシリコン半導体膜S4をP−CVD装置
等を用いて順次成膜する。
FIG. 3(i) shows the second step. First, a gate insulating film 3 made of a silicon nitride film or a silicon oxide film is formed.
, amorphous silicon semiconductor films S4 are sequentially formed using a P-CVD apparatus or the like.

続いて、フォトマスクを用いてゲート電極部z上のTP
Tチャンネル位置にチャンネル保護絶縁膜10を所定の
形状にパターニングする。尚、この時のパターニング法
としては、前述の第3工程と同じく、背面露光と7オト
マスクによる表面露光により形成したレジストをマスク
にエツチングするのが好ましい。
Subsequently, the TP on the gate electrode part z is removed using a photomask.
A channel protection insulating film 10 is patterned into a predetermined shape at the T channel position. As for the patterning method at this time, it is preferable to etch a resist formed by back exposure and front exposure using a 7-oto mask into a mask, as in the third step described above.

その後、不純物半導体膜S5をP−CVD装置等で成膜
する。該チャンネル保護絶縁膜lOとしては、たとえば
、シリコン窒化膜あるいはシリコン酸化膜が使用できる
Thereafter, an impurity semiconductor film S5 is formed using a P-CVD device or the like. For example, a silicon nitride film or a silicon oxide film can be used as the channel protection insulating film IO.

第3図(vii )は第7エ程を示しており、この工程
で、各TPTのチャンネル部の不純物半導体膜S5’ 
をエツチングによって除去する時に、上記チャンネル保
護絶縁膜10が半導体膜4のチャンネル部までエツチン
グされるのを防止する。
FIG. 3(vii) shows the seventh step, in which the impurity semiconductor film S5' in the channel portion of each TPT is removed.
When removing the semiconductor film 4 by etching, the channel protection insulating film 10 is prevented from being etched to the channel portion of the semiconductor film 4.

以上に述べた様に、本発明の製造方法を採用することに
より、例えば、高画業集積のハイビジョン対応の超高精
細液晶表示装置を作製する場合でも、表示電極6・・・
の拡大形成によって、画素占有面積率が高くなるので、
表示画面が明るい高品位の表示が可能となる。また、本
発明は液晶表示装置に限定されず、ELやEC表示装置
に採用してもその製造効果は同様である。
As described above, by employing the manufacturing method of the present invention, for example, even when manufacturing an ultra-high definition liquid crystal display device compatible with high-definition with high image processing integration, the display electrodes 6...
By enlarging the pixel area, the pixel occupation area ratio increases.
A bright, high-quality display is possible on the display screen. Further, the present invention is not limited to liquid crystal display devices, and even if it is applied to EL or EC display devices, the manufacturing effect will be the same.

(ト)発明の効果 本発明のアクティブマトリクス表示装置のTPTアレー
の製造方法は、半導体膜のパターニング及び透明導電膜
のパターニングに背面露光を用いた自己整合法を用い、
さらにドレイン配線は表示電極パターニングに用いたレ
ジストによりリフトオフ形成するものであるので、7オ
トマスクの使用枚数を削減でき、これによって、フォト
マスク精度やそのアラインメント誤差に影響されず、特
に、互いに近接配置される表示電極に対して非常に高精
度のパターンニングが可能となる。従って本発明によれ
ば、高開口率の高精細のアクティブマトリクス表示装置
を得ることができる。
(G) Effects of the Invention The method for manufacturing a TPT array of an active matrix display device of the present invention uses a self-alignment method using back exposure for patterning a semiconductor film and a transparent conductive film,
Furthermore, since the drain wiring is formed by lift-off using the resist used for patterning the display electrodes, it is possible to reduce the number of 7-otomasks used, and as a result, it is not affected by photomask accuracy or alignment error, and in particular, the drain wirings are not affected by photomask accuracy or their alignment errors. This makes it possible to pattern display electrodes with extremely high precision. Therefore, according to the present invention, a high definition active matrix display device with a high aperture ratio can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の製造方法によって得られるアクティブ
マトリクス表示装置のTPTアレーの画素単位の平面図
、第2図(i)〜(vii )は第1図のTPTアレー
の製造工程をそのB−B線に沿って示す工程断面図、第
3図(ii)及び(vii )は本発明方法のさらに他
の実施例を示す工程断面図、第4図(a)及び(b)は
従来のTPTアレーの画素単位の平面図、及びそのA−
A線断面図。 1・・・透光性基板、2・・・ゲート電極部、3・・・
ゲート絶縁膜、4・・・半導体膜、5・・・不純物半導
体膜、6・・・表示電極、7・・・ソース電極、8・・
・ドレイン電極、9・・・付加容量電極、10・・・チ
ャンネル保護絶縁膜、20・・・ゲートライン、80・
・・ドレインライン。 第1図
FIG. 1 is a plan view of each pixel of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention, and FIGS. 2(i) to (vii) show the manufacturing process of the TPT array of FIG. 3(ii) and (vii) are process sectional views showing still another embodiment of the method of the present invention, and FIGS. 4(a) and (b) are process sectional views taken along line B. A plan view of each pixel of the array and its A-
A-line sectional view. DESCRIPTION OF SYMBOLS 1... Transparent substrate, 2... Gate electrode part, 3...
Gate insulating film, 4... Semiconductor film, 5... Impurity semiconductor film, 6... Display electrode, 7... Source electrode, 8...
・Drain electrode, 9... Additional capacitance electrode, 10... Channel protection insulating film, 20... Gate line, 80.
...Drain line. Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)複数のゲート配線と該ゲート配線に交差する複数
の複数のドレイン配線との多数の交差点に、表示電極と
共に薄膜トランジスタを配置し、該薄膜トランジスタの
ゲートをゲート配線に、ドレインをドレイン配線に、並
びにソースを表示電極に結合するアクティブマトリクス
表示装置の薄膜トランジスタアレーの製造方法に於て、 透光性基板上に不透明金属からなる複数本のゲート配線
を形成し、透光性のゲート絶縁膜を積層形成した後、透
明導電膜を成膜し、該透明導電膜上面にレジストを塗布
した状態で、上記ゲート配線をマスクとした背面露光に
より該ゲート配線の反転パターンをなすレジストを残存
させ、該残存レジストをマスクに上記透明導電膜をゲー
ト配線に沿って分離するパターニング処理を行い、続い
て、再度レジストを塗布し、露光処理によりドレイン配
線位置以外のレジストを残存させ、該残存レジストをマ
スクに透明導電膜をドレイン配線に沿って分離するパタ
ーニング処理を行うことにより、 画素単位の透明導電膜からなる多数の表示電極を得るこ
とを特徴としたアクティブマトリクス表示装置の薄膜ト
ランジスタアレーの製造方法。
(1) Thin film transistors are arranged together with display electrodes at numerous intersections between a plurality of gate wirings and a plurality of drain wirings that intersect with the gate wirings, the gates of the thin film transistors are used as gate wirings, the drains are used as drain wirings, In addition, in a method for manufacturing a thin film transistor array for an active matrix display device in which a source is coupled to a display electrode, a plurality of gate wirings made of opaque metal are formed on a transparent substrate, and a transparent gate insulating film is laminated. After the formation, a transparent conductive film is formed, and with a resist applied to the upper surface of the transparent conductive film, a resist forming an inverted pattern of the gate wiring is left by back exposure using the gate wiring as a mask, and the remaining resist is removed. A patterning process is performed to separate the transparent conductive film along the gate wiring using a resist as a mask. Then, a resist is applied again, the resist is left in areas other than the drain wiring position through an exposure process, and the remaining resist is used as a mask to form a transparent conductive film. A method for manufacturing a thin film transistor array for an active matrix display device, characterized in that a large number of display electrodes made of transparent conductive films are obtained in pixel units by performing a patterning process that separates a conductive film along a drain wiring.
(2)透光性基板上に第1金属によりゲート電極部を備
える複数本のゲート配線を形成する第1工程、 ゲート絶縁膜と半導体膜を成膜する第2工程、レジスト
を塗布し、ゲート電極部を備える複数本のゲート配線を
マスクとした基板背面からの露光により該ゲート配線位
置以外のレジストを感光すると共に、基板表面からの露
光処理によりゲート電極部以外のゲート配線位置のレジ
ストを感光し、ゲート電極部にアイランド状のレジスト
を残存させ、該レジストをマスクに半導体膜をパターニ
ングする第3工程、 透明導電膜を成膜した後レジストを塗布し、ゲート電極
部を備える複数本のゲート配線をマスクとした基板背面
からの露光により該ゲート配線の反転パターンをなすレ
ジストを残存させ、該残存レジストをマスクに透明導電
膜をゲート配線に沿って分離するパターニング処理を行
う第4工程、レジストを塗布し、露光処理によりドレイ
ン電極部を備える複数本のドレイン配線位置以外に対応
するレジストを残存させ、該残存レジストをマスクに透
明導電膜をドレイン配線に沿って分離するパターニング
処理を行い、画素単位の透明導電膜からなる多数の表示
電極を得る第5工程、第2金属によりドレイン電極部を
備える複数本のドレイン配線及び多数のソース電極を所
定の形状に形成する第6の工程からなるアクティブマト
リクス表示装置の薄膜トランジスタアレーの製造方法。
(2) A first step of forming a plurality of gate wirings each including a gate electrode portion using a first metal on a light-transmitting substrate, a second step of forming a gate insulating film and a semiconductor film, and applying a resist to form a gate wiring. The resist at the gate wiring positions other than the gate wiring positions is exposed by exposure from the back side of the substrate using a plurality of gate wirings having electrode parts as a mask, and the resist at the gate wiring positions other than the gate electrode parts is exposed by exposure processing from the substrate surface. The third step is to leave an island-shaped resist on the gate electrode portion and pattern the semiconductor film using the resist as a mask. After forming the transparent conductive film, a resist is applied, and a plurality of gates with the gate electrode portion are formed. A fourth step in which a resist forming an inverted pattern of the gate wiring remains by exposure from the back side of the substrate using the wiring as a mask, and a patterning process is performed to separate the transparent conductive film along the gate wiring using the remaining resist as a mask. is coated and subjected to exposure processing to leave a resist corresponding to the positions other than the positions of the plurality of drain wirings comprising the drain electrode portion. Using the remaining resist as a mask, a patterning process is performed to separate the transparent conductive film along the drain wirings, and the pixel A fifth step is to obtain a large number of display electrodes made of a single unit of transparent conductive film, and a sixth step is to form a plurality of drain wirings each having a drain electrode portion and a large number of source electrodes in a predetermined shape using a second metal. A method for manufacturing a thin film transistor array for a matrix display device.
JP33397389A 1989-12-21 1989-12-21 Method of manufacturing thin-film transistor array for active matrix display device Expired - Fee Related JP2846682B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33397389A JP2846682B2 (en) 1989-12-21 1989-12-21 Method of manufacturing thin-film transistor array for active matrix display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33397389A JP2846682B2 (en) 1989-12-21 1989-12-21 Method of manufacturing thin-film transistor array for active matrix display device

Publications (2)

Publication Number Publication Date
JPH03192730A true JPH03192730A (en) 1991-08-22
JP2846682B2 JP2846682B2 (en) 1999-01-13

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ID=18272061

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2846682B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013251557A (en) * 2006-12-22 2013-12-12 Palo Alto Research Center Inc Transistor forming method, intermediate formation for transistor, and intermediate formation for electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013251557A (en) * 2006-12-22 2013-12-12 Palo Alto Research Center Inc Transistor forming method, intermediate formation for transistor, and intermediate formation for electronic device

Also Published As

Publication number Publication date
JP2846682B2 (en) 1999-01-13

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