JPH03184322A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To use a resist film containing no dye, and to form a stable resist pattern accurately at an arbitrary position without being subject to the effect of reflected light by an aluminum wiring as a lower layer on exposure and also depending upon the variation of film thickness by forming an amorphous silicon film as an antireflection film onto an inter-layer insulating film. CONSTITUTION:When a semiconductor integrated circuit device with an aluminum wiring is manufactured, an insulating film 2 is formed onto the main surface of a semiconductor substrate 1, to which a specified element is shaped, first, the aluminum wiring 3 is formed selectively onto the insulating film 2, these insulating film 2 and aluminum wiring 3 are coated with an inter-layer insulating film 4, an amorphous silicon film 5 as an antireflection film is formed onto the whole surface of the inter-layer insulating film 4, a resist film is applied and shaped onto the amorphous silicon film 5, and at least a process in which a resist pattern 6 is formed through exposure and development through a specified exposure mask is included. The inter-layer insulating film 4 is etched selectively, and a through-hole to the first-layer aluminum wiring 3 is bored.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more specifically, for example, in manufacturing a semiconductor integrated circuit device having multilayer aluminum wiring, Regardless of the circumstances, the present invention relates to an improvement in a resist pattern forming method for accurately forming a stable resist pattern as an etching mask.

[Conventional technology]

A conventional method for manufacturing this type of semiconductor integrated circuit device,
In particular, in the manufacture of semiconductor integrated circuit devices having multilayer aluminum wiring, the outline of the method for forming a resist pattern that serves as an etching mask for through holes for connection between wiring is shown in Figures 4 to 7. show.

FIG. 4 is a schematic cross-sectional view showing the configuration at the time of forming a resist pattern when the target surface is relatively flattened during the manufacture of a conventional semiconductor integrated circuit device having multilayer wiring, and FIG. FIG. 3 is a schematic cross-sectional view showing a problem at the time of forming a resist pattern when the target surface is not flattened.

Further, FIG. 6 is a schematic cross-sectional view showing a configuration in the case where a relief measure is taken for the configuration shown in FIG. 5, and FIG. It is.

That is, first, in the method for forming a resist pattern when the surface is relatively flat as shown in FIG. A single-layer insulating film 2 is formed, and a first-layer aluminum wiring 3 is selectively formed on this insulating film 2, and then these are entirely covered with an interlayer insulating film 4 as a second-layer insulating film. Then, a resist film is spin-coated on this interlayer insulating film 4, exposed through a predetermined exposure mask, and developed to obtain a desired resist pattern 6. Although not shown, the interlayer insulating film 4 is selectively etched using the resist pattern 6 as a mask to open a through hole for the first layer aluminum wiring 3, and then the first layer aluminum wiring 3 is etched. Formation of the second layer aluminum wiring connected to 3.

Then, a third layer insulating film is applied, and finally a surface protective film is formed to complete the wafer process.

When forming the interlayer insulating film 4, an oxide film and an SO2 film are formed by plasma CVD in order to meet the demand for surface flattening that accompanies the progress of miniaturization in this type of device configuration.
G (Spin on Glass) membrane, or T EOS (Tetra-Ethyl-
An oxide film made of Orth-3 ilicatel gas is first formed.

By forming a thick layer and then etching back the entire surface, it is possible to bury wiring parts and contact holes and make the surface as flat as possible. Even if the contact hole is extremely fine and has a diameter less than Ittm, its surface can be flattened.

On the other hand, as shown in FIG. 5, for example, a gate electrode wiring 7 is formed on an inter-element isolation insulating film 8 of a semiconductor substrate 1, and a gate electrode wiring 7 is formed on a first layer insulating film 2 having a large step in that part. When the first layer aluminum wiring 3 is selectively formed and a resist pattern 6 is formed on the second layer interlayer insulating film 4 covering these, a resist film is formed using a predetermined exposure mask 9. During exposure, the light transmitted through this resist film is reflected on the surface of the lower first layer aluminum wiring 3, which is necessarily arranged in an oblique direction due to the step difference, and the resist film corresponding to the direction of reflection is reflected. The resist pattern 6 is exposed through the second interlayer insulating film 4, which causes distortion in the pattern after development, making it impossible to accurately form the resist pattern 6 with the desired dimensions and shape.

Therefore, in order to eliminate such disadvantages, in the case of the conventional method, a resist film containing a dye (dye) in the material (hereinafter referred to as a dye-containing resist film) is used. That is, when using this dye-containing resist film, the incident light during exposure is
Since the light is transmitted through the film while being attenuated by the dye contained in the material, the intensity of the light reflected on the surface of the first layer aluminum wiring 3 is sufficiently reduced, and the intensity of the light reflected on the surface of the first layer aluminum wiring 3 is sufficiently reduced. Exposure through the interlayer insulating film 4 is eliminated, and as a result, a resist pattern 6 matching or as close as possible to the original desired pattern can be obtained.

[Problems to be Solved by the Invention] However, even in the case of the method of forming a resist pattern using a resist film containing dye as described above, as shown in FIG. On the other hand, the inconvenience of increased variation in resist pattern dimensions cannot be avoided. That is, the second
In areas where the resist film coated on the interlayer insulating film 4 of the layer is thin, it is possible to obtain the desired dimensions as described above.
Even if it is possible to form a resist pattern 6 according to the shape, the light for exposure will be attenuated in this resist film in areas where the film is thick, and the dimensional controllability at the bottom of the film will deteriorate, resulting in serious problems. Sometimes the bottom of this film is not exposed and
This method has a fatal problem in that the through hole itself cannot be opened.

In other words, in the case of the conventional method of forming a resist pattern as described above, when a resist film containing dye is not used, it is possible to form a resist pattern relatively easily even if the resist film thickness changes, but the resist pattern formed There is a disadvantage that dimensional distortion is likely to occur in the dy
When using a resist film containing e, dimensional distortion does not occur in the resist pattern, but there is a contradiction in that the resist pattern may not be formed due to variations in the resist film thickness.

This invention was made in order to solve these conventional problems, and its purpose is to use a resist film that does not contain dye, and when exposing this resist film, to protect the surface of the underlying aluminum wiring. In addition, it is possible to form a stable resist pattern at any position with high accuracy without being affected by reflected light from the film, and also without being affected by variations in film thickness. A method for manufacturing this type of semiconductor integrated circuit device.

This S provides a method for forming a resist pattern.

[Means to solve the problem]

In order to achieve the above object, a method for manufacturing a semiconductor integrated circuit device according to the present invention includes forming an amorphous silicon film as an antireflection film on an interlayer insulating film before applying a resist film when forming a resist pattern. It was designed to do so.

That is, the present invention provides a method for manufacturing a semiconductor integrated circuit device having aluminum wiring, in which an insulating film is first formed on the main surface of a semiconductor substrate on which predetermined elements have been formed, and then an insulating film is formed on the insulating film. Aluminum wiring is selectively formed, then these are covered with an interlayer insulating film, an amorphous silicon film serving as an anti-reflection film is formed on the entire surface of this interlayer insulating film, and then a resist is coated on the amorphous silicon film. This method of manufacturing a semiconductor integrated circuit device includes at least the steps of coating a film, exposing it to light through a predetermined exposure mask, and developing it to form a resist pattern.

[For production]

Therefore, in the method of the present invention, an amorphous silicon film is formed as an anti-reflection film on the interlayer insulating film before the resist film is applied. Since the light that has completed the process is absorbed and attenuated by the amorphous silicon film, it is possible to eliminate the distortion of the resist pattern due to the influence of the reflected light on the surface of the underlying aluminum wiring, thereby eliminating the need to use a resist film containing dye. Even with variations in resist film thickness, a highly accurate resist pattern can be stably formed.

It is possible.

〔Example〕

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the present invention,
In this section, an embodiment of a resist pattern forming method will be described in detail with reference to FIGS. 1 to 3.

1 to 3 show different embodiments of the resist pattern forming method according to the present invention, and FIG. 1 shows a case where the target surface to which a resist film is applied is relatively flat. , FIG. 2 is a schematic cross-sectional view when the target surface is not flattened, and FIG. 3 is a schematic cross-sectional view when the resist film has a difference in thickness. In the conventional example shown in FIGS. 4 to 7, the same reference numerals indicate the same or corresponding parts.

That is, as shown in FIG. 1, in the embodiment method when the target surface is relatively flattened, the first After forming a layer insulating film 2, a first layer is formed on this insulating film 2.
Layer aluminum wiring 3 is selectively formed, and then these are covered with an interlayer insulating film 4 as a second layer insulating film, and an amorphous silicon film 5 serving as an antireflection film is formed on the entire surface of this interlayer insulating film 4. Then, a resist film is formed on this amorphous silicon film 5, and in this case, d
A resist film that does not contain ye is spin-coated, and then the desired resist pattern 6 is obtained by exposing it to light through a predetermined mask 7 and developing it in exactly the same manner as in the conventional method. After going through the process,
By using this resist pattern 6 as a mask, the interlayer insulating film 4 is selectively etched to open, for example, a through hole for the first layer aluminum wiring 3, and further,
The wafer process is completed by forming a second layer aluminum wiring connected to the first layer aluminum wiring 3, coating with a third layer insulating film, etc., and finally forming a surface protection film.

Here, regarding the interlayer insulating film 4, in this embodiment 1, for example, P E CV D (Plazma En
han-ced G:chemical vapor D
It is best to form an oxide film or SOG film using the oxidation process, an oxide film made from TEO3 gas, or a combination of these films. The gaps can be easily filled in and flattened.

Furthermore, since the amorphous silicon film 5 as the anti-reflection film is formed in a step after the formation of the first layer aluminum wiring 3, treatment at a high temperature of about 450° C. or higher should be avoided and, for example, a sputtering method or the like may be used. Formed by The amorphous silicon film 5 here is intended to attenuate the incident light and reduce the surface reflectance of the aluminum wiring 3 through the interlayer insulating film 4 during exposure of the resist film in the next step. Therefore, it is sufficient to set the film thickness to be sufficient to achieve this, that is, normally, about several 100 to 100 OA.

Next, when exposing the resist film using the exposure mask 9, since this resist film is not dyed,
The attenuation of incident light in the resist film is relatively small compared to those containing dye, and for this reason, the incident light sufficiently reaches the bottom of the resist film, and the arriving light is amorphous. The light is absorbed and scattered by the silicon film 5, and as a result, the influence of light reflection on the surface of the aluminum wiring 3 is eliminated.

Therefore, as shown in FIG. 2, even in the case where the target surface is not flattened, that is, in the case where the aluminum wiring 3 is arranged diagonally, the resulting resist pattern 6 is I'm not used to creating distortions. Furthermore, as shown in FIG. 3, even in the embodiment where the thickness of the resist film is different, the incident light sufficiently reaches the bottom of the resist film and the dimensions near the surface are Since there is little difference between the dimensions near the bottom and the through hole A where the film thickness is relatively thin, through hole B is formed where the film thickness is relatively thick. There is no difference. In other words, it is possible to obtain a highly accurate resist pattern that is stable against variations in resist film thickness and has good dimensional controllability.

In each of the above embodiments, a case has been described in which the second layer aluminum wiring is connected to the first layer aluminum wiring through a through hole in the interlayer insulating film that is opened using this resist pattern as a mask. It goes without saying that similar functions and effects can be obtained by applying the present invention to connections between wirings in upper layers.

[Effects of the Invention] As described in detail above, according to the method of the present invention, in the method for forming a resist pattern when manufacturing a semiconductor integrated circuit device having aluminum wiring, a layer is formed on an interlayer insulating film prior to coating a resist film. Since an amorphous silicon film is formed as an anti-reflection film, when exposing the resist film, the light that has passed through the film and completed its exposure action is absorbed and attenuated by the amorphous silicon film. This eliminates the distortion of the resist pattern caused by the influence of reflected light on the surface of the underlying aluminum wiring, eliminating the need to use a resist film containing dye, and creating a highly accurate resist pattern even with variations in resist film thickness. can be formed stably with good dimensional control, and structurally, it simply forms an amorphous silicon film as an antireflection film on an interlayer insulating film.
It has excellent features such as being extremely easy and simple to implement.

[Brief explanation of drawings]

1 to 3 show different embodiments of the method for forming a resist pattern according to the present invention. Fig. 2 is a schematic cross-sectional view when the target surface is not flattened, Fig. 3 is a schematic cross-sectional view when there is a difference in the thickness of the resist film, and Fig. 4 is a schematic cross-sectional view when the target surface is not flattened. A schematic cross-sectional view showing the configuration at the time of resist pattern formation when the target surface is relatively flat;
FIG. 5 is a schematic cross-sectional view showing problems at the time of resist pattern formation when the target surface is not flattened, and FIG. FIG. 7 is a schematic cross-sectional view showing another problem caused by employing the above-mentioned relief means. l... Semiconductor substrate, 2... First layer insulating film, 3
...First layer aluminum wiring, 4...Second layer interlayer insulating film, 5...Anti-reflection film, 6...Resist pattern, 7...Gate electrode wiring, 8...Insulating film for isolation between elements, 9...Mask for exposure, A...Through hole formed at a location where the resist film thickness becomes relatively thin, B...Resist film A through hole formed at a location where the thickness is relatively thick.

Claims (1)

[Claims] In a method for manufacturing a semiconductor integrated circuit device having aluminum wiring, on the main surface of a semiconductor substrate on which predetermined elements are formed,
First, an insulating film is formed, then aluminum wiring is selectively formed on this insulating film, then these are covered with an interlayer insulating film, and an anti-reflection film is formed on the entire surface of this interlayer insulating film. The method includes at least the steps of forming an amorphous silicon film, then coating and forming a resist film on the amorphous silicon film, exposing it to light through a predetermined exposure mask, and developing it to form a resist pattern. A method for manufacturing a semiconductor integrated circuit device.