JPH03178150A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH03178150A JPH03178150A JP31812389A JP31812389A JPH03178150A JP H03178150 A JPH03178150 A JP H03178150A JP 31812389 A JP31812389 A JP 31812389A JP 31812389 A JP31812389 A JP 31812389A JP H03178150 A JPH03178150 A JP H03178150A
- Authority
- JP
- Japan
- Prior art keywords
- layer wiring
- hole
- resist
- forming
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000008021 deposition Effects 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置及びその製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same.
第２図は従来の半導体装置における２層配線のコンタク
ト形状の形成方法を示す断面図であり、第２図（ａ）で
Ｓｉ等の基板１上にＳｉｎｇ等の絶縁酸化膜２を例えば
５０００人の厚さに形成する。同図（ロ）で絶縁酸化膜
２上にＡｆ、ポリシリコン、シリサイド等からなる１層
目配線４を例えば３０００〜５０００人の厚さになるよ
うにＣＶＤ法やスパッタ法等によりデポする。同図（Ｃ
）で１層目配線４上にＳｉＯ２等の層間ｗＡ縁膜５を例
えば５０００人の厚さに形成する。同図（ｄ）で層間絶
縁膜５上に例えばノボラック系のレジスト３をバターニ
ングする。同図（ｅ）でバターニングされたレジスト３
に対し、ウェットエツチング及びドライエツチングを併
用してスルーホール（コンタクトホール）６を形成する
。同図（ｆ）で１層目配線と同様の厚み、材質の２層目
配ｖＡ７をＣＶＤ法やスパッタ法等によりデポして２層
配線を形成する。FIG. 2 is a cross-sectional view showing a method of forming a contact shape of a two-layer wiring in a conventional semiconductor device. In FIG. Form to a thickness of . In the figure (b), a first layer wiring 4 made of Af, polysilicon, silicide, etc. is deposited on the insulating oxide film 2 to a thickness of, for example, 3,000 to 5,000 layers by CVD, sputtering, or the like. The same figure (C
), an interlayer wA film 5 made of SiO2 or the like is formed to a thickness of, for example, 5,000 wafers on the first layer wiring 4. In FIG. 4(d), a novolac resist 3, for example, is patterned on the interlayer insulating film 5. Then, as shown in FIG. Resist 3 patterned in the same figure (e)
On the other hand, a through hole (contact hole) 6 is formed using a combination of wet etching and dry etching. In FIG. 3F, a second layer wiring vA7 having the same thickness and material as the first layer wiring is deposited by CVD, sputtering, etc. to form a second layer wiring.
従来の半導体装置は以上のように構成されており、半導
体メモリ装置のアルくの杭打ち配線１周辺回路等に利用
されているが、２層目配線の１層目配線に対するスルー
ホール（コンタクトホール）のアスペクト比、即ち横幅
に対する高さが高くなると、スルーホールでのカバレッ
ジが悪くなるという問題点があった。Conventional semiconductor devices are configured as described above, and are used in peripheral circuits of the aluminum staked wiring 1 of semiconductor memory devices. ), that is, the height relative to the width increases, there is a problem in that the coverage in the through hole deteriorates.
この発明は上記のような従来のものの問題点を解消する
ためになされたもので、スルーホール（コンタクトホー
ル）のアスペクト比が高くなっても良好なカバレッジを
得ることのできる半導体装置及びその製造方法を得るこ
とを目的とする。This invention was made in order to solve the problems of the conventional ones as described above, and provides a semiconductor device and its manufacturing method that can obtain good coverage even if the aspect ratio of the through hole (contact hole) becomes high. The purpose is to obtain.
この発明に係る半導体装置及びその製造方法は、２層配
線において１層目配線の下地絶縁酸化膜のコンタクト部
に該当する箇所に段差部を形成して１層目配線に段差を
形成し、その上にスルーホール（コンタクトホール）を
形成することによりスルーホールのアスペクト比を低く
したものである。A semiconductor device and a method for manufacturing the same according to the present invention include forming a step portion in a second layer wiring at a location corresponding to a contact portion of a base insulating oxide film of the first layer wiring to form a step in the first layer wiring; By forming a through hole (contact hole) on the top, the aspect ratio of the through hole is lowered.
この発明における半導体装置及びその製造方法では、１
層目配線の下地酸化膜のコンタクト部に該当する箇所に
段差部を形成したので、コンタクト部の１層目配線が段
差により高くなり、コンタクト部のみ層間絶縁膜中に形
成されるコンタクトのアスペクト比が低くなり、２層目
配線のスルーホール（コンタクトホール）のカバレッジ
が改善される。In the semiconductor device and its manufacturing method according to the present invention, 1
Since a step part is formed at a location corresponding to the contact part of the underlying oxide film of the first layer wiring, the first layer wiring of the contact part becomes higher due to the step difference, and the aspect ratio of the contact formed in the interlayer insulating film only in the contact part increases. is lowered, and the coverage of through holes (contact holes) in the second layer wiring is improved.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例による半導体装置の製造方
法を示し、以下その製造方法について説明する。FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention, and the manufacturing method will be described below.
第１図（ａ）において、Ｓｔ基板上１に絶縁酸化膜２を
形成する。同図（ｂ）において絶縁酸化膜２上のスルー
ホール（コンタクトホール）に該当する部分にレジスト
３をバターニングする。同図（Ｃ）において、同図（ｂ
）で形成されたレジスト３をマスクとして絶縁酸化膜２
を酸化膜ドライエツチングによりエツチングし、例えば
１０００〜１５００人の段差を形成する。同図（２）に
おいて、同図（Ｃ）で形成された段差付絶縁酸化膜２上
に１層目配線４をデポする。In FIG. 1(a), an insulating oxide film 2 is formed on an St substrate 1. In FIG. In FIG. 2B, a resist 3 is patterned in a portion corresponding to a through hole (contact hole) on the insulating oxide film 2. As shown in FIG. In the same figure (C), the same figure (b
) is used as a mask to form an insulating oxide film 2.
is etched by oxide film dry etching to form, for example, 1,000 to 1,500 steps. In the figure (2), the first layer wiring 4 is deposited on the stepped insulating oxide film 2 formed in the figure (C).
同図（ｅ）、 （ｆ）において、１層目配＆Ｉ４上に２
層目配線との層間絶縁膜５をデポし、その後咳層間絶縁
膜５をエッチバックし、平坦性を上げる。In the same figure (e) and (f), 2
An interlayer insulating film 5 with the layer wiring is deposited, and then the interlayer insulating film 5 is etched back to improve flatness.
同図（ｇ）、（ｈ）において、層間絶縁膜５上にレジス
ト３を形成し、これを用いてスルーホール（コンタクト
ホール）６をウェットエツチングとドライエツチングを
併用して形成する。In FIGS. 3G and 5H, a resist 3 is formed on the interlayer insulating film 5, and using this, a through hole (contact hole) 6 is formed by a combination of wet etching and dry etching.
同図（ｉ）において、２層目配線７をデポして２層配線
を形成する。In the same figure (i), the second layer wiring 7 is deposited to form a second layer wiring.
なお、以上の説明で特に数値等を挙げなかったものは、
従来のものと同等の厚み、材質で構成されたものである
。In addition, in the above explanation, those that did not specifically mention numerical values, etc.
It has the same thickness and material as the conventional one.
このように、本実施例によれば、１層目配線の下地絶縁
膜に段差部を形成することで、スルーホール部の底部Ｉ
Ｉ目配線部分が底上げされるようにしたので、スルーホ
ールのアスペクト比が低くなり、２層目配線のスルーホ
ールでのコンタクトカバレッジを改善できるという効果
がある。As described above, according to this embodiment, by forming the stepped portion in the base insulating film of the first layer wiring, the bottom I of the through-hole portion
Since the bottom of the I-th wiring portion is raised, the aspect ratio of the through hole is lowered, and the contact coverage in the through hole of the second layer wiring can be improved.
以上のように、この発明に係る半導体装置及びその製造
方法によれば、１層目配線のコンタクト部に該当する部
分に段差をつけたので、スルーホール（コンタクトホー
ル）のアスペクト比が低くなり、２層目配線のスルーホ
ールでのカバレッジがよくなるという効果がある。As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, since the step is provided in the portion corresponding to the contact portion of the first layer wiring, the aspect ratio of the through hole (contact hole) is lowered, This has the effect of improving the coverage of the through holes of the second layer wiring.
第１図はこの発明の一実施例による半導体装置の製造方
法を示す断面図、第２図は従来の半導体装置の製造方法
を示す断面図である。
図において、ｌはＳｉ基板、２は絶縁酸化膜、３はレジ
スト、４は１層目配線、５は層間絶縁膜、６はスルーホ
ール（コンタクトホール）、’Ｎ；！２層目配線である
。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional method for manufacturing a semiconductor device. In the figure, l is a Si substrate, 2 is an insulating oxide film, 3 is a resist, 4 is a first layer wiring, 5 is an interlayer insulating film, 6 is a through hole (contact hole), 'N;! This is the second layer wiring. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (2)
線の下地絶縁膜に段差を形成して１層目配線に段差を形
成し、 該段差による高い部分上の層間絶縁膜にコンタクトホー
ルを形成し、 該コンタクトホールを介して上記１層目配線と２層目配
線とのコンタクトを得るようにしたことを特徴とする半
導体装置。(1) In a semiconductor device having two-layer wiring, a step is formed in the underlying insulating film of the first-layer wiring to form a step in the first-layer wiring, and a contact hole is formed in the interlayer insulating film on the high part due to the step. A semiconductor device characterized in that the first layer wiring and the second layer wiring are formed in contact with each other through the contact hole.
縁酸化膜上の所定位置にレジストをパターニングする工
程と、 上記レジストをマスクとして上記絶縁酸化膜をエッチン
グし段差を形成する工程と、 その上にデポジションにより１層目配線を形成する工程
と、 その上にデポジションにより層間絶縁膜を形成する工程
と、 該層間絶縁膜をエッチングにより平坦化する工程と、 その上にレジストを形成し、これをマスクとしてスルー
ホールをエッチングする工程と、 その上にデポジションにより２層目配線を形成する工程
とを備えたことを特徴とする半導体装置の製造方法。(2) A method for manufacturing a semiconductor device, which includes: forming an insulating oxide film on a silicon substrate, patterning a resist at a predetermined position on the insulating oxide film, and etching the insulating oxide film using the resist as a mask. a step of forming a step, a step of forming a first layer interconnection by deposition on the step, a step of forming an interlayer insulating film thereon by deposition, and a step of planarizing the interlayer insulating film by etching. A method for manufacturing a semiconductor device, comprising: forming a resist on the resist, etching a through hole using the resist as a mask, and forming a second layer wiring on the resist by deposition. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31812389A JPH03178150A (en) | 1989-12-06 | 1989-12-06 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31812389A JPH03178150A (en) | 1989-12-06 | 1989-12-06 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03178150A true JPH03178150A (en) | 1991-08-02 |
Family
ID=18095758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31812389A Pending JPH03178150A (en) | 1989-12-06 | 1989-12-06 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03178150A (en) |
-
1989
- 1989-12-06 JP JP31812389A patent/JPH03178150A/en active Pending
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