JP4354676B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Semiconductor integrated circuit and manufacturing method thereof Download PDF

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JP4354676B2
JP4354676B2 JP2002217631A JP2002217631A JP4354676B2 JP 4354676 B2 JP4354676 B2 JP 4354676B2 JP 2002217631 A JP2002217631 A JP 2002217631A JP 2002217631 A JP2002217631 A JP 2002217631A JP 4354676 B2 JP4354676 B2 JP 4354676B2
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Prior art keywords
protective film
film
protective
opening
integrated circuit
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Expired - Fee Related
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JP2002217631A
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Japanese (ja)
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JP2004063609A (en
Inventor
哲郎 塩浦
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Seiko Instruments Inc
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Seiko Instruments Inc
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Description

【０００１】
【産業上の利用分野】
この発明は半導体集積回路、特にバンプ工程を有する半導体集積回路に関するものである。
【０００２】
【従来の技術】
図３は、従来の半導体集積回路の一例を示している。従来の半導体集積回路は、半導体基板１上に絶縁膜２を挟んで形成したアルミニウムなどからなる金属配線３と、アルミニウムなどからなるパッド４と、シリコン窒化膜などからなる第１保護膜５より構成されている。保護膜５には、パッド4上が開口されている保護膜開口部７が形成されている。第１保護膜５は、リソグラフィー技術にてレジストをパターンニングし、エッチング技術を用いてパッド４上の保護膜が除去され、保護膜開口部７が形成される。
【０００３】
金属配線３の間隔は、フォトリソグラフィー技術や高耐圧特性などの許す範囲で狭くすることで、半導体集積回路の面積増大を防いでいる。ここで第１保護膜５には、 該金属配線３など下層の段差を反映した段差が生じる。 また第１保護膜5はＣＶＤ法にて形成されるのが一般的であるが、 ＣＶＤ法で形成された場合には、配線が隣接したような箇所において保護膜自身のオーバーハングにより空洞８が形成されていた。
【０００４】
【発明が解決しようとする課題】
前述の従来技術においては、リソグラフィー技術で保護膜開口部７をパターンニングする時、第１保護膜５表面に生じた段差部や空洞８の中に侵入したレジストが完全に取りきれずに残ったり、パッド４上に図示しないバンプを設ける工程において、バンプ下に用いる金属膜残りが発生し、好ましくなかった。
【０００５】
【課題を解決するための手段】
上記課題を解決するために、本発明では保護膜を形成した後、保護膜表面を平坦にするものである。
【０００６】
上述した工程によって保護膜表面の段差が無くなり、保護膜開口部形成工程でのレジストや、バンプ工程における金属膜が残らないようにできる。
【０００７】
【実施例】
図1は本発明の実施例を示す断面構造図である。図1において、半導体基板１上に絶縁膜２を挟んでアルミニウムなどの金属配線３が所望の形状に形成されている。また、絶縁膜２上にアルミニウムなどからなるパッド４が形成されている。更にそれらの上に、ＣＶＤ法によりシリコン酸化膜やシリコン窒化膜などからなる第１保護膜５が形成されている。パッド４上の第１保護膜5には、保護膜開口部７が形成されている。第１保護膜５の表面は、パターニングされた金属配線３及びパッド４の厚さにより、図１に示すような凹凸（空洞）が形成されることになる。更に、表面が平坦化されたシリコン酸化膜などからなる第２保護膜６が構成されている。第１保護膜5のパッド４上は、保護膜開口部７が形成されている。簡単のため半導体素子などは省略する。第２保護膜6は、第１保護膜５の表面の凹凸を平坦にするもので、第１保護膜5の凹部は厚く、凸部は薄く形成されている。この構成によれば、保護膜開口部７形成工程でのレジストや、その後のバンプ工程における金属膜が第２保護膜6の表面に残らないようにできる。
【０００８】
図２は本発明の実施例を示す半導体集積回路の製造方法である。図２（ａ）は、半導体基板１上に絶縁膜２を挟んで、パターニングされた金属配線３及びパッド４を形成し、その上にＣＶＤ法で形成されたシリコン窒化膜などからなる第１保護膜５を設ける。更にその上に、シリコン酸化膜などの第２保護膜６を形成する工程を示すものである。第２保護膜６は、第１保護膜５に比べ、厚く形成される。
【０００９】
次のに、図２（ｂ）に示したのは、前記第１保護膜５及び第２保護膜６を、ケミカルメカニカルポリッシング（ＣＭＰ）装置などを用いて平坦にする工程である。第２保護膜６の凸部が除去され、表面は平坦になる。
【００１０】
更に次に、図２（ｃ）に示したのは、図示しないマスクを用いて、パッド４上の第１及び第２保護膜５、６を除去し、開口部７を形成する工程である。
【００１１】
以上の製造方法によれば、保護膜表面の段差を無くすことができる。
【００１２】
【発明の効果】
以上説明したように、本発明では最終保護膜表面の段差や空洞を埋めて平坦化することによって、半導体集積回路の最終保護膜上に外観不良を無くす効果がある。
【図面の簡単な説明】
【図１】図1は、本発明の半導体集積回路の断面構造図である。
【図２】図２は本発明の半導体集積回路の工程順を示す断面構造図である。
【図３】図３は、従来の半導体集積回路の断面構造図である。
【符号の説明】
１ 半導体基板
２ 絶縁膜
３ 金属配線
４ パッド
５ 第１保護膜
６ 第２保護膜
７ 保護膜開口部
８ 空洞[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a bump process.
[0002]
[Prior art]
FIG. 3 shows an example of a conventional semiconductor integrated circuit. A conventional semiconductor integrated circuit includes a metal wiring 3 made of aluminum or the like formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween, a pad 4 made of aluminum or the like, and a first protective film 5 made of a silicon nitride film or the like. Has been. In the protective film 5, a protective film opening 7 having an opening on the pad 4 is formed. The first protective film 5 is formed by patterning a resist using a lithography technique, and the protective film on the pad 4 is removed using an etching technique to form a protective film opening 7.
[0003]
The space between the metal wirings 3 is narrowed within a range allowed by photolithography technology, high breakdown voltage characteristics, and the like, thereby preventing an increase in the area of the semiconductor integrated circuit. Here, the first protective film 5 has a level difference reflecting the level difference of the lower layer such as the metal wiring 3. The first protective film 5 is generally formed by the CVD method. However, when the first protective film 5 is formed by the CVD method, the cavity 8 is formed due to an overhang of the protective film itself at a place where the wiring is adjacent. Was formed.
[0004]
[Problems to be solved by the invention]
In the above-described prior art, when patterning the protective film opening 7 by the lithography technique, the stepped portion formed on the surface of the first protective film 5 or the resist that has entered the cavity 8 cannot be completely removed and remains. In the step of providing a bump (not shown) on the pad 4, a metal film residue used under the bump is generated, which is not preferable.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention flattens the surface of the protective film after forming the protective film.
[0006]
The steps described above eliminate the step on the surface of the protective film, so that the resist in the protective film opening forming process and the metal film in the bump process are not left.
[0007]
【Example】
FIG. 1 is a sectional structural view showing an embodiment of the present invention. In FIG. 1, a metal wiring 3 made of aluminum or the like is formed in a desired shape on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. A pad 4 made of aluminum or the like is formed on the insulating film 2. Furthermore, a first protective film 5 made of a silicon oxide film, a silicon nitride film, or the like is formed thereon by CVD. A protective film opening 7 is formed in the first protective film 5 on the pad 4. On the surface of the first protective film 5, irregularities (cavities) as shown in FIG. 1 are formed depending on the thickness of the patterned metal wiring 3 and pad 4. Furthermore, a second protective film 6 made of a silicon oxide film having a planarized surface is formed. A protective film opening 7 is formed on the pad 4 of the first protective film 5. For simplicity, the semiconductor elements are omitted. The second protective film 6 is for flattening the unevenness of the surface of the first protective film 5, and the concave portion of the first protective film 5 is thick and the convex portion is thin. According to this configuration, it is possible to prevent the resist in the protective film opening 7 forming process and the metal film in the subsequent bump process from remaining on the surface of the second protective film 6.
[0008]
FIG. 2 shows a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 2A, a patterned metal wiring 3 and a pad 4 are formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween, and a first protection composed of a silicon nitride film or the like formed thereon by a CVD method. A membrane 5 is provided. Further, a process of forming a second protective film 6 such as a silicon oxide film thereon is shown. The second protective film 6 is formed thicker than the first protective film 5.
[0009]
Next, FIG. 2B shows a step of flattening the first protective film 5 and the second protective film 6 using a chemical mechanical polishing (CMP) apparatus or the like. The convex portion of the second protective film 6 is removed, and the surface becomes flat.
[0010]
Next, FIG. 2C shows a process of forming the opening 7 by removing the first and second protective films 5 and 6 on the pad 4 using a mask (not shown).
[0011]
According to the above manufacturing method, a step on the surface of the protective film can be eliminated.
[0012]
【The invention's effect】
As described above, the present invention has the effect of eliminating appearance defects on the final protective film of the semiconductor integrated circuit by filling and leveling the steps and cavities on the surface of the final protective film.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a cross-sectional structure diagram showing a process sequence of the semiconductor integrated circuit of the present invention.
FIG. 3 is a cross-sectional structure diagram of a conventional semiconductor integrated circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Metal wiring 4 Pad 5 1st protective film 6 2nd protective film 7 Protective film opening part 8 Cavity

Claims (2)

半導体基板上に設けられた絶縁膜と、該絶縁膜上に接近して設けられた複数の金属配線と、該複数の金属配線上に設けられた保護膜と、該複数の金属配線のうちの特定の該金属配線上のみに設けられた該保護膜の開口部と、該開口部に設けられたバンプとからなる半導体集積回路において、該保護膜は該金属配線などによる下層の段差を反映した凹凸の段差が生じている第１保護膜と、該凹凸の上に、該第１保護膜の凹部は厚く、凸部は薄くなるように平坦化されて形成された最上層となる第２保護膜とから構成され、該開口部の側壁が該第１保護膜と該第２保護膜との２層膜からなる半導体集積回路。An insulating film provided on a semiconductor substrate, a plurality of metal wires provided close on the insulating film, and a protective film provided on said plurality of metal wirings, of the plurality of metal wires In a semiconductor integrated circuit including an opening of the protective film provided only on the specific metal wiring and a bump provided in the opening, the protective film reflects a lower step due to the metal wiring or the like. a first protective film unevenness of step is formed, on the said irregularities, recesses of the first protective layer is thick, the convex portion and the second protection is the top layer which is formed is planarized to be thinner is composed of a film, the semiconductor integrated circuit side wall of the opening is made of a two-layered film of the first protective layer and said second protective layer. 半導体基板上に設けられた絶縁膜と、該絶縁膜上に接近して設けられた複数の金属配線と、該複数の金属配線上に設けられた２層の保護膜と、該複数の金属配線のうちの特定の該金属配線上のみに設けられた該２層の保護膜の開口部と、該開口部に設けられたバンプとからなる半導体集積回路の製造方法であって、
前記半導体基板上に前記接近した複数の金属配線及びパッドが形成された面に、シリコンチッ化膜を前記金属配線などによる下層の段差を反映した凹凸の段差を有する第１保護膜として形成する工程と、
前記第１保護膜上にシリコン酸化膜からなる最上層となる第２保護膜を、前記第１保護膜に比べて膜厚を厚く形成する工程と、
前記第２保護膜の表面をケミカルメカニカルポリッシングにより、前記第２保護膜表面が平坦になるまで研磨する工程と、
前記パッド部上の前記第１及び第２保護膜を除去し、側壁が前記第１保護膜と前記第２保護膜との２層膜からなる前記開口部を設ける工程と、
前記開口部にバンプを形成する工程とからなる半導体集積回路の製造方法。 An insulating film provided on a semiconductor substrate, a plurality of metal wirings provided close to the insulating film, a two-layer protective film provided on the plurality of metal wirings, and the plurality of metal wirings A method of manufacturing a semiconductor integrated circuit comprising: an opening portion of the two-layer protective film provided only on the specific metal wiring of the semiconductor device; and a bump provided in the opening portion,
Forming on said semiconductor plurality of metal wires and pads the close was formed on the substrate surface, a first protective film having the step of irregularities The silicon nitride film reflecting the underlying steps due the metal wiring When,
Forming a second protective film, which is an uppermost layer made of a silicon oxide film, on the first protective film so as to be thicker than the first protective film;
Polishing the surface of the second protective film by chemical mechanical polishing until the surface of the second protective film becomes flat;
Removing the first and second protective films on the pad, and providing the opening having a sidewall formed of a two-layer film of the first protective film and the second protective film ;
A method of manufacturing a semiconductor integrated circuit comprising a step of forming a bump in the opening.
JP2002217631A 2002-07-26 2002-07-26 Semiconductor integrated circuit and manufacturing method thereof Expired - Fee Related JP4354676B2 (en)

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