JP2001345381A5

JP2001345381A5 -

Info

Publication number: JP2001345381A5
Application number: JP2000165781A
Authority: JP
Filing date: 2000-06-02
Publication date: 2005-01-13

Description

【０００６】
さらに、このコーナー部の発生を解消すべく、絶縁膜上にＳＯＧ膜を塗布しベークすることによって、絶縁膜を平坦化する方法も考え得るが、前述のごとく最上層配線は、膜厚が大きいため配線間の絶縁膜の膜厚が局所的に大きくなり、この部分における膜応力により、クラックを生じさせ得る。特開平９−２４６３７７号公報にはタングステン配線上に高密度プラズマにより絶縁膜を形成する開示がある。特開平１０−１６３１９２号公報には配線上にフッ素添加絶縁膜を高密度プラズマＣＶＤ法により形成する開示がある。特開平１１−１５４６７３号公報には配線上に高周波高密度プラズマＣＶＤ法により絶縁膜を形成したのち低周波高密度プラズマＣＶＤ法により絶縁膜を埋め込む開示がある。特開平１１−３４０２２１号公報には配線上に高密度プラズマＣＶＤで絶縁膜を形成した後に配線間を高密度プラズマＣＶＤ法により埋め込む開示がある。特開平９−２６６２０７号公報には配線上を酸化膜で覆った後Ｆ含有絶縁膜を高密度プラズマＣＶＤ法により形成する開示がある。 [0006]
Furthermore, in order to eliminate the occurrence of this corner portion, it is conceivable to planarize the insulating film by applying and baking an SOG film on the insulating film, but as described above, the thickness of the uppermost layer wiring is large. As a result, the film thickness of the insulating film between the interconnections locally increases, and a film stress in this portion can cause a crack. JP-A-9-246377 discloses that an insulating film is formed on a tungsten wiring by high density plasma. JP-A-10-163192 discloses that a fluorine-added insulating film is formed on a wiring by high density plasma CVD. Japanese Patent Application Laid-Open No. 11-154673 discloses that an insulating film is formed on a wiring by high frequency high density plasma CVD and then embedded by a low frequency high density plasma CVD. JP-A-11-340221 discloses that after forming an insulating film on a wiring by high density plasma CVD, the space between the wirings is embedded by high density plasma CVD. Japanese Patent Application Laid-Open No. 9-266207 discloses that an F-containing insulating film is formed by high density plasma CVD after the wiring is covered with an oxide film.

Claims

(A) forming an element on the main surface of the semiconductor substrate;
(B) forming a first insulating film on the device;
(C) forming a conductive layer on the first insulating film and patterning it into a desired shape to form a wiring layer;
(D) after forming a silicon nitride film by a plasma CVD method to the wiring layer, by depositing a third insulating film to a high-density plasma CVD method, the second has a tapered shape on the wiring layer end Forming a third insulating film, and then forming a fourth insulating film on the third insulating film by plasma CVD .
A method of manufacturing a semiconductor integrated circuit device, comprising:

(A) forming an element on the main surface of the semiconductor substrate;
(B) forming a first insulating film on the device;
(C) forming a conductive layer on the first insulating film and patterning it into a desired shape to form a wiring layer;
(D) forming a silicon oxide film as a second insulating film on the wiring layer by plasma CVD;
(E) by depositing by the high-density plasma CVD method, a silicon oxide film on the second insulating film as the third insulating film, the third insulating film having a tapered shape on the wiring layer end Forming a silicon oxide film as a fourth insulating film on the third insulating film by plasma CVD method ;
A method of manufacturing a semiconductor integrated circuit device, comprising:

(A) forming an element on the main surface of the semiconductor substrate;
(B) forming a first insulating film on the device;
(C) forming a conductive film made of a laminated film of titanium nitride, aluminum, and titanium nitride on the first insulating film , and patterning it into a desired shape to form a low resistance wiring;
(D) forming a silicon nitride film as a second insulating film on the low resistance wiring by a plasma CVD method;
(E) by depositing by the high-density plasma CVD method, a silicon oxide film on the second insulating film as the third insulating film, the third insulating film having a tapered shape on the wiring layer end Forming a silicon oxide film as a fourth insulating film on the third insulating film by plasma CVD method ;
A method of manufacturing a semiconductor integrated circuit device, comprising:

(A) forming an element on the main surface of the semiconductor substrate;
(B) forming a plurality of layers of wiring electrically connected to the device;
(C) forming a silicon nitride film as a first insulating film by plasma CVD on the uppermost layer wiring among the plurality of wiring layers;
(D) forming an insulating film on the first insulating film by high density plasma CVD to form a second insulating film having a tapered shape on the end of the wiring layer;
A method of manufacturing a semiconductor integrated circuit device, comprising:

(A) forming an element on the main surface of the semiconductor substrate;
(B) forming a plurality of layers of wiring electrically connected to the device;
(C) forming a first insulating film by plasma CVD on the uppermost layer wiring among the plurality of layers of wiring;
(D) forming an insulating film on the first insulating film by high density plasma CVD to form a second insulating film having a tapered shape on the end of the wiring layer;
(E) exposing the surface of the uppermost layer wiring by etching the first and second insulating films;
(F) forming a base electrode on the exposed portion of the uppermost layer wire;
(G) forming a bump electrode on the base electrode on the exposed portion of the uppermost layer wiring;
A method of manufacturing a semiconductor integrated circuit device, comprising: