JP2001345381A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which can mitigate a stress to be applied to an interlayer insulation film and decrease cracks to occur in the interlayer insulation film. SOLUTION: After a silicon nitride film 29 is deposited on an uppermost layer wiring layer 28 by a plasma CVD method, a silicon oxide film 30 is deposited by a high-density plasma CVD method, whereby a silicon oxide film having a tapered shape is formed on an end part of the uppermost layer wiring layer 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to formation of an insulating film on a metal wiring.

[0002]

2. Description of the Related Art In recent years, with the increasing integration of LSIs, a multilayer wiring structure in which wirings and insulating films are repeatedly formed has been adopted.

As the uppermost layer wiring, a thick film wiring such as a power supply wiring is formed, and a CCB bump electrode is formed on the uppermost layer wiring. This CCB
In the bump electrode, first, an insulating film formed on the uppermost layer wiring is opened, and a base metal film such as a CrNiAu (chromium, nickel, gold) film is formed on the insulating film including the inside of the opening. Formed on top.

[0004]

However, as the number of wiring layers increases, cracks tend to occur in the interlayer insulating film.
When a crack occurs, moisture or the like enters through the crack, causing corrosion of the wiring and reducing the reliability of the LSI.

In particular, in the above-mentioned CCB structure, CrN is formed on the insulating film in order to improve the adhesion to the CCB bump.
Although an iAu film is formed, the CrNiAu film has a large stress, and may cause cracks at corners of a lower insulating film during film formation.

Further, in order to eliminate the corner portion, a method of applying an SOG film on the insulating film and baking the same to flatten the insulating film can be considered. Since the thickness is large, the thickness of the insulating film between the wirings locally increases, and cracks may be generated due to the film stress in this portion.

An object of the present invention is to provide a technique capable of relaxing stress applied to an interlayer insulating film and reducing the occurrence of cracks generated in the interlayer insulating film.

Another object of the present invention is to provide a technique for improving the reliability of an LSI.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming an element on a main surface of a semiconductor substrate; and (b) forming a first insulating film on the element. (C) forming a conductive film on the first insulating film and patterning it into a desired shape to form a wiring layer; and (d) forming a second insulating film on the wiring layer. Forming a second insulating film having a tapered shape on the end of the wiring layer by depositing the second insulating film by high-density plasma CVD.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming an element on a main surface of a semiconductor substrate; and (b) forming a first insulating film on the element. (C) forming a conductive film on the first insulating film and patterning it into a desired shape to form a wiring layer; and (d) forming a second insulating film on the wiring layer. CV
Forming a third insulating film on the second insulating film by a high-density plasma CVD method to form a third insulating film having a tapered shape on the end of the wiring layer; Forming an insulating film.

(3) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of (a) forming an element on a main surface of a semiconductor substrate, and (b) forming a first insulating film on the element. (C) forming a conductive film on the first insulating film and patterning it into a desired shape to form a low-resistance wiring; and (d) forming a second resistance wiring on the low-resistance wiring. (E) forming a third insulating film on the second insulating film by a high-density plasma CVD method to form a tapered shape on the end of the wiring layer; Forming a third insulating film.

(4) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming an element on a main surface of a semiconductor substrate; and (b) forming a plurality of layers electrically connected to the element. Forming a wiring, (c) forming a first insulating film on the uppermost wiring of the plurality of wirings by a CVD method, and (d) forming an insulating film on the first insulating film. Forming a second insulating film having a tapered shape on the end of the wiring layer by depositing a film by a high-density plasma CVD method.

(5) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming an element on a main surface of a semiconductor substrate; and (b) forming a plurality of layers electrically connected to the element. Forming a wiring, (c) forming a first insulating film on the uppermost wiring of the plurality of wirings by a CVD method, and (d) forming an insulating film on the first insulating film. Forming a second insulating film having a tapered shape on the end of the wiring layer by depositing a film by high-density plasma CVD, and (e) etching the first and second insulating films. (F) forming a base electrode on the exposed portion of the uppermost layer wiring; and (g) forming a base electrode on the exposed portion of the uppermost layer wiring. Forming a bump electrode.

According to the above means, the second insulating film having a tapered shape is formed on the end of the wiring layer by depositing the second insulating film on the wiring layer by the high-density plasma CVD method. In addition, the stress applied to the insulating film can be reduced, and the occurrence of cracks in the insulating film can be reduced. Further, the reliability of the LSI can be improved.

Furthermore, if an insulating film on the uppermost wiring is deposited by a high-density plasma CVD method and an insulating film having a tapered shape is formed on the end of the wiring layer, the formation of a base electrode and the formation of a bump electrode thereafter Accordingly, even if stress is applied to the insulating film, these stresses can be relieved, and the occurrence of cracks in the insulating film can be reduced.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Next, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described. 1 to 3
FIG. 3 is a sectional view of a main part showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

First, as shown in FIG.
An element isolation groove 2 having a depth of about 350 nm is formed by etching a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about Ωcm.

Thereafter, the substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the groove. Next, CVD (Chemical Vapor deposition) is performed on the substrate 1 including the inside of the groove.
A silicon oxide film 7 having a thickness of about 450 to 500 nm is deposited by a method, and is subjected to chemical mechanical polishing (CMP).
Polishing) is performed to polish the silicon oxide film 7 on the upper portion of the groove, and the surface thereof is flattened.

Next, after p-type impurities (boron) and n-type impurities (for example, phosphorus) are ion-implanted into the substrate 1,
By diffusing the impurities by heat treatment at about 1000 ° C. to form p-type well 3 and n-type well 4, a film is formed on each surface of p-type well 3 and n-type well 4 by thermal oxidation at about 800 ° C. A clean gate oxide film 8 having a thickness of about 6 nm is formed.

Next, phosphorus (P) is formed on the gate oxide film 8.
A low-resistance polycrystalline silicon film 9a with a thickness of about 100 nm is deposited by CVD, and a WN film (not shown) with a thickness of about 10 nm and a W film with a thickness of about 50 nm are formed thereon by sputtering. 9c and C on top of it.
A silicon nitride film 10 having a thickness of about 200 nm is deposited by the VD method.

Next, the silicon nitride film 10 is dry-etched using a photoresist film (not shown) as a mask, leaving the silicon nitride film 10 in a region where a gate electrode is to be formed, and using the silicon nitride film 10 as a mask. W film 9c, WN film (not shown) and polycrystalline silicon film 9a
Is dry etched to form a gate electrode 9 composed of a polycrystalline silicon film 9a, a WN film and a W film 9c.

Next, the p-type wells 3 on both sides of the gate electrode 9 are formed.
An n ⁻ -type semiconductor region 11 is formed by ion-implanting an n-type impurity (phosphorus) into the n-type well 4, and a p-type impurity (boron) is ion-implanted into the n-type well 4.
^- -type semiconductor region 12.

Next, a silicon nitride film having a thickness of about 50 nm is deposited on the substrate 1 by the CVD method, and is etched anisotropically to form a sidewall spacer 13 on the side wall of the gate electrode 9.

Next, an n ⁺ -type semiconductor region 14 (source, drain) is formed by ion-implanting an n-type impurity (phosphorous or arsenic) into the p-type well 3, and a p-type impurity (boron) is formed in the n-type well 4. Is ion-implanted to form ap ⁺ type semiconductor region 15 (source, drain). Up to this point, LDD (Lightly DopedDr
ain) n-channel type MI with source and drain
An SFET Qn and a p-channel MISFET Qp are formed.

Subsequently, a silicon oxide film 16 having a thickness of about 700 nm to 800 nm is deposited on the gate electrode 9 by the CVD method, and the silicon oxide film is polished by the CMP method to planarize the surface, thereby forming an interlayer insulating film. A film 16 is formed.

Next, a photoresist film is formed on the interlayer insulating film 16 (not shown), and the interlayer insulating film 16 is etched using the photoresist film as a mask, thereby forming the n ⁺ type semiconductor on the main surface of the semiconductor substrate 1. A contact hole 17 is formed on the region 14 and the p ⁺ type semiconductor region 15.

Next, a tungsten film is deposited on the interlayer insulating film 16 including the inside of the contact hole 17 by CVD, and the tungsten film is polished by CMP (Chemical Mechanical Polishing) until the interlayer insulating film 16 is exposed. Thereby, a plug 18 is formed in the contact hole 17. Next, a titanium nitride film (not shown), an aluminum film and a titanium nitride film (not shown) are formed on the interlayer insulating film 16 and the plug 18 by sputtering.
Are sequentially deposited and patterned into a desired shape, thereby forming the first layer wiring 20.

Next, an interlayer insulating film 21 is formed on the first layer wiring 20.
To form The interlayer insulating film 21 is formed in the same manner as the interlayer insulating film 16. Thereafter, a contact hole 22 is formed in the interlayer insulating film 21, and a plug 23 is formed in the contact hole 22. This plug 23 is
It is formed in the same manner. Next, a second layer wiring 24 is formed on the interlayer insulating film 21 and the plug 23 in the same manner as the first layer wiring.

Next, an interlayer insulating film 25 is formed in the same manner as the interlayer insulating films 16 and 21, and a plug 27 is formed in the same manner as the plugs 18 and 23. Next, a third layer wiring 28 is formed on the interlayer insulating film 25 and the plug 27. This third layer wiring is also formed by sequentially depositing a titanium nitride film, an aluminum film and a titanium nitride film by a sputtering method and patterning them into a desired shape, similarly to the first layer and the second layer wiring. However, since the third layer wiring is a power supply wiring, it has a thickness (about 1 to 3 μm) about twice as large as the first and second layer wirings in order to reduce the resistance. FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1. As shown in FIG. 2, a plurality of third layer wirings 28 are formed on the interlayer insulating film 25.

Next, an insulating film is formed on the third layer wiring which is to be the uppermost layer wiring, an opening is formed on the bonding pad BP on the uppermost layer wiring (third layer wiring) 28, and a base electrode is formed on the opening. The steps up to the formation of the bump electrode will be described in detail with reference to FIGS. 3 and 4.

FIG. 3A is a partially enlarged view of the vicinity of the uppermost layer wiring in FIG. As shown in FIG. 3A, a plasma CVD (hereinafter referred to as PC) is formed on the uppermost layer wiring (third layer wiring) 28.
VD) method so that the silicon nitride film 29 has a thickness of 0.1 to 1.0.
Deposit about μm. At this time, in the P-CVD method, a shape reflecting the step due to the uppermost layer wiring (third layer wiring) 28 is reflected, so that the uppermost layer wiring 28 is formed on the silicon nitride film 29.
(See FIG. 3 (a)).
Part A) surrounded by a broken line inside. The silicon nitride film 2
9 may be a TEOS film made of tetraethoxysilane formed by a P-CVD method.

Next, a silicon oxide film 30 is deposited on the silicon nitride film 29 by high density plasma CVD (hereinafter referred to as HDP-CVD) to a thickness of about 0.5 to 2.0 μm.

Here, the HDP-CVD means a low pressure
CVD performed in a high electron density atmosphere
In P-CVD, the pressure is 1 to 10 Torr and the electron density is 1 ×
10 ⁹~ 1 × 10^TenIs processed by HDP
-In CVD, the pressure is 0.001 to 0.01 Torr,
Density is 1 × 10¹²The processing is performed as described above.

Therefore, simultaneously with the deposition of the film forming component (in this case, silicon oxide), etching by high-density plasma occurs simultaneously.

As a result, the silicon oxide film deposited by the HDP-CVD method has a tapered shape on the corner portion on the silicon nitride film 29 (portion A surrounded by a broken line in FIG. 3A).

Next, a TEOS film 31 made of tetraethoxysilane is formed on the silicon oxide film by a P-CVD method.
To form At this time, since the corner of the silicon nitride film 29 on the HDP-CVD silicon oxide film 30 serving as a base is tapered, the tapered shape is reflected, and the corner of the silicon nitride film 29 of the TEOS film 31 is reflected. The upper part has a tapered shape. The TEOS film 31
May be a silicon nitride film formed by a P-CVD method.

Therefore, according to the present embodiment, TEOS
On the surface of the film 31, as shown in FIG. 3B, generation of a steep step S and a corner B caused when a single P-CVD silicon oxide film 129 is formed on the uppermost wiring 28. Can be avoided, the insulating film (silicon nitride film 29, HDP-CVD silicon oxide film 30, TE film
Cracks in the OS film 31) can be reduced.

Next, as shown in FIG. 4, a chromium film, a nickel film and a gold film are sequentially deposited, and a base electrode 40 composed of these three layers is formed. At this time, the base electrode 40 other than the bump electrode contact area is removed by etching. The base electrode 40 is formed in order to improve the adhesion between the later-described CCB bump electrode 41 and the uppermost layer wiring 28.

Subsequently, a CCB bump electrode is formed on the base electrode. CCB bump electrode is lead Pb (lead) / Sn
(Tin) or Sn (tin) / Ag (silver) solder, and is formed by a method such as ball transfer or screen printing.

Thereafter, the semiconductor substrate 1 in a wafer state is diced, divided into a plurality of chips, and mounted on the upper surface of the package substrate. For example, as shown in FIG. 5, the chip 1 is face-down bonded on the package substrate 51, and the bump electrodes 41 are heated and reflowed. A pad electrode 52 is formed on the mounting surface of the package substrate 51 and on the back surface thereof.
The bump electrode 41 on the chip 1 is mounted so as to abut. The underfill resin 53 between the chip 1 and the package substrate 51 may be filled.

As described above, according to the present embodiment, after the silicon nitride film is deposited on the wiring by the P-CVD method, and then the silicon oxide film is deposited by the HDP-CVD method, Since the upper silicon oxide film 30 can be formed in a tapered shape and steep steps and corners can be avoided, the occurrence of cracks in the insulating film can be reduced. Therefore, a base electrode and a CCB bump electrode are further formed, and the stress of the metal film constituting the base electrode and C
Even if stress is applied during the formation of the CB bump electrode, the occurrence of cracks in the insulating film can be reduced.

The HDP-CV is directly formed on the uppermost wiring layer.
Although it is possible to form a D silicon oxide film, as described above, in HDP-CVD, a film-forming component (in this case, silicon oxide) is deposited and etching by high-density plasma occurs simultaneously. In the initial stage of film formation, the uppermost wiring surface may be etched.

Therefore, if the silicon nitride film 29 is formed on the wiring layer in advance, the uppermost wiring surface can be prevented from being etched.

Further, the CCB bump electrode may be formed on the HDP-CVD silicon oxide film without forming the P-CVD TEOS film. However, since the TEOS film has excellent moisture resistance, such a film is formed. The entry of moisture can be prevented.

In this embodiment, the HDP-CVD silicon oxide film or the like is formed on the uppermost layer wiring.
Other wiring The insulating film on the first layer wiring and the second layer wiring is HDP-
It may be a CVD silicon oxide film.

In particular, when the necessity of flattening by the CMP method is small, such as when the wiring interval is large, the interlayer insulating film is formed of an HDP-CVD silicon oxide film or the like, so that a steep step or a corner portion is formed. Occurrence can be avoided. In addition to the power supply wiring, when the resistance is reduced to ensure high-speed operation, the thickness of the wiring layer becomes large. Therefore, the effect of forming the insulating film by the HDP-CVD silicon oxide film or the like is obtained. Is big.

It is possible to flatten the insulating film on the uppermost wiring by using the CMP method. However, when the thickness of the wiring layer is large, the amount of deposition of the insulating film is large, so the polishing amount is small. It becomes difficult to control polishing.

The semiconductor elements constituting the integrated circuit are as follows:
For example, not only the above-mentioned MISFET but also a bipolar transistor or a combination of a MISFET and a bipolar transistor may be used, and further, a combination of these active elements and passive elements such as capacitors and resistors may be used. In addition to the above-described Al wiring, the wiring may be W (tungsten) or the like. Further, the wiring is not limited to three layers, and may be four or more layers.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

[0053]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a second insulating film is formed on a wiring layer by high-density P-CVD.
Since the second insulating film having a tapered shape is formed on the end of the wiring layer by depositing by the method, the stress applied to the insulating film can be reduced, and the occurrence of cracks generated in the insulating film can be reduced. be able to. In addition, LSI
Reliability can be improved.

Further, the insulating film on the uppermost wiring is formed of a high density P
-Deposition by the CVD method, forming an insulating film having a tapered shape on the end of the wiring layer, alleviates these stresses even if stress is applied to the insulating film by the subsequent formation of the base electrode and the formation of the bump electrode And the occurrence of cracks in the insulating film can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

3A is a partially enlarged view of the vicinity of the uppermost layer wiring in FIG. 1, and FIG. 3B is a diagram for explaining an effect of the present invention.

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 P-type well 4 N-type well 7 Silicon oxide film 8 Gate oxide film 9 Gate electrode 9a Polycrystalline silicon film 9c W film 10 Silicon nitride film 11 n ^- type semiconductor region 12 p ^- type semiconductor region Reference Signs List 13 sidewall spacer 14 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 16 interlayer insulating film 17 contact hole 18 plug 20 first layer wiring 21 interlayer insulating film 22 contact hole 23 plug 24 second layer wiring 25 interlayer insulating film 27 plug Reference Signs List 28 third layer wiring 29 silicon nitride film or silicon oxide film 30 HDP-CVD silicon oxide film 31 TEOS film or silicon nitride film 40 base electrode 41 bump electrode 51 package substrate 52 pad electrode 53 underfill resin A portion B corner portion Qnn Channel type MISF T Qp p-channel type MISFET S step

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI theme coat ゛ (Reference) H01L 21/318 H01L 21/90 M (72) Inventor Kazunori Omori 6-16 Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi Device Development Center Co., Ltd. (reference) AA10 AA20 AB31 AB32 AB33 AC09 AE15 AE17 AE21 AE23 5F058 BA20 BC02 BC08 BD01 BD04 BD10 BF04 BF08 BF09 BF25 BF29 BJ02

Claims (5)

[Claims] (A) forming an element on a main surface of a semiconductor substrate; (b) forming a first insulating film on the element; and (c) forming a first insulating film on the first insulating film. Forming a wiring layer by forming a conductive film on the wiring layer and patterning it into a desired shape; and (d) forming a second insulating film on the wiring layer by high-density plasma C.
Forming a second insulating film having a tapered shape on the end of the wiring layer by depositing by a VD method. A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming an element on a main surface of a semiconductor substrate; (b) forming a first insulating film on the element; and (c) forming an element on the first insulating film. Forming a conductive film on the wiring layer and patterning it into a desired shape to form a wiring layer; (d) forming a second insulating film on the wiring layer by a CVD method; Forming a third insulating film having a tapered shape on the end of the wiring layer by depositing a third insulating film on the second insulating film by a high-density plasma CVD method. A method for manufacturing a semiconductor integrated circuit device. 3. A step of forming an element on a main surface of a semiconductor substrate; a step of forming a first insulating film on the element; and a step of forming a first insulating film on the element. Forming a low-resistance wiring by forming a conductive film on the low-resistance wiring by patterning into a desired shape; (d) forming a second insulating film on the low-resistance wiring by a CVD method; Forming a third insulating film having a tapered shape on the end of the wiring layer by depositing a third insulating film on the second insulating film by a high-density plasma CVD method. A method for manufacturing a semiconductor integrated circuit device. 4. A step of forming an element on a main surface of a semiconductor substrate; a step of forming a plurality of wiring layers electrically connected to the element; and a step of forming a plurality of wirings electrically connected to the element. Forming a first insulating film on the uppermost wiring of the wirings by a CVD method; and (d) depositing an insulating film on the first insulating film by a high-density plasma CVD method. Forming a second insulating film having a tapered shape on an end of the wiring layer. A method for manufacturing a semiconductor integrated circuit device, comprising: 5. A step of forming an element on a main surface of a semiconductor substrate; a step of forming a plurality of wiring layers electrically connected to the element; and a step of forming a plurality of wirings electrically connected to the element. Forming a first insulating film on the uppermost wiring of the wirings by a CVD method; and (d) depositing an insulating film on the first insulating film by a high-density plasma CVD method. Forming a second insulating film having a tapered shape on the end of the wiring layer; and (e) exposing the surface of the uppermost wiring by etching the first and second insulating films. (F) forming a base electrode on the exposed portion of the uppermost layer wiring; and (g) forming a bump electrode on the base electrode on the exposed portion of the uppermost layer wiring. Of manufacturing a semiconductor integrated circuit device.