TWI559414B - Through substrate via process - Google Patents

Description

Substrate perforation process

This invention relates to a semiconductor process and, more particularly, to a through substrate via (TSV) process.

As semiconductor technology continues to advance, in order to increase the degree of integration of semiconductor components and to meet the demand for high component performance, development has been progress toward wafer stack structures. Substrate perforation is a commonly used technique for fabricating wafer stack structures in the prior art by first forming a high aspect ratio hole in the substrate of the wafer and filling the opening with a conductor material. Then, a chemical mechanical polishing process is performed to remove the conductor material outside the opening. Next, a portion of the back side of the substrate is removed to thin the thickness of the substrate and expose the conductor material in the opening. Thereafter, the plurality of wafers are bonded together in a stacked manner, and the wafers are electrically connected by the conductor material in the openings.

In general, the substrate perforation process can be mainly divided into four types, however, each type of substrate perforation process has its own disadvantages.

The first type of substrate via process is performed prior to fabrication of a semiconductor component such as a metal oxide semiconductor (MOS) transistor. When the conductor material filled in the opening is made of metal, it tends to cause contamination on the wafer and affects the subsequent process, and the metal filled in the opening cannot withstand the high temperature when the semiconductor element is subsequently formed. (for example, the high temperature of the thermal oxidation process performed when the gate dielectric layer is formed, and the high temperature during the source/drain region activation process) temperature). In addition, if polycrystalline germanium is filled into the opening in order to avoid the above-mentioned contamination problem, the resistance of the polycrystalline germanium is too high, which affects the performance of the device.

The second type of substrate via process is performed after the fabrication of semiconductor components (such as MOS transistors) and after the post-process (such as interconnect process). However, when the conductor material is filled into the opening, the degree of difficulty in the CMP process is often increased due to the formation of the semiconductor component on the substrate.

The third type of substrate perforation process is performed after the post-stage process and prior to wafer bonding. However, in order to have sufficient areas for the substrate via process after the interconnect process, it is often necessary to increase the area of the wafer. In addition, in order to preserve the area where the substrate perforation process is performed, the complexity of the interconnect process is often also increased.

The fourth type of substrate via process is performed after wafer bonding. However, the adhesive material used to bond the wafer often cannot withstand the high temperature in the substrate perforation process and is damaged, thereby causing the problem that the wafer cannot be joined.

In view of the above, an object of the present invention is to provide a substrate perforation process which can prevent the conductor material in the opening from being damaged in a high temperature environment without causing contamination on the substrate.

The present invention provides a substrate perforation process that first provides a substrate having opposing first and second sides. Then, a plurality of openings are formed in the substrate on the first side. Thereafter, a first dielectric layer is formed on the sidewalls and the bottom of the opening. Next, a second dielectric layer is formed in the opening. The material of the second dielectric layer is different from the material of the first dielectric layer. Then, a semiconductor element and an interconnect are formed on the substrate on the first side. Then, at least part of the substrate on the second side is removed, A second dielectric layer in the opening is exposed. Subsequently, the second dielectric layer is removed. Thereafter, a conductor layer is formed in the opening.

According to the substrate perforation process of the embodiment of the invention, the material of the first dielectric layer is, for example, tantalum oxide or tantalum nitride.

According to the substrate perforation process of the embodiment of the invention, the material of the second dielectric layer is, for example, tantalum oxide or tantalum nitride.

According to the substrate perforation process of the embodiment of the invention, the method for forming the first dielectric layer is, for example, a chemical vapor deposition method.

According to the substrate perforation process of the embodiment of the invention, the material of the conductor layer is, for example, copper.

In the substrate perforation process according to the embodiment of the invention, the method for removing a portion of the substrate on the second side is, for example, a chemical mechanical polishing method.

In the substrate perforation process according to the embodiment of the invention, the method for removing the second dielectric layer is, for example, a wet etching method.

According to the substrate perforation process of the embodiment of the invention, the method for forming the second dielectric layer is, for example, a chemical vapor deposition method.

In the substrate perforation process according to the embodiment of the invention, the conductor layer is formed by, for example, forming a layer of a conductor material on the substrate on the second side and filling the opening. Then, the layer of conductive material outside the opening is removed.

According to the substrate perforation process of the embodiment of the invention, the semiconductor component is, for example, a metal oxide semiconductor transistor.

According to the substrate perforation process of the embodiment of the invention, the material of the substrate is, for example, germanium.

After forming the opening, the present invention fills the opening with a dielectric layer instead of the conductor layer, and then performs a semiconductor process on the substrate, and then opens the hole. The dielectric layer is removed and filled into the conductor layer, thereby avoiding the problem of contamination on the substrate and preventing the conductor layer from being damaged by the high temperature in the semiconductor process.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A-1D are schematic cross-sectional views showing a process of a substrate perforation process according to an embodiment of the invention. Referring first to Figure 1A, a substrate 100 is provided. The substrate 100 is, for example, a crucible substrate. The substrate 100 has opposing first side 102 and second side 104. An opening 106 is then formed in the substrate 100 of the first side 102. The method of forming the opening 106 is, for example, sequentially performing a lithography process and an etching process. Next, a dielectric layer 108 is formed on the substrate 100. The material of the dielectric layer 108 is, for example, tantalum oxide or tantalum nitride, and the formation method thereof is, for example, conformally formed on the substrate 100 by chemical vapor deposition. Then, a dielectric layer 110 is formed on the substrate 100 and fills the opening 106. The material of the dielectric layer 110 is, for example, hafnium oxide or tantalum nitride, and the formation method thereof is, for example, a chemical vapor deposition method. In particular, the material of the dielectric layer 108 must be different from the material of the dielectric layer 110 so that the dielectric layer 108 is retained by different etching characteristics of the different materials when the dielectric layer 110 is subsequently removed. That is, when the material of the dielectric layer 108 is yttrium oxide, the material of the dielectric layer 110 is tantalum nitride. On the contrary, when the material of the dielectric layer 108 is tantalum nitride, the material of the dielectric layer 110 is yttrium oxide. Next, the dielectric layer 108 and the dielectric layer 110 outside the opening 106 are removed, while the dielectric layer 108 on the sidewalls and bottom of the opening 108 and the dielectric layer 110 in the opening 106 are retained. The dielectric layer 108 on the sidewalls and the bottom of the opening 106 can be used as a barrier layer or an insulating layer, so that the conductor layer formed in the opening 106 is not electrically connected to the substrate 100.

Then, referring to FIG. 1B, a well-known semiconductor process is performed on the substrate 100 of the first side 102. For example, the semiconductor device 112, the dielectric layer 120, the interconnect, the pad 123, and the protective layer 125 are formed on the substrate 100 of the first side 102. The semiconductor element 112 is, for example, a metal oxide semiconductor transistor. In detail, the semiconductor device 112 includes a gate dielectric layer 114 and a gate 116 sequentially formed on the substrate 100, and a source/drain region 118 including the substrate 100 on both sides of the gate 116. The interconnect includes wires 124 and plugs 126 that are respectively located in different layers. The materials and formation methods of the semiconductor device 112, the dielectric layer 120 interconnect, the pad 123, and the protective layer 125 are well known to those of ordinary skill in the art and will not be described herein. Specifically, the substrate through holes are electrically connected to the semiconductor device 112 through any one of the interconnect wires 124. Preferably, the uppermost wire 124 of the interconnect is connected first, and then electrically connected to the semiconductor device 112. The pad 123 can be electrically connected to the outside of the wafer in a conventional manner.

In particular, since only the dielectric layers 108, 110 are formed in the openings 106 without the conductor material, contaminants that affect subsequent processes are not generated on the substrate 100.

Next, referring to FIG. 1C, a portion of the substrate 100 of the second side 104 is removed to expose the dielectric layer 110 in the opening 106. A method of removing a portion of the substrate 100 of the second side 104 is, for example, a chemical mechanical polishing method. In the present embodiment, a portion of the substrate 100 and the dielectric layer 108 are removed by chemical mechanical polishing until the dielectric layer 110 is exposed. In another embodiment, chemistry can be utilized The mechanical polishing method removes a portion of the substrate 100 from the dielectric layers 108, 110 until the thickness of the substrate 100 reaches a predetermined thickness. Subsequently, the dielectric layer 110 is removed. The method of removing the dielectric layer 110 is, for example, a wet etching method. Since the dielectric layer 108 is different from the material of the dielectric layer 110, the dielectric layer 108 can be left in the process of removing the dielectric layer 110 by adjusting the etching rate of the dielectric layer 108 and the dielectric layer 110. On the side wall of the hole 106.

Thereafter, referring to FIG. 1D, a conductor layer 128 is formed in the opening 106. The material of the conductor layer 128 is, for example, copper. The conductor layer 128 is formed by, for example, forming a layer of conductive material on the substrate 100 of the second side 104 and filling the opening 106. Then, the method of removing the layer of the conductor material outside the opening 106 to remove the layer of the conductor material other than the opening 106 is, for example, a chemical mechanical polishing method. Since the semiconductor element 112 is formed on the substrate 100 when the conductor layer 128 is formed in the opening 106, the conductor layer 128 is not damaged by the high temperature when the semiconductor element 112 is formed.

After performing the above-described substrate perforation process, a plurality of wafers may be bonded in a stacked manner using an adhesive material. Since the substrate perforation process has been completed before the wafer is bonded by the adhesive material, it is possible to avoid the problem that the adhesive material is not affected by the high temperature and the wafer cannot be bonded.

In summary, the present invention fills the opening with a dielectric layer instead of the conductor layer after forming the opening, and then performs a semiconductor process on the substrate, thereby avoiding the problem of contamination on the substrate.

In addition, the present invention removes the dielectric layer in the opening and fills the conductor layer after performing the semiconductor process, thereby preventing the conductor layer from being damaged by high temperature.

In addition, the present invention performs wafer bonding after completing the substrate perforation process. Therefore, it is possible to avoid the problem that the adhesive material is not affected by the high temperature and the wafer cannot be joined.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Base

102‧‧‧ first side

104‧‧‧ second side

106‧‧‧Opening

108, 110, 120‧‧‧ dielectric layer

112‧‧‧Semiconductor components

114‧‧‧gate dielectric layer

116‧‧‧ gate

118‧‧‧Source/Bungee Area

123‧‧‧ solder pads

124‧‧‧Wire

125‧‧‧Protective layer

126‧‧‧ plug

128‧‧‧ conductor layer

1A-1D are schematic cross-sectional views showing a process of a substrate perforation process according to an embodiment of the invention.

100‧‧‧Base

102‧‧‧ first side

104‧‧‧ second side

106‧‧‧Opening

108, 110‧‧‧ dielectric layer

Claims (11)

A substrate perforating process includes: providing a substrate having an opposite first side and a second side; forming a plurality of openings in the substrate on the first side; sidewalls and bottoms of the openings Forming a first dielectric layer; forming a second dielectric layer in the openings, wherein the second dielectric layer fills the openings, and the material of the second dielectric layer is the first The dielectric layer is different in material; a semiconductor element and an interconnect are formed on the substrate on the first side; and at least a portion of the substrate on the second side is removed to expose the second of the openings a dielectric layer; removing the second dielectric layer; and forming a conductor layer in the openings. The substrate perforation process of claim 1, wherein the material of the first dielectric layer comprises hafnium oxide or tantalum nitride. The substrate perforation process of claim 1, wherein the material of the second dielectric layer comprises hafnium oxide or tantalum nitride. The substrate perforation process of claim 1, wherein the method of forming the first dielectric layer comprises chemical vapor deposition. The substrate perforating process of claim 1, wherein the material of the conductor layer comprises copper. The substrate perforation process as described in claim 1 of the patent application, wherein A method of removing a portion of the substrate on the second side includes a chemical mechanical polishing process. The substrate perforation process of claim 1, wherein the method of removing the second dielectric layer comprises a wet etching process. The substrate perforation process of claim 1, wherein the method of forming the second dielectric layer comprises chemical vapor deposition. The substrate perforation process of claim 1, wherein the forming of the conductor layer comprises: forming a layer of conductive material on the substrate on the second side, filling the openings; and removing the The layer of conductor material outside the openings. The substrate perforation process of claim 1, wherein the semiconductor component comprises a metal oxide semiconductor transistor. The substrate perforating process of claim 1, wherein the material of the substrate comprises ruthenium.