JP2002299366A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce generation of breakdowns and disconnections by reducing stress applied to a solder bump of a mounted semiconductor chip. SOLUTION: A photosensitive polyimide film 25a of a film thickness of 20 μm or large is formed on a rearrangement wiring 22 in the upper part of a semiconductor substrate 1. A solder bump 28a is formed filled inside an opening part C5, which is formed in the photosensitive polyimide film 25a and reaches a surface of the rearrangement wiring 22, to project on the opening part C5. As a result, the distance between the semiconductor substrate 1 (semiconductor chip C) and a mounting substrate 30, whereon the semiconductor substrate 1 is subjected to facedown mounting, can be ensured to be large and stress applied to the solder bump 28a, which joins the semiconductor substrate 1 and the mounting substrate 30, can be relaxed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a technology effective when applied to flip chip mounting.

[0002]

2. Description of the Related Art Flip-chip mounting is a method in which a bump electrode called a bump is formed on an electrode on the surface of a semiconductor chip, the chip is turned upside down, and the wiring and the bump on a wiring board are aligned and face-down bonding is performed. This is an implementation method to connect with. According to this mounting method, package miniaturization (so-called chip size package (CSP)),
There is an advantage that the mounting density can be increased.

However, depending on the material of the wiring board, the difference in the coefficient of thermal expansion between the wiring board and the semiconductor chip (eg, a silicon substrate) increases, and the stress applied to the semiconductor chip increases.

Japanese Patent Application Laid-Open No. Sho 62-117346 describes a technique for securing the height of a flip chip joint and securing the joint life by forming solder bumps using metals or alloys having different melting points. Have been.

Also, electronic materials, September 1999, p22
26 to 26 describe a CSP technique in which a copper post is formed on the rewiring (Al), a barrier plating is formed on the post, and a solder ball is formed on the post after resin sealing.

[0006]

SUMMARY OF THE INVENTION The present inventors are studying the relaxation of stress due to the difference in the coefficient of thermal expansion between the aforementioned wiring board and the semiconductor chip (for example, a silicon substrate). For example, when a resin-based material is used for the wiring board, the stress occurs because the thermal expansion coefficient is about five times larger than that of a semiconductor chip (for example, a silicon substrate). In particular, during an acceleration test (temperature cycle test) under high and low temperatures, stress is likely to cause breakage of the joint between the chip and the wiring board and breakage of the wiring formed inside or on the surface thereof. If a material having high rigidity, such as copper, is used for the joint, the joint is easily broken.

On the other hand, when a wiring board made of a ceramic material is used, the difference in the coefficient of thermal expansion between the wiring board and the silicon substrate is reduced, and the stress can be reduced. However, since the ceramic material is expensive, the package cost is reduced. Cannot be reduced.

An object of the present invention is to provide a technique for reducing a stress applied to a mounted semiconductor chip.

Another object of the present invention is to reduce the occurrence of breakage and disconnection due to a temperature cycle.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The semiconductor device of the present invention is an organic insulating film formed on the rearranged wiring, and has a thickness of 20 μm.
m or more of an organic insulating film, an opening formed in the organic insulating film, an opening reaching the surface of the relocation wiring, a solder bump filled in the opening, and protruding above the opening. And

(2) The method of manufacturing a semiconductor device according to the present invention
Forming an organic insulating film having a thickness of 20 μm or more on the relocation wiring, forming an opening on the relocation wiring by selectively removing the organic insulating film; Forming a solder on the organic insulating film including the inside and performing a heat treatment to form a solder bump filled in the opening and protruding above the opening.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

1 to 10 are main-portion cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG.
By the ET forming process, the n-channel type MISFET Q
An n and p channel type MISFET Qp is formed.

A typical MISFET forming process includes, for example, the following.

First, an element isolation 2 is formed on a semiconductor substrate 1 made of p-type single crystal silicon. In order to form the element isolation 2, an element isolation groove is formed by etching the semiconductor substrate 1, and CVD (Ch) is formed on the substrate 1 including the inside of the groove.
After the silicon oxide film 7 is deposited by an em- ical vapor deposition (chemical vapor deposition) method, chemical mechanical polishing (CMP) is performed.
The silicon oxide film 7 above the groove is polished by a cal polishing method.

Next, a p-type impurity and an n-type impurity are ion-implanted into the substrate 1 and the impurities are diffused by heat treatment to form a p-type well 3 and an n-type well 4, and then the p-type well is formed by thermal oxidation. A gate oxide film is formed on each surface of the 3 and n-type wells 4.

Next, a low-resistance phosphorus-doped polycrystalline silicon film is deposited on the gate oxide film by a CVD method, and then a thin WN film (not shown) and a W film are formed thereon by a sputtering method. Then, a silicon nitride film 10 is further deposited thereon by a CVD method.

Next, the silicon nitride film 10 is dry-etched to leave the silicon nitride film 10 in a region where a gate electrode is to be formed. Using the silicon nitride film 10 as a mask, a W film, a WN film (not shown) and By dry-etching the polycrystalline silicon film, a gate electrode 9 composed of a polycrystalline silicon film, a WN film (not shown) and a W film is formed.

Next, the p-type wells 3 on both sides of the gate electrode 9 are formed.
An n ⁻ -type semiconductor region 11 is formed by ion-implanting an n-type impurity into the n-type well, and a p ⁻ -type semiconductor region 12 is formed by ion-implanting a p-type impurity into the n-type well 4.
To form

Next, after depositing a silicon nitride film on the substrate 1 by the CVD method, anisotropic etching is performed to form a sidewall spacer on the side wall of the gate electrode 9.

Next, p by n ⁺ -type semiconductor regions 14 (source and drain) by ion implantation of n-type impurity into the p-type well 3 is formed, and ion implantation of p-type impurity into the n-type well 4 ⁺ Type semiconductor region 15
(Source, drain) are formed.

Up to this point, LDD (Lightly Doped
N-channel type MISFET Qn and p-channel type MISFET Qp
Is formed.

Thereafter, an interlayer insulating film such as a silicon oxide film and a conductive film such as an aluminum film are alternately deposited on the MISFETs Qn and Qp to form a plurality of wirings.

For example, after depositing a silicon oxide film on the MISFETs Qn and Qp by the CVD method, the silicon oxide film is polished by the CMP method and the surface thereof is flattened to form the interlayer insulating film TH1.

Next, a photoresist film is formed on the interlayer insulating film TH1 (not shown), and the interlayer insulating film TH1 is etched using the photoresist film as a mask, thereby forming an n ⁺ type semiconductor on the main surface of the semiconductor substrate 1. A contact hole C1 is formed on the region 14 and the p ⁺ type semiconductor region 15.

Next, a tungsten film is deposited on the interlayer insulating film TH1 including the inside of the contact hole C1 by the CVD method, and the tungsten film is polished by the CMP method until the interlayer insulating film TH1 is exposed. To form a plug P1. Next, a titanium nitride film (not shown), an aluminum film, and a titanium nitride film (not shown) are sequentially deposited on the interlayer insulating film TH1 and the plug P1 by a sputtering method, and are patterned into a desired shape to form a first film. The layer wiring M1 is formed.

Thereafter, by repeatedly forming the interlayer insulating films (TH2, TH3), plugs (P2, P3) and wirings (M2, M3), a multilayer wiring structure is formed. FIG.
Shows the case of three-layer wiring (M1 to M3).

Next, a silicon nitride film 20 is formed on the uppermost layer wiring (third layer wiring M3 in FIG. 1) by the CVD method. Thereafter, a rearrangement wiring electrically connected to the uppermost wiring is formed, and a solder bump is formed thereon. Then, the wiring on the mounting board and the solder bump are aligned and connected by face-down bonding. The solder bump forming step and the face-down bonding step will be described with reference to FIGS. 2 to 7
FIG. 9 is a partially enlarged view of a pad portion of the uppermost layer wiring (M3).

As shown in FIG. 2, a contact hole 21 is formed by selectively removing the silicon nitride film 20 on the uppermost layer wiring (third layer wiring M3 in FIG. 1).
The size of the contact hole 21 is about 30 nm, and the bottom of the contact hole 21 has the surface of the uppermost layer wiring (pad portion P).
Is exposed.

Next, including the inside of the contact hole 21,
On the silicon nitride film 20, a relocation wiring 22 made of, for example, a Cu (copper) film is formed. This Cu film can be formed by a sputtering method or an electrolytic plating method.
After the u film is deposited on the silicon nitride film 20 including the inside of the contact hole 21, the relocation wiring 22 is formed by patterning. This relocation wiring 22
Plays a role of connecting a plurality of pad portions P, each of which is densely formed, to a plurality of solder bumps 28a, each of which is spaced apart to some extent (FIG. 8).
reference).

Next, a 20 μm-thick photosensitive polyimide film 25 a is formed on the redistribution wiring 22 and the silicon nitride film 20.
To form In order to form the photosensitive polyimide film 25a, first, as shown in FIG. 3, the photosensitive polyimide resin 25 is spin-coated on the semiconductor substrate 1.

Next, as shown in FIG. 4, the photosensitive polyimide resin 25 is subjected to a heat treatment to evaporate the solvent in the resin, and then exposed and developed to form contact holes ( An opening C5 is formed. At the bottom of the contact hole C5, a part (polyimide opening 26) of the surface of the relocation wiring 22 is exposed. Thereafter, heat treatment is performed to cure the photosensitive polyimide film 25a. Thus, if a photosensitive film is used, patterning can be performed without using a resist film.

Here, in order to make the photosensitive polyimide film 25a thick, there are a method of using a high-viscosity one, a method of coating a plurality of times, and the like. For example, a film having a thickness of 40 μm can be formed by forming a 20 μm photosensitive polyimide layer twice. The photosensitive polyimide film 25a plays a role as a protective film for the redistribution wiring 22.

Next, as shown in FIG. 5, Au (gold) is deposited on the polyimide opening 26 by electroless plating to form a base metal layer 27. This base metal layer 27
Is formed to improve solder wetting (adhesion of a solder paste described later).

Next, as shown in FIG.
7 and on the photosensitive polyimide film 25a in the vicinity thereof,
A solder paste 28 made of an alloy of Sn (tin) and Pb (lead) is formed by screen printing. At this time, the solder paste 28 is printed in an amount (thickness) sufficient for the solder to fill the contact hole C5 and protrude from the surface of the photosensitive polyimide film 25a by a heat treatment described later.

Next, as shown in FIG. 7, heat treatment is performed to form solder bumps 28a. By this heat treatment, the solder is melted and rounded, and the upper portion of the solder bump 28a becomes spherical as shown in FIG.

The above steps are performed in a wafer state. That is, as shown in FIG. 8A, there is a chip area CA partitioned into a rectangular shape on the wafer W.
Are densely formed in the center of the chip area CA. As shown in FIG. 8B, the rearrangement wiring 22 is drawn out from the pad portion P on the uppermost wiring, and further, a solder bump 28a is formed on an upper portion thereof (above the polyimide opening portion 26). It is formed (FIG. 8C). Thus, the pad portion P is connected to the solder bump 2 by the rearrangement wiring 22.
By drawing out to 8a, a large formation region of the solder bumps 28a and the space between the solder bumps can be secured, and short-circuit can be prevented.

Thereafter, by dicing the wafer W shown in FIG. 8C, a plurality of chips C can be obtained by cutting each chip area CA.

Next, the chip C is mounted on the mounting substrate 30. The mounting process will be described below. As shown in FIGS. 9 and 10, the surface on which the solder bump 28a of the chip C (semiconductor substrate 1) is formed is set to the lower side,
Face-down bonding is performed on the mounting substrate 30. The wiring 31 is formed on the mounting board 30 in advance, and the wiring 31 is aligned so that a part of the wiring 31 is in contact with the solder bump 28a. Next, the solder bump 28
The chip C and the mounting substrate 30 are bonded by heating and reflowing a. The wiring 31 is made of, for example, Cu
A wiring can be formed, and a solder resist 32 is formed around the wiring 31. FIG.
5 is an overall view after mounting the chip C on the mounting board 30. FIG.

As described above, according to the present embodiment, 20
A photosensitive polyimide film 25a having a thickness of .mu.m was formed, and solder bumps 28a were formed in and on contact holes C5 formed in this film.
(Relocation wiring 22 on the upper part of the semiconductor substrate 1) and the mounting substrate 30
(Joining height) can be increased. Since the distortion due to the difference between the thermal expansion coefficient of the chip C (semiconductor substrate 1) and the mounting substrate 30 is inversely proportional to the bonding height,
By ensuring a large joining height, the stress applied to the chip C can be reduced.

For example, if the photosensitive polyimide resin film is 5 μm
When the solder bumps 28a are formed in the same manner as in the present embodiment, even if the height of the solder bumps 28a is set to 150 μm, the solder bumps 28a are crushed during the subsequent bonding to the mounting board. , Joint height is 90
It becomes about μm. On the other hand, when the photosensitive polyimide resin is thickened as in the present embodiment, the bonding height can be increased by the thickness of the photosensitive polyimide resin. For example, if the thickness of the photosensitive polyimide resin film is 20
If it is set to μm, the junction height will be about 110 μm (1.2 times that of 90 μm). If the thickness of the photosensitive polyimide resin film is 40 μm, the bonding height is about 130 μm.
m (1.4 times that of 90 μm).

As a result, for example, the destruction of the solder bump joint between the chip C and the mounting board 30 by the accelerated test (temperature cycle) at a high temperature, and the disconnection of the wiring formed inside or on the surface thereof are prevented. can do.

Even when an inexpensive resin substrate is used, a high-performance semiconductor device can be provided, and the package cost can be reduced.

In the present embodiment, Sn
Solder paste 28 consisting of an alloy of (tin) and Pb (lead)
Was formed by screen printing and heat treatment was performed to form the solder bumps 28a. However, as shown in FIG. 11, the solder balls 22a were formed on the contact holes C5.
8 and heat-treat the solder balls 2
28, solder is filled into the contact holes C5, and the solder bumps 228 protruding therefrom are melted.
a may be formed (FIG. 12). Note that the solder mentioned here includes Pb (lead) -free solder.

Through the above steps, a polyimide film 25a having a thickness of 20 μm or more formed on the relocation wiring 22, a contact hole C5 formed in the polyimide film 25a, and a filling in the contact hole C5, Further, a semiconductor device is formed in which the semiconductor substrate 1 (chip C) having the solder bumps 28a protruding from the upper surface thereof is face-down bonded to the mounting substrate 30.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the first and second embodiments,
Although the MISFETs Qn and Qp are formed as semiconductor elements, the present invention is not limited to these MISFETs, and other semiconductor elements such as bipolar transistors may be formed.

In the present embodiment, the present invention is applied between the semiconductor chip C and the mounting substrate 30. For example, in a multi-chip module using a multilayer mounting substrate, the present invention is applied between the mounting substrates. For example, the present invention can be widely applied to products for connecting between substrates using solder bumps.

In particular, even when the mounting substrates are heavy and the bonding between the mounting substrates is likely to be distorted, the distance between the mounting substrates can be secured by applying the present invention.

[0053]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

A polyimide film having a thickness of 20 μm or more is formed on the relocation wiring on the semiconductor substrate, and an opening formed in the polyimide film and reaching the surface of the relocation wiring. And the solder bumps are formed so as to protrude above the openings, so that a large distance can be secured between the semiconductor substrate and the mounting substrate on which the semiconductor substrate is mounted. As a result, stress applied to the semiconductor substrate and the mounting substrate can be reduced. Further, occurrence of destruction or disconnection due to a temperature cycle can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a plan view of a main part of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a cross-sectional view of a main part of a substrate, illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation 3 p-type well 4 n-type well 7 silicon oxide film 9 gate electrode 10 silicon nitride film 11 n ^- type semiconductor region 12 p ^- type semiconductor region 14 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 20 Silicon nitride film 21 Contact hole 22 Relocation wiring 25 Photosensitive polyimide resin 25a Photosensitive polyimide film 26 Polyimide opening 27 Base metal layer 28 Solder paste 28a Solder bump 30 Mounting board 31 Wiring 32 Solder resist 228 Solder ball 228a Solder bump C Semiconductor Chip C1 to C4 Contact hole C5 Contact hole (opening) CA Chip area M1 to M3 Wiring P Pad section P1 to P3 Plug Qn N-channel MISFET Qp P-channel MISFET TH1 to TH3 Interlayer insulation W wafer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Osamu Ito 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5F044 QQ02 QQ04 QQ05

Claims (3)

[Claims] (A) a relocation wiring electrically connected to an uppermost layer wiring formed on an upper portion of a semiconductor substrate; and (b) an organic insulating film formed on the relocation wiring. An organic insulating film having a thickness of 20 μm or more; and (c) an opening formed in the organic insulating film,
An opening reaching the surface of the relocation wiring; (d) a solder bump filled in the opening and protruding above the opening; (e) a wiring contacting the solder bump; and (f) the wiring A semiconductor device, comprising: a mounting substrate on which is formed. 2. The semiconductor device according to claim 1, wherein said opening has a diameter of 50 to 200 μm. 3. A process of forming a relocation wiring on an uppermost wiring formed on an upper part of a semiconductor substrate; and (b) an organic insulating film having a thickness of 20 μm or more on the relocation wiring. (C) forming an opening on the relocation wiring by selectively removing the organic insulating film; and (d) soldering on the organic insulating film including inside the opening. Forming a solder bump filled in the opening and protruding above the opening by performing a heat treatment; and (e) wiring of the mounting board on which the wiring is formed is in contact with the solder bump. A method of manufacturing a semiconductor device, comprising the steps of: