JPH03174764A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent ions from charging up an island semiconductor layer by partially removing gate insulating film only from an Nch transistor in a CMOS semiconductor device comprising thin film transistors fabricated on an insulating substrate. CONSTITUTION:An insulating substrate 1 having thoroughly polished surface is cleaned and a semiconductor material layer 2 is formed. The semiconductor layer 2 is then isolated into islands through photolithography etching and an insulating film 3 is formed thereon. A layer 4 is formed thereon and patterning is carried out thus obtaining a gate electrode 4. Gate insulating film on an Nch transistor is then removed through etching, a semiconductor layer for providing a source and a drain is exposed, and an a-SiOxPy layer is formed and subjected to thermal diffusion processing for lowering the resistance and subsequently removed. Boron ions are then implanted with resist being left at the Nch transistor part through photolithography. By such method, breakdown of insulating film due to charge-up can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device having a thin film transistor on an SUa substrate and a method for manufacturing the same.

[Prior art]

The source/drain regions of a normal MOS type TPT require high concentration impurity doping in order to lower the resistance.

This high concentration impurity doping is performed by a diffusion method or an ion implantation method. The degree of this reduction in resistance varies depending on the purpose of the semiconductor device, but generally when using An or an Af1 alloy containing S3 and Cυ as a wiring electrode material, the impurity concentration needs to be 1X10''/a+Y or more.

Furthermore, when forming an ohmic contact with an n-type semiconductor layer, LX], 0''/a+? is required.

Normally, when forming the source/drain by ion implantation, an ion implantation amount of IXl015/c+7 or more is required. However, in this case, TPT is unique in that an island-shaped semiconductor layer is formed on an insulating substrate, so ions charge up on the island-shaped semiconductor layer during ion implantation, and the charge is transferred to a part of the implantation equipment. A problem arises in that this semiconductor layer is destroyed during discharge.

This destruction of the semiconductor layer occurs more frequently as the implantation amount increases, but it rarely occurs if I x 1015/d or less.

However, for the ohmic contact with the n-type semiconductor layer mentioned above, I
Ion implantation of the order of X 1020/a& is required, and 1X10"5/ci is insufficient, so countermeasures are being sought.

〔the purpose〕

The purpose of the present invention is to reduce the surface impurity concentration of the n-type semiconductor layer by lX
10''/-, 4- is to prevent ions from charging up on the island-shaped semiconductor layer.

[structure]

One of the present inventions relates to a C-MO5 semiconductor device comprising a thin film transistor fabricated on an insulating substrate, in which only the Nch transistor has a shape in which a portion of the gate insulating film is removed.

Another aspect of the present invention is to form a semiconductor layer in an island shape on an insulating substrate, then form an insulating film on the surface of the semiconductor layer, and then
When forming the transistor section and the Nch transistor section, the source/drain regions of the Pch transistor section are formed by ion implantation, and the source/drain regions of the Nch transistor section are formed after removing at least part of the gate insulating film in that area. 1. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by a thermal diffusion method.

A first aspect of the present invention will be explained according to FIG.

(1) After thoroughly cleaning an insulating substrate (eg, glass, ceramics) 1 whose surface has been sufficiently polished, a semiconductor material layer (amorphous-8i, polycrystalline Si, or compound semiconductor) 2 is formed. In this example, polycrystalline Si is
500A or more, preferably 1000A by low pressure CVD method
Deposit people. This semiconductor layer 2 is separated and formed into island shapes by photolithography and etching [Fig.
)reference〕.

(2) Next, an insulating film 3 is formed on the surface of the semiconductor layer 2 [see FIG. 1(b)].

The M edge film 3 may be made of 5in2, Si3N4 by CVD method, but since it will be a gate insulation II# film, M of polycrystalline Si may be used.
It is desirable to form 2 by dry thermal oxidation (iooo° C.) to a thickness of 500 Å or more, preferably 800 Å, to obtain a high quality insulating film. Next, a layer 4 (metal silicide, high melting point metal, polycrystalline silicon, etc., in this embodiment, polycrystalline silicon) 3000A which will become a gate electrode is formed.

(3) Perform desired patterning by photolithography and etching to obtain the gate electrode 4 [see FIG. 1(c)].

(4) Next, the gate insulating film on the Nch transistor is removed by etching to expose the semiconductor layer that will become the source/drain [Fig. 1(d)], and then the a-5iO
xPy calendar is formed [Fig. 1(e)]. Then, the resistance is lowered by thermal diffusion treatment (900°C, 30 minutes) in the drive process (for example, if the n-type impurity is phosphorus, 9
The surface impurity concentration of P can be reduced to 5×1020/a3 at 00° C. for 30 minutes in an inert atmosphere. Further, in the PCh transistor, since the gate insulating film blocks phosphorus from entering, phosphorus does not diffuse. )
. Subsequently, the a-8iOxPy layer is removed [first
Figure (f)].

(5) Next, boron ions are implanted by photolithography, leaving a resist in the Nch transistor section [FIG. 1(g)]. As mentioned above, in order to obtain good ohmic contact with a P-type semiconductor, an impurity concentration of 1X10''/d or more is sufficient, and in this example, the implantation amount was 5×10'□'/al. This is because f(!!edge damage due to the charged up charge is less than 110"/-).

(6) Next, as shown in FIG. 1(e), after depositing a two-layer green film 5 and opening source/drain contact holes, a wiring material 6 was formed.

A second aspect of the present invention will be explained according to FIG.

(1) After thoroughly cleaning an insulating substrate (eg, glass, ceramic) whose surface has been sufficiently polished, a semiconductor material layer (amorphous-8i, polycrystalline Si, or compound semiconductor) 2 is formed. In this embodiment, polycrystalline Si is deposited to a thickness of 500 Å or more, preferably 100 OA, by low pressure CVD. This semiconductor layer 2 is separated and formed into island shapes by photolithography and etching [see FIG. 2(a)].

~ (2) Next, the M edge film 3 is formed on the surface of the semiconductor layer 2 [see FIG. 2(b)].

The insulating film 3 may be SiO2, 5j3N4 by CVD method, but since it will be a gate insulating film, the polycrystalline Si layer 2 is dry thermally oxidized at 1000°C to a thickness of 500 Å or more, preferably 8
It is desirable to form the insulating film by 0.00 people and to obtain a high quality insulating film.

Next, layer 4 (AQ, metal silicide,
A high-melting point metal, polycrystalline silicon, etc. (polycrystalline silicon in this example) is used to form 3000A.

(3) Perform desired patterning on photo 1 by lithography and etching to obtain gate electrode 4 [second
See figure (C)].

(4) Next, boron ions are implanted by photolithography, leaving a resist in the Nch transistor section. As mentioned above, in order to obtain good ohmic contact with a P-type semiconductor, an impurity concentration of 1X1018/- or more is sufficient and in this example, the implantation amount was 5X1014/ci. The dielectric breakdown due to the charged up charge is lXl0
This is because there are almost no cases below 15/ci [Figure 2 (
See d)].

(5) Next, the gate insulating film at the portions corresponding to the source/drain regions of the Nch transistor is etched away by photolithography. The etching method used at this time was wet etching that provided a selectivity to the gate electrode material, and the etchant used was a mixed solution of hydrofluoric acid and ammonium fluoride (buffered hydrofluoric acid).

(6) Next, a coating film (Spin on Glass) containing at least one of the elements phosphorus, arsenic, and antimony is applied.
s:5OG)7. In this example, SOG containing phosphorus was coated to a thickness of 1000K, and subsequently an interlayer insulating film 5 was deposited. This layer consists of SiO2 film, Si3N
In the present invention, a film of 200 OA or more, preferably 50 OA, is deposited by low-pressure CVD (see Fig. 0-2 (e)).

(7) Next, annealing is performed to activate B+ ions implanted into the source/drain regions of the Pch transistor, and to thermally diffuse phosphorus atoms contained in the SOG film into the source/drain regions of the Nch transistor. The annealing temperature at this time is 600℃ or higher.

It is preferably carried out at 900° C. for 30 minutes in an inert atmosphere. Under these conditions, the surface impurity concentration of active NSi is 5 x 102
0/a+? This is because there is no problem with ohmic contact. Also, in the Pch transistor, the gate 1IA
Since the n film blocks phosphorus intrusion, phosphorus does not diffuse.

(8) After opening source/drain contact holes as shown in FIG. 2(f), wiring material 6 was formed.

A third aspect of the present invention will be explained according to FIG.

(1) After thoroughly cleaning the insulating substrate 1 whose surface has been sufficiently polished (for example, glass or ceramics), a semiconductor material layer (amorphous-8i, polycrystalline Si, or
Compound semiconductor) 2 is formed. In this example, polycrystalline Si
500 Å or more, preferably 10 Å or more, by low pressure CVD method.
Deposit 0OA. This semiconductor layer 2 is separated and formed into island shapes by photolithography and etching [see FIG. 3(a)].

(2) Next, an insulating film 3 is formed on the surface of the semiconductor layer 2 [see FIG. 3(b)].

The insulating film 3 may be made of Sj○2, Si, or N by CVD, but since it will be a gate insulating film, the polycrystalline Si layer 2 is dry thermally oxidized at 1000°C to a thickness of 500 Å or more, preferably 8
It is desirable to form the insulating film by 0.00 people and to obtain a high quality insulating film.

Next, a layer 4 (AQ, - metal silicide, high melting point metal, polycrystalline silicon, etc.) that becomes the gate electrode.

In this example, 3000 polycrystalline silicon (polycrystalline silicon) are formed.

(3) Perform desired patterning by photolithography and etching to obtain the gate electrode 4 [see FIG. 3(c)].

(4) Next, by photolithography, Nch
The gate insulating film at the portion corresponding to the source/drain region of the transistor is removed by etching to expose the source/drain region of the Nch transistor section [Figure 3(d)]
reference〕.

(5) Next, a resist film is left on the Nch transistor part using photolink roughy, and this resist film is
Boron B+ ions are implanted into the Pch transistor part as a mask for the ch transistor part [Fig. 3(e)]
].

The dose amount is 1xlO''/c+#, which prevents the problem of breakdown of the insulating film due to charge-up.

(6) Next, a glabellar insulating film 8' is deposited. This layer is
A 5in2 film, a Si3N film, a silicon oxide film containing nitrogen (Si○N), or the like may be used. In this example, a thickness of 2000 Å or more, preferably 6000 Å, was deposited by low pressure CVD. Further, on this glabellar insulating film 8', a PSG film 8' containing at least one of the elements phosphorus, arsenic, and antimony, and containing 5 mol% of phosphorus in this example, was deposited (see FIG. 3). f) see]. Note that (5) and (6) may be performed in the reverse order.

(7) Next, by annealing, B1 ion-implanted into the source/drain region of the PCh transistor is activated, and the interlayer IIl! is applied to the source/train region of the Nch transistor. The phosphorus atoms contained in the edge film 5 are thermally diffused. This annealing is performed at a temperature of 600° C. or higher, preferably 900° C., for 30 minutes in an inert atmosphere. Under this condition, the surface impurity concentration of the active layer Si is I x 10
” / a+?, and there is no problem with ohmic contact.

Further, in the PCh transistor, since the gate insulating film blocks phosphorus from entering, phosphorus does not diffuse.

Thereafter, as shown in FIG. 3(g), after contact holes for source and drain were opened, wiring material 6 was formed.

〔effect〕

By thermal diffusion, the resistance of the source and drain of the Nch transistor was reduced, thereby forming an ohmic contact.

Furthermore, this diffusion method eliminates defects such as insulation film breakdown due to charge-up, which had occurred with the ion implantation method, and improved yield.

Furthermore, planarization has been achieved using SOG, and the step coverage of Afl wiring has increased from 35% to 5%.
0%, which is an improvement, and the failure mode due to Afl disconnection has decreased.

[Brief explanation of drawings]

Figure 1 (a)', (b), (c), (d)
, (e), (f), (g) and (h) are manufacturing process diagrams explaining the first embodiment of the present invention, and FIG.
a), (b), (C), (d), (e
) and (f) are manufacturing process diagrams explaining the second embodiment of the present invention, and FIGS. 3(a), (b), (c),
(d), (e), (f) and (g) are manufacturing process diagrams illustrating the third embodiment of the non-explosion method. l...Insulating substrate 2...Semiconductor layer 3...Gate 1MAa film 4...Gate electrode 5...Interlayer insulating film 6...Wiring electrode 7...5OG 8- a -S i Ox P y N8'...PS
G film 9...resist

Claims (1)

[Claims] 1. A C-MOS semiconductor device comprising a thin film transistor fabricated on an insulating substrate, characterized in that only the Nch transistor has a shape in which a portion of the gate insulating film is removed. 2. After forming a semiconductor layer in an island shape on an insulating substrate, forming an insulating film on the surface thereof, and removing at least part of the gate insulating film in the source/drain region of the Nch transistor part,
An a-SiOxPy layer is formed, then thermal diffusion treatment is performed to diffuse P into the source/drain region of the Nch transistor section, the a-SiOxPy layer is removed, the Nch transistor section is resisted, and the source/drain region of the Pch transistor section is removed. By implanting boron ions into the drain region, Pch
2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming source/drain regions of a transistor section. 3. After forming a semiconductor layer in the form of an island on an insulating substrate, an insulating film is formed on its surface, and a source/drain region of a Pch transistor part is formed by boron ion implantation.
After removing at least part of the gate insulating film in the source/drain region of the transistor section, an SOG film containing Nch forming impurities is formed, and thermal diffusion treatment is performed to form the source/drain regions of the Nch transistor section. 2. A method for manufacturing a semiconductor device according to claim 1. 4. After forming a semiconductor layer in an island shape on an insulating substrate, forming an insulating film on the surface thereof and removing at least part of the gate insulating film in the source/drain region of the Nch transistor part, (a) Nch A step of resisting the transistor part and implanting boron ions into the Pch transistor part, and (b) forming an interlayer insulating film containing impurities for Nch formation,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the two steps of forming the source/drain regions of the Nch transistor portion by thermal diffusion treatment are performed in any order.