KR940004252B1 - Isolation method with local polyoxide - Google Patents
Isolation method with local polyoxide Download PDFInfo
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- KR940004252B1 KR940004252B1 KR1019900021826A KR900021826A KR940004252B1 KR 940004252 B1 KR940004252 B1 KR 940004252B1 KR 1019900021826 A KR1019900021826 A KR 1019900021826A KR 900021826 A KR900021826 A KR 900021826A KR 940004252 B1 KR940004252 B1 KR 940004252B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Abstract
Description
제1도는 종래의 로코스(LOCOS)를 이용한 소자격리제조방법을 나타낸 단면도.1 is a cross-sectional view showing a device isolation manufacturing method using a conventional LOCOS.
제2도는 본 발명의 로컬폴리 산화물 소자분리방법을 이용한 제1의 공정을 나타낸 단면도.2 is a cross-sectional view showing a first process using the method for separating a local poly oxide device of the present invention.
제3도는 본 발명의 로컬폴리 산화물 소자분리방법의 제2의 공정을 나타낸 단면도.3 is a cross-sectional view showing a second step of the method for separating a local poly oxide device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 21, 31 : 실리콘기판 15, 25 : 폴리실리콘1, 21, 31: silicon substrate 15, 25: polysilicon
2, 22, 32 : 산화막 16, 26 : 폴리산화막2, 22, 32: oxide film 16, 26: polyoxide film
3, 23, 33 : 질화막 17, 27 : 필드산화막3, 23, 33: nitride film 17, 27: field oxide film
4, 24, 34 : 감광막 28 : 스페이스4, 24, 34: photosensitive film 28: space
본 발명은 반도체소자격리 제조방법에 관한 것으로, 특히 기존의 폴리실리콘을 이용하여 로코스(LOCOS : Local oxida-tion of silicon) 방법에서 발생하는 버드즈빅(Bird's beak새의 부리형상)을 제거하고 불순물의 재분산 없는 전기적 특성이 좋은 소자를 개발하기 위한 로컬폴리 산화물을 이용한 격리제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device isolated, and in particular, using polysilicon to remove Bud's beak (Bird's beak bird's beak shape) generated by the LOCOS method and removing impurities The present invention relates to an isolation manufacturing method using local poly oxide for the development of devices with good electrical properties without redispersion.
일반적으로 반도체의 고집적화에 관한 연구가 진행되어 감에 따라 소자를 분리하는 기술은 칩 에레이(Chip Area)상에 중요 문제로 대두되었고 현재 64MDRAM를 제조하는데 있어서는 0.5um 이하까지 소자간의 분리를 필요로 하며 이러한 문제를 해결하기 위하여 LOCOS방법에서의 버드즈빅(Bird's beak)를 줄일 수 있는 많은 격리(Isolation) 방법들이 제안되고 있다.In general, as the research on the high integration of semiconductors has progressed, the technology of device separation has emerged as an important problem on the chip area. Currently, in the manufacture of 64MDRAM, the separation between devices is required to less than 0.5um. In order to solve this problem, many isolation methods have been proposed to reduce Bird's beak in the LOCOS method.
이에 따라서 트렌치(Trench)를 이용한 격리(Isolation) 방법은 개발초기에 많은 관심이 집중되었으며 현재도 연구가 진행되고 있지만 아직까지도 트렌치(Trench)를 이용한 격리(Isolation) 방법들에는 프로세스(Process)와 전기적 특성에 많은 문제가 남아 있다.Accordingly, the isolation method using trenches has been focused on the early stages of development, and although the research is still underway, the process of isolation and isolation methods using trenches is still used. Many problems remain with the properties.
따라서 현재의 제안된 격리(Isolation) 방법들 중에서 16MDRAM에 가장 많이 사용하는 격리(Isolation) 방법은 로코스(LOCOS) 제조공정을 개량한 방법들이며 이런 평면을 이용한 제조공정으로 소자에 적용가능한 소자분리의 한계는 0.7um 정도이다.Therefore, among the currently proposed isolation methods, the isolation method most commonly used in 16MDRAM is an improvement of the LOCOS manufacturing process. The limit is about 0.7um.
이를 위하여 본 발명에서는 평면을 이용한 격리(Isolation) 방법의 하나로 폴리실리콘(Polysilicon)을 이용하여 로코스(LOCOS) 방법에서 발생하는 버드즈빅(Bird's beak)를 없애고 불순물의 재분산(Redistribution)을 줄여 16Mbit 이상의 고집적 소자개발에 필수적인 0.5um의 격리(Isolation)에서도 전기적 특성이 양호한 소자분리법을 개발함으로써 칩의 면적을 줄이기 용이하며 고집적화에 적용가능한 것이다.To this end, the present invention eliminates Bird's beak generated in the LOCOS method by using polysilicon as one of the isolation methods using a plane, and reduces redistribution of impurities to 16 Mbit. Even in the isolation of 0.5um, which is essential for the development of highly integrated devices, the device isolation method having good electrical characteristics can be developed to reduce the chip area and be applicable to high integration.
제1도는 종래의 로코스(LOCOS) 방법을 이용한 소자격리 제조방법을 나타낸 것으로, 제1a도는 실리콘기판(1) 상면에 산화막(2)를 소정의 두께로 증착하고, 그위에 질화막(3)을 소정의 두께로 증착하는 과정을 나타낸 것이다.FIG. 1 shows a device isolation manufacturing method using a conventional LOCOS method. FIG. 1A deposits an oxide film 2 to a predetermined thickness on an upper surface of a silicon substrate 1 and deposits a nitride film 3 thereon. The process of depositing a predetermined thickness is shown.
제1b도는 상기의 위에 감광막(4)을 형성하고 포토리소그라픽공정을 이용하여 질화막(3)의 패턴을 형성한다.In FIG. 1B, the photosensitive film 4 is formed on the above, and the pattern of the nitride film 3 is formed using a photolithographic process.
제1c도는 채널스톱(Channel Stop)을 위한 불순물(L2P)을 주입시킴으로써 산화를 실시하는 과정을 나타낸 것이다.FIG. 1c illustrates a process of oxidizing by injecting impurities (L 2 P) for channel stop.
제1d도는 소자격리 산화막(5)을 기르는 과정을 나타낸 것이다.1D illustrates a process of growing the device isolation oxide film 5.
제1e도는 질화막(3)을 식각하고, 또한 산화막(2)를 식각함으로써 산화막(6)를 형성한다.In FIG. 1E, the oxide film 6 is formed by etching the nitride film 3 and etching the oxide film 2.
상기의 제조공정에서, 채널스톱을 위한 불순물이 주입될 때, 재분산도어 소자격리를 위한 산화물의 버드즈빅이 커지는 문제점을 가지게 된다.In the above manufacturing process, when the impurity for the channel stop is injected, there is a problem that the Budsvik of the oxide for the redispersion door device isolation becomes large.
이에 따라서 본 발명은 로코스(LOCOS) 방법에 의해 발생되는 버드즈빅(Bird's beak)을 없애고 불순물의 재분산이 없는 전기적 특성이 좋은 소자를 개발하기 위한 로컬폴리 산화물을 이용한 제조방법을 제공하는 것을 그 목적으로 한다.Accordingly, the present invention provides a manufacturing method using a local poly oxide to eliminate the Bird's beak generated by the LOCOS method and to develop a device having good electrical characteristics without redispersion of impurities. The purpose.
이하 첨부도면에 따라 본 발명의 제조과정을 설명하면 다음과 같다.Hereinafter, the manufacturing process of the present invention according to the accompanying drawings.
제2도는 본 발명의 소자격리를 형성하는 제1의 공정과정을 나타낸 것으로, 제2a도는 실리기판(1)위에 산화막(12)를 10∼100nm 정도의 두께로 증착하고, 그 상면에 질화막(3)를 100∼200nm 정도의 두께로 증착하는 과정을 나타낸 것이다.FIG. 2 shows a first process for forming the device isolation of the present invention, and FIG. 2A shows the deposition of an oxide film 12 on the silicon substrate 1 to a thickness of about 10 to 100 nm and the nitride film 3 on the upper surface thereof. ) Shows a process of depositing a thickness of about 100 ~ 200nm.
제2b도에서는 감광막(Photoresist)(14)를 증착하고 포토리소그라피 (Photolithography) 공정을 이용하여 질화막(13)의 패턴(Pattern)을 만든다.In FIG. 2B, a photoresist 14 is deposited and a pattern of the nitride layer 13 is formed by using a photolithography process.
제2c도는 채널정지(Channel Stop)을 위한 불순물(1E13-1E15)을 주입한다.In FIG. 2C, impurities 1E13-1E15 are injected for channel stop.
제2d도는 소자격리를 위한 소자격리 산화물을 만들기 위하여 폴리실리콘막 (Polysilicon)(15)를 100∼400nm 정도의 두께로 형성하는 과정을 나타낸 것이다.2d illustrates a process of forming a polysilicon film 15 to a thickness of about 100 to 400 nm in order to make a device isolation oxide for device isolation.
제2e도는 폴리산화물(Poly oxide)를 제조하기 위해서 폴리실리콘(15)을 산화(oxidation)한 후 폴리산화막(16)을 증착한 과정을 나타낸 것이다.2e illustrates a process of depositing a poly oxide film 16 after oxidizing the polysilicon 15 to manufacture a poly oxide.
제2f도는 폴리산화막(16)을 질화막(13) 상측까지 에칭백(Etch back) 식각을 실시한 후, 소자격리를 위한 필드산화막(Field oxide)(17)이 형성된 과정을 나타낸 것이다.FIG. 2F illustrates a process in which the poly oxide film 16 is etched back to the upper side of the nitride film 13, and then a field oxide 17 is formed for device isolation.
제2g도는 질화막(3)과 산화막(12)를 차례로 에칭한 후의 형태로 나타낸 것이다.2g shows the form after etching the nitride film 3 and the oxide film 12 in sequence.
제3도는 본 발명의 소자격리를 형성하는 제2의 과정을 나타낸 것으로 제3a도는 실리콘기판(21)위에 산화막(22)를 약 10∼100nm 정도의 두께로 증착하고, 그 상면에 질화막(23)를 약 100∼200nm 정도의 두께로 증착한다.FIG. 3 shows a second process of forming the device isolation of the present invention. FIG. 3A shows that the oxide film 22 is deposited on the silicon substrate 21 to a thickness of about 10 to 100 nm, and the nitride film 23 is formed on the upper surface thereof. Is deposited to a thickness of about 100-200 nm.
제3b도는 상기의 상면에 감광막(24)를 증착하고, 포토리소그라피 (Photolithograph) 공정을 이용하여 질화막(23)의 패턴을 형성한다.In FIG. 3B, the photoresist film 24 is deposited on the upper surface, and a pattern of the nitride film 23 is formed by using a photolithograph process.
제3c도는 폴리실리콘(Polysilicon)막(25)의 산화진행시 실리콘기판(1)의 면이 산화되는 것을 없애기 위하여 질화막 또는 산화막의 측면에 산화스페이스 (28) (oxide spacer)을 형성하고 채널정지(Channel stop)을 위한 불순물(1E13∼1E15)을 주입하는 과정을 나타낸 것이다.FIG. 3C shows an oxide spacer 28 on the side of the nitride film or the oxide film to prevent oxidation of the surface of the silicon substrate 1 during oxidation of the polysilicon film 25, and stops the channel ( A process of injecting impurities 1E13 to 1E15 for channel stop is shown.
제3d도는 상기의 위에 폴리실리콘막 약 100∼400nm 정도의 두께로 제3e도는 폴리산화물(Poly oxide)를 제조하기 위해서 폴리실리콘(25)을 산화한 후 폴리산화막 (26)을 식각하는 과정을 나타낸 것이다.FIG. 3d illustrates a process of etching the polyoxide film 26 after oxidizing the polysilicon 25 to produce a poly oxide having a thickness of about 100 to 400 nm. will be.
제3f도는 폴리산화막(26)을 질화막(23) 상측까지 에칭백(etch back) 실시한 후, 소자격리를 위한 필드산화막(27)이 형성된다.In FIG. 3F, after the poly oxide film 26 is etched back to the upper side of the nitride film 23, a field oxide film 27 for device isolation is formed.
제3g도는 질화막(23)과 산화막(22)를 차례로 에칭한 후의 형태를 나타낸 것이다.FIG. 3G shows the form after the nitride film 23 and the oxide film 22 are sequentially etched.
따라서 본 발명은 종래의 공정에 비하여 폴리실리콘막(Poly silicon)을 형성하여 산화시키고 에칭백(Etch back) 공정이 추가되지만 비교적 공정이 간단하고 소자분리 산화물을 위하여 폴리실리콘을 이용하기 때문에 채널정지를 위한 불순물의 재분산이 없고 소자분리를 위한 산화물 버드즈빅(Bird's beak)이 커지지 않는다.Therefore, the present invention forms and oxidizes a polysilicon film and adds an etching back process as compared to the conventional process, but the process is relatively simple and the channel is stopped due to the use of polysilicon for device isolation oxide. There is no redispersion of impurities and no oxide bird's beak for device isolation.
Claims (4)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900021826A KR940004252B1 (en) | 1990-12-26 | 1990-12-26 | Isolation method with local polyoxide |
| JP3330620A JPH05182959A (en) | 1990-12-26 | 1991-12-13 | Method of isolating semiconductor element utilizing local polyoxide |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900021826A KR940004252B1 (en) | 1990-12-26 | 1990-12-26 | Isolation method with local polyoxide |
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| Publication Number | Publication Date |
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| KR920013611A KR920013611A (en) | 1992-07-29 |
| KR940004252B1 true KR940004252B1 (en) | 1994-05-19 |
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| KR1019900021826A KR940004252B1 (en) | 1990-12-26 | 1990-12-26 | Isolation method with local polyoxide |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100227189B1 (en) * | 1996-09-23 | 1999-10-15 | 김영환 | Method of forming an element isolation region in a semiconductor device |
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1990
- 1990-12-26 KR KR1019900021826A patent/KR940004252B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100227189B1 (en) * | 1996-09-23 | 1999-10-15 | 김영환 | Method of forming an element isolation region in a semiconductor device |
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| KR920013611A (en) | 1992-07-29 |
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