JP3107848B2 - Method for manufacturing semiconductor device including non-volatile memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EPROM or an EEPROM.
FAMOS (Floating-gate Avalan used for M etc.
The present invention relates to a method for manufacturing a semiconductor device including a non-volatile memory ( che-injection Metal-Oxide Semiconductor) .

[0002]

2. Description of the Related Art There are a three-layer polysilicon process and a two-layer polysilicon process for manufacturing a semiconductor device including a FAMOS memory which is a nonvolatile memory and a peripheral MOS transistor.

The three-layer polysilicon process is performed as shown in FIG. The left side is the EPROM section, and the right side is the peripheral section. (A) A field oxide film 4 is formed on a substrate 2, and a gate oxide film 6 is formed to a thickness of, for example, about 300 °. Approximately 2000 of polysilicon film for floating gate
A polysilicon film for a control gate is formed to a thickness of about 3500 through an interlayer film 10 having a thickness of about 400 mm.
Å thickness. Thereafter, patterning is performed by photolithography and etching to form a stacked gate electrode including the floating gate 8, the interlayer film 10, and the control gate 12. (B) Using the gate oxide film 6 of the EPROM as a through oxide film, boron ions are implanted for channel doping for threshold control of the peripheral portion. Injection energy 30 KeV
The implantation amount is about 10 ¹² / cm ³ . (C) Thereafter, the through oxide film 6 is removed, and a gate oxide film 14 in the peripheral portion is formed to a thickness of about 200 °. (D) Thereafter, a polysilicon film 16a is deposited to a thickness of about 3500 °, and phosphorus glass is deposited to form a polysilicon film 1a.
6a is reduced in resistance and its phosphorus glass is removed. (E) The polysilicon film 16a is patterned by photolithography and etching to form a peripheral gate electrode 16.

FIG. 4 illustrates a two-layer polysilicon process. (A) A field oxide film 4, a gate oxide film 6 and a floating gate 8 of an EPROM portion are
It is formed by patterning a polysilicon film having a thickness of Å. In the peripheral portion, channel doping is performed using the gate oxide film 6 as a through oxide film. (B) Thereafter, the through oxide film 6 is removed, and a gate oxide film 14 in the peripheral portion is formed. At this time, in the EPROM portion, the surface of the floating gate 8 is oxidized and
Is formed to a thickness of about 400 °. (C) A polysilicon film 16a is deposited, and phosphorus is introduced to reduce the resistance. (D) The EPROM portion is patterned by photolithography and etching to form a stack gate electrode including the floating gate 8, the interlayer film 10, and the control gate 12. Reference numeral 18 denotes a resist for this patterning. (E) The peripheral portion is patterned by photolithography and etching to form the gate electrode 16. Reference numeral 20 denotes a resist for patterning.

[0005]

When channel doping of the peripheral portion is performed by the conventional method, from the formation of the gate oxide film of the EPROM used for the through oxide film for channel doping until the channel doping is performed. In the three-layer polysilicon process, there are steps of etching a polysilicon film, an oxide film, and a polysilicon film. In the two-layer polysilicon process, a polysilicon film is deposited, a phosphorus glass is deposited, and a polysilicon film is deposited. Etching. Therefore, during the process from the deposition of the polysilicon film to the etching of the polysilicon film, the damage to the substrate in the peripheral channel region remains on the substrate, and the gate during the peripheral gate oxidation in the subsequent process is not removed. It is taken into the oxide film. As a result, a gate oxide film reflecting the defect structure grows, and a B-mode failure of 5 to 7 MV / cm occurs in the gate oxide film breakdown voltage. Withstand voltage of 10 MV / c for high quality gate oxide film
m.

EPRO used for through oxide film in the peripheral part
Although the gate oxide film of M is slightly etched in the over-etching time of the dry etching of the polysilicon film in the previous process, the film is reduced by the etching. Since the selection ratio of the oxidation-resistant film of the polysilicon etch rate is usually 6 to 9, about 1/6 to 1/9 of the polysilicon film is reduced. Therefore, the in-plane uniformity of the thickness of the through oxide film is (in-plane uniformity at the time of formation) + (the in-plane uniformity of the oxidation-resistant film selectivity of the polysilicon etch) + (the uniformity of the thickness of the polysilicon layer). (Variation depending on the location of the overetch time)), which is extremely poor. Therefore,
The profile of the channel dope impurity in the depth direction varies in the wafer surface, and the threshold value also varies in the wafer surface.

In order to solve these problems, the gate oxide film of the EPROM exposed before the channel doping in the peripheral portion is removed and oxidized again to form an oxide film having a thickness of, for example, about 400 °. Then, channel doping is performed using the new oxide film as a through oxide film, and then, the through oxide film is removed to form a new peripheral gate oxide film. As described above, by oxidizing the channel region that has been damaged in the previous process, defects are taken into the oxide film, and then the oxide film is removed and a gate oxide film is formed again. And a high quality oxide film having a uniform gate oxide film and a high withstand voltage can be obtained. By forming a new through oxide film uniformly, the profile of the implanted impurity in the depth direction is also controlled uniformly, and the variation in the threshold value in the well surface can be suppressed. There is also an advantage that the substrate can be protected from damage due to implantation.

However, when such sacrificial oxidation for so-called channel doping is performed, the already formed EPRO is formed.
Since the floating gate and the control gate of M are oxidized, bird's beaks of the oxide film penetrate into the oxide film 10 between the floating gate 8 and the substrate 2 and between the floating gate 8 and the control gate 12, as shown in FIG. As a result, the thickness of the gate oxide film at the drain end of the EPROM or the oxide film between the floating gate 8 and the control gate 12 is increased, and the vertical electric field is weakened.

The present invention suppresses the deterioration of the gate oxide film in the peripheral portion and the in-plane variation of the channel dope impurity,
An object of the present invention is to provide a manufacturing method capable of preventing a decrease in on-current and a deterioration in writing characteristics due to generation of a bird's beak in a stack gate of a PROM.

[0010]

According to the present invention, a FAMOS
Gate oxide film of memory part and floating gate
After the formation of the gate oxide film and before performing the channel doping ion implantation for the threshold control of the peripheral MOS transistor portion , the oxide film also formed in the peripheral MOS transistor portion at the time of forming the gate oxide film of the FAMOS memory portion in the previous process. Oxidation in a dry oxygen atmosphere of 950 ° C. or more while leaving
Thereafter, before performing the etching step , channel doping of the peripheral MOS transistor is performed through an oxide film in which the oxide film formed in this oxidation step and the remaining oxide film are combined. The remaining oxide film is removed, and a gate oxide film of the peripheral transistor portion is formed again.

When the present invention is applied to a three-layer polysilicon process, after forming a gate oxide film of a FAMOS memory portion and a stack gate electrode for FAMOS thereon,
A resist pattern having an opening in the FAMOS memory section is formed by photolithography, and the source
After removing the gate oxide film on the drain region, the FA
Impurity is implanted into the source / drain regions of the MOS memory portion, and thereafter, oxidation is performed in a dry oxygen atmosphere at 950 ° C. or higher. Through the channel doping of the peripheral MOS transistor portion.

[0012]

FIG. 1 shows an embodiment in which the present invention is applied to a method of manufacturing a three-layer polysilicon process. The left side of the figure is a memory transistor portion, and the right side is a peripheral portion. In the peripheral portion, for example, a CMOS is formed. (A) A field oxide film 4 and a gate oxide film 6 having a thickness of about 300 DEG are formed on a silicon substrate 2, a first polysilicon film having a thickness of about 2000 DEG is formed thereon, and a film thickness of about 400 DEG is formed thereon. A polysilicon film having a thickness of about 3000 Å as a second layer is formed thereon, and patterned by photolithography and etching to form a floating gate 8, an interlayer film 10 and a control gate 12. I do. (B) A resist pattern 30 having an opening in the EPROM portion is formed by photolithography, and the gate oxide film 6 exposed in the EPROM portion is removed.
Impurities are implanted into the drain region. The impurity is, for example, arsenic as an N-type impurity, the implantation energy is about 50 KeV, and the implantation amount is about 6 × 10 ¹⁵ / cm ³ . (C) After removing the resist 30, drive heat treatment of the source / drain regions 32 and 34 is performed in a dry oxygen atmosphere. The conditions at this time are, for example, 950 ° C. for 50 minutes, the atmosphere is O ₂ at 9000 cc / min, and N ₂ is 1800
0 cc / min ₂ and 500 cc / min HCl. By this heat treatment, the source / drain regions 32, 3 of the EPROM are
4 is activated and the source / drain region 3 is activated.
An oxide film 36 of about 450.degree. Is formed on the substrates 2, 34, and an oxide film of about 150.degree. Is formed on the substrate. An oxide film is also formed on the gate oxide film 6 for EPROM which has been left before. This results in an oxide film having a total thickness of about 450 °. this is,
Since many oxygen atoms enter the thin portion of the oxide film and oxygen atoms do not easily enter the thick portion, the oxide film 36 has a substantially uniform thickness as a whole. (D) Using the oxide film 36 as a through oxide film, channel-doped polon is implanted into the peripheral portion. The injection energy is 30
At KeV, the implantation dose is about 10 ¹² / cm ³ . (E) After that, after removing the through oxide film 36, a gate oxide film 38 is newly formed on the peripheral portion, and the gate of the peripheral portion is formed by depositing polysilicon film, depositing phosphorus glass, removing phosphorus glass, and patterning the polysilicon film. An electrode 16 is formed.

FIG. 2 shows an embodiment in which the present invention is applied to a two-layer polysilicon process. (A) A field oxide film 4, a gate oxide film 6, and a floating gate 8 are formed on a silicon substrate 2. (B) By oxidizing in a high-temperature dry oxygen atmosphere of 950 ° C. or more, the through oxide film 36 of uniform film quality is formed by supplementing the thin portion of the old EPROM gate oxide film. (C) Using this oxide film 36 as a through oxide film, channel doping of the peripheral portion is performed. The conditions for channel doping are the same as in FIG. (D) After removing the through oxide film 36, a peripheral gate oxide film 38 is formed, a second polysilicon film is deposited, the resistance is reduced by introducing phosphorus, and the pattern of the polysilicon film is reduced. Of the peripheral gate electrode 16 and EP
The control gate 12 of the ROM is formed.

[0014]

According to the method of the present invention, the oxide film between the substrate and the floating gate of the EPROM and between the floating gate and the control gate does not penetrate into the oxide film, the film thickness is uniform, and the substrate surface is damaged. Since a through oxide film for channel doping incorporating the layer can be formed, the withstand voltage characteristics of the peripheral gate oxide film can be improved without deteriorating the EPROM characteristics, and the in-plane variation of the threshold voltage can be improved. Can also be suppressed. If the present invention is applied to a three-layer polysilicon process of an on-chip EPROM, the drive and impurity activation of the EPROM source / drain and the formation of a through oxide film in the peripheral portion can be performed at the same time, so that the process can be shortened. .

[Brief description of the drawings]

FIG. 1 is a process sectional view showing an embodiment in which the present invention is applied to a three-layer polysilicon process.

FIG. 2 is a process sectional view showing an embodiment in which the present invention is applied to a two-layer polysilicon process.

FIG. 3 is a process sectional view showing a conventional three-layer polysilicon process.

FIG. 4 is a process sectional view showing a conventional two-layer polysilicon process.

FIG. 5 is a partial cross-sectional view showing a problem due to sacrificial oxidation.

[Explanation of symbols]

 Reference Signs List 2 silicon substrate 6 gate oxide film 8 floating gate 10 interlayer oxide film 12 control gate 16 peripheral gate electrode 32, 34 source / drain region of EPROM 36 through oxide film 38 peripheral gate oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device including a FAMOS memory section and the peripheral MOS transistor portion, FAM
Gate oxide film of OS memory part and floating on it
After the formation of the gate, before performing the channel-doped ion implantation for threshold control of the peripheral MOS transistor portion, the gate oxide film type of the FAMOS memory portion in the previous process is formed.
Oxide film is also formed in the peripheral MOS transistor section when formed
Performs oxidation in a dry oxygen atmosphere of more than 950 ° C., leaving the after this, before performing the etching step, the oxide that had left the oxide film formed in this oxidation process
A method for manufacturing a semiconductor device, comprising the steps of: performing channel doping of a peripheral MOS transistor through an oxide film combined with a film; removing the exposed oxide film after the channel doping; and forming a gate oxide film of the peripheral transistor portion again. . 2. A three-layer polysilicon process, comprising:
Gate oxide film of AMOS memory section and FAMO on it
After the stack gate electrode for S is formed, a resist pattern having an opening in the FAMOS memory portion is formed by photolithography, and the gate oxide film on the source / drain region of the FAMOS memory portion is removed. Implanting impurities into the drain region, and then oxidizing in a dry oxygen atmosphere at 950 ° C. or higher,
2. The method of manufacturing a semiconductor device according to claim 1, wherein channel doping of the peripheral MOS transistor portion is performed through the gate oxide film in the peripheral MOS transistor portion and the oxide film formed by oxidation in the dry oxygen atmosphere.