KR0142641B1 - Nonvolatile Memory Cell Manufacturing Method - Google Patents
Nonvolatile Memory Cell Manufacturing MethodInfo
- Publication number
- KR0142641B1 KR0142641B1 KR1019940022557A KR19940022557A KR0142641B1 KR 0142641 B1 KR0142641 B1 KR 0142641B1 KR 1019940022557 A KR1019940022557 A KR 1019940022557A KR 19940022557 A KR19940022557 A KR 19940022557A KR 0142641 B1 KR0142641 B1 KR 0142641B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon layer
- film
- oxide film
- memory cell
- self
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
본 발명은 비휘발성 메모리 셀 제조방법에 관한 것으로, 플로팅 게이트용 제1 폴리실리콘층의 1 차 식각공정시 노출부위의 제 1 폴리실리콘층을 완전히 식각하지 않고 소정의 두께로 남긴 후 이 남은 부분의 제 1 폴리실리콘층을 산화공정에 의해 산화시켜 이 산화된 부분을 후공정인 자기정렬 식각공정시 기판 손상(Substrate Attack)을 방지하는 막으로 사용함으로써 소자의 수율 및 신뢰성을 향상시킬 수 있는 비휘발성 메모리 셀 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a nonvolatile memory cell, wherein the remaining portion of the first polysilicon layer for floating gates after leaving the first polysilicon layer at an exposed portion at a predetermined thickness without being completely etched. Non-volatile which can improve the yield and reliability of the device by oxidizing the first polysilicon layer by an oxidation process and using this oxidized portion as a film to prevent substrate attack during the subsequent self-aligned etching process The present invention relates to a memory cell manufacturing method.
Description
제1도는 일반적인 NOR형 플래쉬 셀의 레이아웃도.1 is a layout diagram of a general NOR flash cell.
제2도는 종래 자기정렬 식각공정후 제1도의 X - X'선을 따라 절단한 단면도.2 is a cross-sectional view taken along the line X-X 'of FIG. 1 after a conventional self-aligned etching process.
제3a 내지 3c도는 본 발명을 설명하기 위해 제1도의 X -X'선을 따라 절단한 단면도.3A to 3C are cross-sectional views taken along the line X-X 'of FIG. 1 to illustrate the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11:실리콘 기관12:필드 산화막11: silicon organ 12: field oxide film
13:터널 산화막14:잔여 폴리실리콘층(제1폴리)13: Tunnel oxide film 14: Residual polysilicon layer (first poly)
14A:산화막14B:잔여 산화막14A: oxide film 14B: residual oxide film
A:비활성영역B:비트라인A: inactive area B: bit line
C:소오스 디퓨젼 라인D:제 1 폴리실리콘층 패턴C: source diffusion line D: first polysilicon layer pattern
E:제2폴리실리콘층 패턴(컨트롤 게이트)F:플로팅 게이트E: Second polysilicon layer pattern (control gate) F: Floating gate
본 발명은 비휘발성 메모리 셀 제조방법에 관한 것으로, 특히 플로팅 게이트용 제 1 폴리실리콘층의 1차 식각공정시 노출부위의 제 1 폴리실리콘층을 완전히 식각하지 않고 소정의 두께로 남긴 후 이 남은 부분의 제 1 폴리실리콘층을 산화공정에 의해 산화시켜 이 산화된 부분이 후공정인 자기정렬 식각공정시 기판 손상(Substrate Attack)을 방지하는 막으로 사용하므로써 소자의 수율 및 신뢰성을 향상 시킬 수 있는 비휘발성 메모리 셀 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a nonvolatile memory cell, and in particular, in the first etching process of the first polysilicon layer for floating gate, the remaining portion after leaving the first polysilicon layer of the exposed portion to a predetermined thickness without being completely etched. The first polysilicon layer is oxidized by the oxidation process, and the oxidized portion is used as a film to prevent substrate attack during the subsequent self-aligned etching process, thereby improving the yield and reliability of the device. A method of manufacturing a volatile memory cell.
비휘발성 메모리 셀은 가장 기본적인 구조가 스택형(Stack Type)으로서 제 1 및 2 폴리실리콘층의 적층으로 이루어지는데, 제조공정중 자기정렬 식각공정시 기판이 손상되는 부위가 발생된다. 기판이 손상될 경우 소자 동작시 누설전류 레벨(Leakage Current Level)이 크게 증가되는 문제가 야기된다.The most basic structure of a nonvolatile memory cell is a stack type, which is a stack of first and second polysilicon layers, and a portion of the substrate is damaged during the self-aligned etching process during the manufacturing process. If the substrate is damaged, a problem arises in that the leakage current level is greatly increased during device operation.
제1도는 NOR형 플래쉬 셀의 일반적인 레이아웃도로서, 이를 참조하여 종래 제조방법에 의한 문제점을 설명하기로 한다. 점선으로 표시된 제 1 폴리실리곤층 패턴(D)은 제 1 폴리 마스크 및 식각작업으로 얻어진 패턴이며, 이 패턴(D)은 이후 제 2 폴리실리콘층 패턴(E)을 마스크로 사용한 자기정렬 식각시 식각되어 제 2 폴리실리콘층 패턴(E) 하단의 빗금친 부분만 남아 플로팅 게이트(F) 역할을 하게된다.FIG. 1 is a general layout diagram of a NOR type flash cell, with reference to which will be described a problem by the conventional manufacturing method. The first polysilicon layer pattern (D) indicated by a dotted line is a pattern obtained by a first poly mask and an etching operation, and the pattern (D) is subsequently etched during self-aligned etching using the second polysilicon layer pattern (E) as a mask. As a result, only the hatched portion of the lower end of the second polysilicon layer pattern E serves as the floating gate F.
제2도는 제1도의 X-X'선을 따라 절단한 소자의 단면도로서, 이 부분은 자기정렬 식각공정시 제 1 폴리실리콘층으로 덮혀있지 않은 관계로 실리콘 기판(1)이 식각되면서 손상이 발생하게 된다. 자기정렬 식각공정은 제 2 폴리 마스크 작업후 감광막으로 덮히지 않은 부분에 대해 차례로 제 2 폴리실리콘층 식각, 층간 절연막 식각, 제 1 폴리실리콘층 식각을 행하게 되는데, X-X'부분은 제 1 폴리실리콘층이 존재하지 않기 때문에 상기 제 1 폴리실리콘층 식각시 기판이 손상된다. 그리고 필드 산화막(2)이 존재하는 부위와 제 1 폴리실리콘층 패턴(D)이 덮힌 부분은 기판손상이 발생하지 않는다.FIG. 2 is a cross-sectional view of the device cut along the line X-X 'of FIG. 1, which is not covered with the first polysilicon layer during the self-aligned etching process, and thus damage occurs as the silicon substrate 1 is etched. Done. In the self-aligned etching process, the second polysilicon layer etching, the interlayer insulating layer etching, and the first polysilicon layer etching are sequentially performed on the portions not covered with the photoresist film after the second poly mask operation. Since the silicon layer does not exist, the substrate is damaged when the first polysilicon layer is etched. In addition, substrate damage does not occur in the portion where the field oxide film 2 exists and the portion where the first polysilicon layer pattern D is covered.
도면에서 미설명 부호(A)는 비활성 영역이며, 부호(B)는 각 단위셀의 드레인이 연결되어 이루어지는 비트라인이며, 부호(C)는 소오스 디퓨젼라인(Source Diffusion Line)이며, 부호(G)는 드레인 콘택부이다. 기판 손상이 발생할 경우, 특히 플래쉬 EEPROM 셀과 같이 소오스 디퓨젼라인에 12 V 정도의 높은 전압이 걸릴 경우에는 누설전류 레벨이 크게 증가할 뿐만 아니라, 추후에 추가적인 폴리실리콘 패턴 형성이나 자기정렬 콘택공정을 위한 절연막 스페이서 형성시 문제가 된다. 상기한 문제를 해결하기 위한 방안으로 제 1 폴리실리콘층의 1 차 식각시 활성영역에 제 1 폴리실리콘층을 남기는 방법이 있는데, 이 경우 제 1 폴리실리콘층과 제 2 폴리실리콘층의 간격확보와 제 1 폴리실리콘층과 필드 산화막의 중첩을 확보하기 위하여 셀 면적의 증가가 불가피하다.In the drawing, reference numeral A denotes an inactive region, reference numeral B denotes a bit line connected to a drain of each unit cell, reference numeral C denotes a source diffusion line, and reference numeral G ) Is a drain contact portion. In the event of damage to the substrate, especially when a high voltage of 12 V is applied to the source diffusion line, such as a flash EEPROM cell, the leakage current level is greatly increased, and additional polysilicon pattern formation or a self-aligned contact process is later performed. This is a problem when forming insulating film spacers. In order to solve the above problem, there is a method of leaving the first polysilicon layer in the active region during the first etching of the first polysilicon layer. In this case, the gap between the first polysilicon layer and the second polysilicon layer In order to secure the overlap of the first polysilicon layer and the field oxide film, an increase in the cell area is inevitable.
따라서 본 발명은 플로팅 게이트용 제 1 폴리실리콘층의 1 차 식각 공정시 노출부위의 제 1 폴리실리콘층을 완전히 식각하지 않고 소정의 두께로 남긴 후 이 남은 부분의 제 1 폴리실리콘을 산화공정에 의해 산화시켜 이 산화된 부분을 후공정인 자기정렬 식각공정시 기판 손상(Substrate Attack)을 방지하는 막으로 사용하므로써 셀 면적의 증가없이 기판 손상을 방지할 수 있는 비휘발성 메모리 셀 제조방법을 제공함에 그 목적이 있다. 이러한 목적을 달성하기 위한 본 발명의 비휘발성 메모리 셀 제조방법은 실리콘 기판 상에 필드 산화막, 터널 산화막, 제 1 폴리실리콘층 및 층간 절연막으로 산화막과 질화막을 형성한 상태에서, 감광막 도포 및 제 1 폴리 마스크 작업으로 감광막을 패턴화하고, 패턴화된 감광막을 이용하여 노출부위의 제 1 폴리실리콘층을 소정두께 식각하여 잔여 폴리실리콘층을 형성하는 단계와, 상기 단계로부터 노출된 잔여 폴리실리콘층에 불순물을 주입한 후 감광막을 제거하고, 전체적으로 산화공정을 실시하여 불순물이 주입된 잔여 폴리실리콘층을 산화시키는 단계와, 상기 단계로부터 제 2 폴리실리콘층 증착 및 자기정렬 식각공정을 실시하는 단계로 이루어지는 것을 특징으로 한다.Therefore, in the present invention, the first polysilicon layer for the floating gate is not etched completely and the first polysilicon layer is left in a predetermined thickness without being completely etched. By oxidizing and using this oxidized portion as a film to prevent substrate attack during the subsequent self-aligned etching process, it provides a method of manufacturing a nonvolatile memory cell that can prevent substrate damage without increasing the cell area. There is a purpose. In the nonvolatile memory cell manufacturing method of the present invention for achieving the above object, the photosensitive film is applied and the first poly is formed in a state in which an oxide film and a nitride film are formed of a field oxide film, a tunnel oxide film, a first polysilicon layer, and an interlayer insulating film on a silicon substrate. Patterning the photoresist layer by a mask operation, etching the first polysilicon layer on the exposed portion using a patterned photoresist to form a residual polysilicon layer, and impurities in the remaining polysilicon layer exposed from the step. And the photoresist film is removed and the oxidation process is performed to oxidize the remaining polysilicon layer into which impurities are injected, and to perform the second polysilicon layer deposition and self-alignment etching process. It features.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3a 내지 3c도는 전술한 제1도의 레이아웃도에서 본 발명의 비휘발성 메모리 셀 제조방법을 설명하기 위해 X - X'선을 절단한 소자의 단면도로서, 이를 참조하여 설명하면 다음과 같다.3A through 3C are cross-sectional views of a device cut along line X-X 'in order to explain the method of manufacturing the nonvolatile memory cell of the present invention in the layout diagram of FIG. 1 described above.
먼저, 실리콘 기판(11)에 웰을 형성한 후 비활성영역(A)에 필드 산화막(12)을 성장시키고, 이후 터널 산화막(13)을 산화공정으로 형성한다. 전체구조 상부에 플로팅 게이트용 제 1 폴리실리콘층을 증착하고 그 상부에 층간 절연막중 일부인 산화막과 질화막을 형성한다. 감광막을 도포한 후 제 1 폴리 마스크로 패턴화한 후 패턴화된 감광막(제1도의 점선부분 D상에만 존재함)을 이용한 제 1 폴리 식각공정을 실시하되 종래와 같이 전부 제거하지 않고 소정두께로 예를들어 약 500 Å 정도로 남긴다. 이로서 기판 손상이 발생될 부위에는 제3a도에 도시된 바와 같이 잔여폴리실리콘층(14)이 남게된다. 이 상태에서 불순물(예를들어,As)을 잔여 폴리실리콘층(14)에 주입하되, 이때 불순물의 농도가 최대가 되는 부분(range of projection ; 이하 RP라 칭함)이 잔여 폴리실리콘층(14)내에 위치하도록 주입에너지를 제어한다. 이후 패턴화된 감광막을 제거한 상태를 제3a도에 도시하고 있다.First, after forming a well in the silicon substrate 11, the field oxide film 12 is grown in the inactive region A, and then the tunnel oxide film 13 is formed by an oxidation process. A first polysilicon layer for floating gate is deposited on the entire structure, and an oxide film and a nitride film, which are part of the interlayer insulating film, are formed thereon. After applying the photoresist film, patterning it with a first poly mask, and then performing a first poly etching process using the patterned photoresist film (only present in the dotted line part D in FIG. 1), but without removing all of them to a predetermined thickness as in the prior art For example, about 500 Å left. This leaves a residual polysilicon layer 14 at the site where substrate damage will occur, as shown in FIG. 3A. In this state, an impurity (for example, As) is injected into the remaining polysilicon layer 14, where a portion of the maximum concentration of the impurity (range of projection; RP) is referred to as the remaining polysilicon layer 14 The injection energy is controlled so as to be located within. Thereafter, a state in which the patterned photosensitive film is removed is shown in FIG. 3A.
여기서 중요한 것은 잔여 폴리실리콘층(14)의 두께인데, 이 두께는 자기정렬 식각공정에서 발생하는 산화막 손실을 고려하여 최적화하여야 한다. 제3B도는 상기 제 3A도의 상태하에서 폴리 산화공정을 실시하여 상기 잔여 폴리실리콘층(14)을 산화시켜 산화막(14A)을 형성한 상태를 도시한 것으로, 상기 폴리 산화공정은 습식 산화방식으로 800∼900℃의 낮은 온도에서 실시한다. 이 산화조건에서는 불순물이 주입된 잔여 폴리실리콘층(14)의 산화속도가 매우 빨라 10분 이내에 모두 완전히 산화되며, 이 산화막(14A)의 두께는 잔여 폴리실리콘층(14)의 두께보다 약 2배정도가 되어 후속공정인 자기정렬 식각공정시 기판 손상을 방지하게 된다. 동시에 최초 감광막으로 가려진 부분의 제 1 폴리실리콘층(제 1도의D부분)상의 질화막도 일부 산화되어 ONO 구조의 층간 절연막이 완성된다. 이후 컨트롤 게이트용 제 2 폴리실리콘층을 증착하고, 제 2 폴리 마스크 및 식각공정과 자기정렬 식각공정을 진행하여 제 1 및 2 폴리실리콘층으로 된 적층 게이트(플로팅 게이트 및 컨트롤 게이트)를 형성한 상태에서 X - X'선을 절단한 단면도를 제 3c도에 도시하고 있다. 제 3c도에서는 자기정렬 식각공정시 제 1 폴리실리콘층이 존재하지 않는 부위의 산화막(14A)이 손실되어 얇은 잔여 산화막(14B)이 남게된다.What is important here is the thickness of the remaining polysilicon layer 14, which should be optimized in consideration of oxide loss in the self-aligned etching process. FIG. 3B shows a state in which an oxide film 14A is formed by oxidizing the remaining polysilicon layer 14 by performing a poly oxidation process under the state of FIG. 3A. The poly oxidation process is a wet oxidation method 800 to 800. FIG. It is carried out at a low temperature of 900 ° C. Under these oxidation conditions, the oxidation rate of the remaining polysilicon layer 14 into which impurities are injected is very fast, and all of them are completely oxidized within 10 minutes, and the thickness of the oxide film 14A is about twice the thickness of the remaining polysilicon layer 14. This prevents substrate damage during the subsequent self-aligned etching process. At the same time, the nitride film on the first polysilicon layer (part D in FIG. 1) of the portion covered by the first photosensitive film is also partially oxidized to complete the interlayer insulating film of the ONO structure. After that, a second polysilicon layer for control gates is deposited, and a second poly mask, an etching process, and a self-aligning etching process are performed to form stacked gates (floating gates and control gates) of the first and second polysilicon layers. Is a cross-sectional view taken along line X-X 'in FIG. 3C. In FIG. 3C, the oxide film 14A at the portion where the first polysilicon layer does not exist during the self-alignment etching process is lost, leaving a thin residual oxide film 14B.
상기 상태하에서 불순물 주입으로 소오스 및 드레인을 형성하고, 콘택부를 형성하며, 금속배선 공정을 실시하여 본 발명의 비휘발성 메모리셀을 제조한다.Under the above conditions, a source and a drain are formed by impurity implantation, a contact portion is formed, and a metal wiring process is performed to manufacture the nonvolatile memory cell of the present invention.
한편, 잔여 폴리실리콘층(14)에 불순물 주입공정시 RP를 기판내에 두어 기판에 불순물이 주입되도록 하고, 이후이 폴리산화공정을 약간 늘림으로써, 후공정의 소오스 및 드레인 형성을 위한 불순물 주임공정시 그 부위에 불순물이 주입되지 않더라도 소오스 디퓨젼 라인이 형성되도록 할 수 있다. 이 방법은 잔여 폴리실리콘층의 산화에 의해 얻어지는 산화막(14A)두께가 상대적으로 얇은 점은 있으나, 자기정렬 식각공정시 이 부위의 잔여 산화막(14B) 두께를 최적화시킬 필요가 없다는 장점이 있다. 상술한 바에 의거한 본 발명은 셀 면적의 증가를 수반하지 않고, 기존의 문제점인 기판 손상을 방지할 수 있어 소자의 수율 및 신뢰성을 향상시킬 수 있다.On the other hand, in the impurity implantation process to the remaining polysilicon layer 14, RP is placed in the substrate so that the impurity is implanted into the substrate, and then the polyoxidation process is slightly increased, so that the impurity chimney process for forming the source and drain of the subsequent process is performed. The source diffusion line may be formed even when no impurities are injected into the site. This method has a relatively thin thickness of the oxide film 14A obtained by the oxidation of the remaining polysilicon layer, but has the advantage that it is not necessary to optimize the thickness of the remaining oxide film 14B at this site during the self-aligned etching process. The present invention based on the above can avoid damage to the substrate, which is an existing problem, without involving an increase in the cell area, thereby improving the yield and reliability of the device.
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