JPH03166626A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the processing of an information processor from being stopped even if abnormality is generated in a part of an instruction buffer by bringing the instruction buffer in which abnormality is generated to degeneracy, in the case abnormality is generated in a part of plural instruction buffers, and continuing the processing by using the instruction buffer in which no abnormality is generated. CONSTITUTION:In the case abnormality is generated in a first instruction buffer 1, this instruction buffer 1 is brought to degeneracy, and by the degeneracy operation, a first instruction buffer degeneracy bit BR1 is set, effective bits B3, B4 corresponding to a second instruction buffer 2 are reset, and a pointer in an instruction selecting circuit 7 is set to an instruction C3. Since a second instruction buffer 2 becomes empty, an instruction fetch request is outputted from an instruction fetch control circuit 13. A storage circuit 18 which receives the request makes an instruction data effective signal 19 significant and outputs instruction data. By this instruction data, a second instruction buffer empty detecting circuit 12 becomes significant. In such a way, even if abnormality is generated in a first instruction buffer 1, the processing is continued by using a second instruction buffer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improving the reliability of an information processing device having a plurality of instruction buffers.

[Prior Art] FIG. 2 is a diagram showing an instruction reading section of a conventional information processing device. In the figure, (1) and (2) are two instructions CI,
A first instruction buffer and a second instruction buffer that can store C2, C3, and C4, (3) an instruction data selection circuit for selecting an instruction to be decoded from the instructions stored in the instruction buffer, and (4) each A valid bit generator that generates a valid bit BINB4 indicating that the instructions C1 to C4 are valid; (5) a valid bit selection circuit for selecting a valid bit corresponding to the instruction to be decoded from the valid bits;
(6) is an instruction decode circuit for decoding the valid instruction selected by the instruction data selection circuit (3) and the valid bit selection circuit (5); (a) is the instruction decode circuit (
6) is an instruction selection circuit for receiving a completion signal and selecting the next instruction; (10) is a completed instruction invalidation circuit for receiving the output of the instruction selection circuit (7) and resetting the valid bit of the instruction that has been decoded. (11) and (l2) are first and second instruction buffer empty detection circuits (11) and (12) for detecting that the first and second instruction buffers (1) and (2) are empty, respectively. 13) is an instruction fetch control circuit, and (14) is when both the first and second instruction buffers (1) and (2) are emptied, and the instruction data is transferred to the first instruction buffer (1) by the next instruction fetch. A pointer reset circuit (15) detects that the second instruction buffer (2) is empty and sets the pointer of the instruction selection circuit (7) to the instruction CI. a second instruction buffer selection circuit (16) and (17) for storing instruction data in the second instruction buffer (2) only when the instruction buffer (1) is not empty;
) are first and second instruction buffer storage control circuits (l8) for storing instruction data in the first instruction buffer (1) and second instruction buffer (2) and setting corresponding valid bits, respectively; ) is a storage device, (l9) is a storage device (18)
(20) is an instruction data bus for sending instruction data; (2l) is a first instruction buffer (1) or a second instruction buffer (2); ) is an abnormality reporting circuit that reports the abnormality when it occurs.

Next, the operation will be explained. First and second instruction buffers (1). (2) is empty, both the first and second instruction buffer empty detection circuits (l1) and (12) become significant, and the instruction fetch control circuit (13) to the storage device (l1) becomes significant.
A command fetch request is issued to 8).

The storage device (18) that received the request makes the instruction data valid signal (I9) significant and outputs the instruction data to the instruction data path (2Q). Since both the first and second instruction buffer empty detection circuits (11) and (12) have become significant, the second instruction buffer selection circuit (15)
Only the instruction buffer storage control circuit (16) becomes significant,
The instruction data is stored in the first instruction buffer (1) and valid bits 81 and 82 are set.

The instruction C1 stored in the first instruction buffer 1(l) is selected by the instruction data selection circuit (3) and sent to the instruction decoding circuit (6). Further, the valid bit B1 corresponding to instruction 01 is also selected by the valid bit selection circuit (5) and sent to the instruction decode (6). Instruction decoding circuit (
The instruction C1 sent to step 6) is confirmed to be valid by the valid bit B1 and is decoded.

When the decoding is completed, a decoding completion signal is sent from the instruction decoding circuit (6) to the instruction selection circuit (7), which selects the next instruction, instruction C2. The completed instruction invalidation circuit (10) which received the signal selecting the instruction C2 detects that the decoding of the instruction CI is completed and resets the valid bit 8l. The instruction data selection circuit (3) and valid bit selection circuit (5) that have received the signal for selecting the instruction C2 send the instruction C2 and the valid bit Bl to the instruction decoding circuit (6).

When instruction data is stored in the first instruction buffer (1) and valid bits Bl and B2 are set, the second instruction buffer (2) is empty and valid bits B3 and B4 are not set. Second instruction buffer empty detection circuit (
12) becomes significant, and an instruction fetch request is issued from the instruction fetch control circuit (13) to the storage device (18).

The storage device (18) that received the request makes the instruction data valid signal (19) significant and outputs the instruction data to the instruction data bus (20). Since the second instruction buffer empty detection circuit (l2) has become significant, the second instruction buffer selection circuit (15) has become significant, and the second instruction buffer storage control circuit (step 7) has become significant. The instruction data is stored in the second instruction buffer (2) and valid bits 83, 84 are set.

Instruction C2 sent to the instruction decode circuit (6) is decoded, and a decode completion signal is sent to the instruction selection circuit (7). The instruction selection circuit (7) outputs a signal for selecting the next instruction, instruction C3. The completed instruction invalidation circuit (10) that receives the signal selecting the instruction C3 resets the valid bit B2. The instruction data selection circuit (3) and valid bit selection circuit (5) that received the signal to select instruction C3 select instruction 03.
and valid bit B3 are sent to the instruction decode circuit (6).

When the decoding of the instruction C2 is completed and the valid bit B2 is reset, the first instruction buffer empty detection circuit (11) becomes significant, an instruction fetch request is output from the instruction fetch control circuit (l3), and the storage device Command data is sent from (l8), stored in the first command buffer (1), and corresponding valid bits B1 and B2 are set.

Thereafter, by repeating the same operation, Cl-C2-C3
−C4 → Cl are sequentially decoded. however,
When the decoding of instruction 02 is completed, the second instruction buffer empty detection circuit (12) becomes significant, and the instruction data generated by the instruction fetch is transferred to the second instruction buffer 7.
7 (.2), both the first and second instruction empty detection circuits (l1) and (l2) become significant, so the pointer reset circuit (l4) becomes significant and the instruction is selected. In the circuit (7), the instruction C1 is selected. Also, at this time, only the first instruction buffer 7 storage control circuit (16) becomes significant by the second instruction buffer selection circuit (15), and the instruction data is stored in the first instruction buffer (1). , valid bit Bl, 82 is set.

If an abnormality is detected in the first or second instruction buffer during the above operation, the abnormality reporting circuit (2l)
An abnormality is reported, and the information processing device stops processing due to the abnormality in the instruction reading section.

[Problem to be solved by the invention]

Since conventional information processing devices are configured as described above, the problem is that if an abnormality occurs in one of the plurality of instruction buses held within the device, instruction processing must be stopped. was there.

This invention was made to solve the above-mentioned problems. Even if an error occurs in one instruction buffer among multiple instruction buffers, only the instruction buffer in which the error has occurred can be degraded, and the error can be removed. It is an object of the present invention to provide an information processing device that can continue processing instructions using an instruction buffer other than the instruction buffer in which the error occurred.

[Means to solve the problem]

An information processing device according to the present invention is an information processing device having a plurality of instruction buffers for storing instruction data sent from a storage device, in which an abnormality is detected for each instruction buffer 7, and when an abnormality occurs, an abnormality is detected. The apparatus is equipped with a control means for degenerating the instruction buffer in which the abnormality has occurred and continuing processing using an instruction buffer other than the instruction buffer in which the abnormality has occurred.

[Effect]

The information processing device according to the present invention uses the control means to detect an instruction buffer in which an abnormality has occurred, identify the instruction buffer in which an abnormality has occurred, degenerate the instruction buffer in which an abnormality has occurred, and degenerate the instruction buffer in which an abnormality has occurred. Processing continues using a different instruction buffer.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1, in which the same parts as in FIG. 2 are denoted by the same reference numerals. In FIG. 1, (22) are first and second instruction buffer degeneration bits 8Rl for holding information when an abnormality is detected in the first and second instruction buffers (1) and (2), respectively. and BR2
The degenerate bit generator (23) is a degenerate selection circuit for fixing the instruction buffer selection portion of the output of the instruction selection circuit (7) to a non-degenerate instruction buffer so as not to use the degenerate instruction buffer. , the completed instruction invalidation circuit (10) is connected to the instruction selection circuit (7) and degeneration control circuit (23).
) and resets the valid bit of the decoded instruction.

Furthermore, (24) and (25) are the first and second instruction buffer empty detection circuits (11) and (12) when the first and second instruction buffers (1) and (2) are degenerated, respectively. )
The instruction buffer storage selection circuit (l5) receiving the output of the first and second instruction buffer degeneration circuits for invalidating the output of the instruction buffer (2) is empty and not degenerated,
Instruction data is stored in the instruction buffer (2) when the instruction buffer (1) is not empty or when the instruction buffer (1) is degenerated. Furthermore, (2
6) is an abnormality reporting circuit for reporting an abnormality when an abnormality occurs in both instruction buffers (1) and (2).

Next, the operation will be explained.

The operation when both the first and second instruction buffers (1) and (2) are operating without any abnormality is as follows: When the first and second instruction buffers (1) and (2) are empty, Both the first and second instruction buffer empty detection circuits (l1) and (12) become significant, and the instruction fetch control circuit (13) to the storage device (
An instruction fetch request is issued to 18). The storage device (18) that received the request makes the instruction data valid signal (19) significant and outputs the instruction data to the instruction data path (20). Since both the first and second instruction buffer empty detection circuits (1l) and (l2) are significant, the second
Only the first instruction buffer 1 storage control circuit (16) becomes significant by the instruction buffer selection circuit (l5) of , the instruction data is stored in the first instruction buffer (1), and valid bits B1 and B2 are set. , the instruction c1 stored in the instruction buffer (1) is selected by the instruction data selection circuit (3) and sent to the instruction decoding circuit (6). Further, the valid bit B1 corresponding to the instruction CI is also selected by the valid bit selection circuit (5) and sent to the instruction decoding circuit (6). The instruction C1 sent to the instruction decode circuit (6) is confirmed to be valid by the valid bit B1 and is decoded.

When the decoding is completed, a decoding completion signal is sent from the instruction decoding circuit (6) to the instruction selection circuit (7), which selects the next instruction, instruction 02. The completed instruction invalidating circuit (10) which receives the signal selecting the instruction C2 detects that the decoding of the instruction C1 is completed and resets the valid bit B1. The instruction data selection circuit (3) and valid bit selection circuit (5), which have received the signal for selecting the instruction C2, send the instruction 02 and the valid bit B2 to the instruction decoding circuit (6).

Furthermore, when the instruction data is stored in the first instruction buffer (1) and the valid bit B1 and 62 are set, the second
The instruction buffer (2) is empty and the valid bits B3 and B4 are not set, so the second instruction buffer empty detection circuit (l2) becomes significant and the instruction fetch control circuit (13) becomes significant.
), an instruction fetch request is issued to the storage device (l8). The storage device (18) that received the request makes the command data valid signal significant and outputs the command data to the command data path (20). Second instruction buffer empty detection circuit (1
Since only 2) has become significant, the second instruction buffer selection circuit (l5) has become significant, the second instruction buffer storage control circuit (17) has become significant, and the instruction data is stored in the second instruction buffer ( 2), and valid bits B3 and B4 are set.

Instruction 02 sent to the instruction decode circuit (6) is decoded, and a decode completion signal is sent to the instruction selection circuit (7). The instruction selection circuit (7) outputs a signal for selecting the next instruction, instruction C3. Upon receiving the signal selecting instruction 03, the completed instruction invalidation circuit (10) resets the valid bit B2. The instruction data selection circuit (3) and valid bit selection circuit (5) which received the signal to select the instruction C3 select the instruction C3.
3 and valid bit B3 to the instruction decode circuit (6).

When decoding of instruction C2 is completed and valid bit B2 is reset, the first instruction buffer empty detection circuit (11) becomes significant, an instruction fetch request is output from the instruction fetch control circuit (13), and the storage device Command data is sent from (18), stored in the first command buffer <1), and corresponding valid bits B1 and B2 are set.

Thereafter, by repeating the same operation, instructions C1→C2→
The signals are decoded in the order of C3→C4→C1.

However, when the decoding of instruction C2 is completed, the second instruction buffer empty detection circuit (12) becomes significant, and the instruction data generated by the instruction fetch is not stored in the second instruction buffer (2). In this case, both the first and second instruction buffer empty detection circuits (11) and (12) become significant, so the pointer reset circuit (14) becomes significant, and the instruction selection circuit (7) selects the instruction C1. do. Also, at this time, only the first instruction buffer storage IJ control circuit (l6) becomes significant by the second instruction buffer selection circuit (l5), the instruction data is stored in the instruction buffer C1, and valid bits Bl and B2 are set. be done.

During the above operation, the first instruction buffer (1)
If an abnormality occurs in the instruction buffer (1), this instruction buffer (1) is degraded. Due to the degeneracy operation, the first instruction buffer degeneration bit BRI is set, the valid bits B3 and B4 corresponding to the second instruction buffer (2) are reset, and the pointer in the instruction selection circuit (7) is set to the instruction C3. be done. Second
Since the instruction buffer (2) becomes empty, an instruction fetch request is issued from the instruction fetch control circuit (13). Upon receiving the request, the storage device (18) makes the instruction data valid signal (19) significant and outputs the instruction data. At this time, even if valid bits B1 and B2 are in the reset state and the first instruction buffer empty detection circuit (11) is significant, the first instruction buffer degeneration circuit (24) invalidates the valid bits. The operation is the same as when the instruction buffer 1 (1) is not empty. Therefore, the instruction data output from the storage device (18) is stored in the second instruction buffer (2), and valid bits B3 and B4 are set.

The instructions stored in the second instruction buffer (2) are first
Instruction C3 is selected by the instruction selection circuit (7) and the instruction
The signal is sent to the code circuit (6) and decoded. Command C3
When decoding is completed, a decoding completion signal is sent from the instruction decoding circuit (6) to the instruction selection circuit (7), instruction C4 is selected, and valid bit B3 is reset.

When the decoding of instruction C4 is completed in the same manner, the output of the instruction selection circuit (7) indicates instruction CI, but the degeneration control circuit (23) changes the instruction buffer selection portion of the output of the instruction selection circuit (7) to the second Since it is fixed to the instruction buffer (2), the instruction data selection circuit (3) that receives the output
Valid bit selection circuit (5) and completed instruction invalidation circuit (l
O) receives a signal indicating instruction C3.

When the decoding of the instruction C4 is completed and the instruction C3 is selected, the completed instruction invalidation circuit (10) resets the valid bit B4. This causes the second instruction buffer empty detection circuit (
12) becomes significant, the instruction fetch control circuit (l3
), an instruction fetch request is output from the storage device (
18) and outputs the command data. The output instruction data is transferred to the second instruction buffer (2) in the same manner as above.
is stored in

In this way, even if an abnormality occurs in the first instruction buffer (1), it is possible to continue processing using the second instruction buffer (2). Also, the second instruction buffer (2
), it is possible to continue processing using only the first instruction buffer (1) in a similar manner.

Note that in the above embodiment, there are two instruction buffers, but
Any number may be used as long as there is a plurality of instructions, and although the number of instructions entering the instruction buffer is set to two, it goes without saying that the number may be any number depending on the number of instructions read out by instruction fetch and the structure of the buffer. Furthermore, although the unit of instruction buffer degeneration is each instruction buffer, a plurality of instruction buffers may be divided into a plurality of groups, and a plurality of instruction buffers may be degenerated all at once.

(Effects of the Invention) As described above, according to the present invention, when an error occurs in some of a plurality of instruction buffers, the instruction buffer in which the error occurs is degraded, and the instruction buffer in which the error does not occur is used. Since it is possible to continue the processing by the instruction buffer, it is possible to obtain a highly reliable information processing device in which the processing of the information processing device does not stop even if an abnormality occurs in a part of the instruction buffer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an instruction reading section of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing an instruction reading section of a conventional information processing apparatus. (1) and (2) are instruction buffers, (3) are instruction data selection circuits, (4) are valid bit generators, (5) are valid bit selection circuits, (6) are instruction decoding circuits, and (7) are An instruction selection circuit (10) is a completed instruction invalidation circuit (11)
), (12) is the instruction puffer empty detection circuit, (13)
is an instruction fetch control circuit, (l4) is a pointer reset circuit, (15) is an instruction buffer selection circuit, (16),
(17) is an instruction storage control circuit, (18) is a storage circuit,
(19) is an instruction data valid signal, (20) is an instruction data bus, (22) is a degeneration bit generator, (23) is a degeneration control circuit, (24) and (25) are instruction buffer degeneration circuits,
(26) is an abnormality reporting circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] In an information processing device that has multiple instruction buffers that store instruction data sent from a storage device, an abnormality is detected for each instruction buffer, and when an abnormality occurs, the instruction buffer in which the abnormality has occurred is degraded and the abnormality is detected. 1. An information processing apparatus comprising: a control means for continuing processing using an instruction buffer other than the instruction buffer that has been used.