JP2979962B2 - Failure detection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detecting system in a digital communication interface device.

[0002]

2. Description of the Related Art An error detection technique for digital block data is disclosed in Japanese Patent Application Laid-Open No. 58-168346. In the technique described in this publication, both the vertical and horizontal parities of one block are added, and codes for error detection and correction are added to data at corresponding positions in a plurality of blocks. Accordingly, even if the data of the corresponding position of the plurality of blocks is determined that all the error, an error occurs in one word if you look for each block, and fewer if the error correction becomes impossible.

[0003]

[0004]

[0005]

[0006]

[0007]

[0008]

[0009]

[0010]

[0011]

[0012]

[0013]

[0014] In the prior art, as if the error detection by the error check code is performed, and if the actual destruction of data occurs, is considered a case of failure of the error checking circuit itself. In the above prior art,
Vertical parity and horizontal parity are used as error check codes .

[0015]

However, the prior art
Or in the technique causes of errors in data corruption, it is difficult to determine due to the failure other than the data destruction.

When an error due to horizontal parity or the like is detected, a method for checking whether the cause is data destruction or another factor is to compare the data in which the error was detected with the original data. Is simple and reliable. However, in the case of an interface device connected to a data transmission path, the above-described means cannot be used due to the fact that the original data does not already exist, or even if it exists, there is a physical distance. is there. Further, since data in which an error is detected is usually discarded, it is impossible to verify the data, and it has been difficult to specify the cause of the error.

An object of the present invention is to provide a failure detection system capable of easily determining the cause of a horizontal parity error in an interface device.

Another object of the present invention is to provide a failure detection system which can classify a failure of the horizontal parity generation circuit itself or a failure of the horizontal parity error check circuit itself as a cause of the failure.

Another object of the present invention is to provide a fault detection system which can perform data input and data output to an interface device in parallel.

Another object of the present invention is to provide a failure detection system capable of continuously receiving data when valid data transfer requests are continuously supplied to an interface device.

Another object of the present invention is to provide a failure detection system which prevents overwriting of error data stored in a buffer and prevents transmission of error data during normal operation.

[0022]

According to a first system of the present invention, a buffer memory means for storing data including an error check code for a plurality of externally provided words, and a buffer memory means for storing data to be stored in the buffer memory means. A horizontal parity error detecting means for detecting an error with the error check code, and a storage suppressing means (hereinafter referred to as a buffer) for suppressing storage of new data in the buffer memory means when a data error is detected by the horizontal parity error detecting means. Access controller).

According to a second system of the present invention, in the first system, when the horizontal parity error detecting means detects a data error, the buffer access controller suppresses all data storage in the buffer memory means. It is characterized by the following.

According to a third system of the present invention, in the first system, when the horizontal parity error detecting means detects a data error, an error flag is set in the means for controlling an error data storage area of the buffer memory means. Thus, the storage suppression unit suppresses writing of new data only in the corresponding storage area where the error flag is set.

According to a fourth system of the present invention, in the fifth system, the writing of new data to only the corresponding storage area in which the error flag is set is suppressed, and the error data is read from the storage area at normal time. It is characterized in that it is prevented from being issued.

A fifth system according to the present invention comprises a plurality of the buffer memory means in the first system, wherein one buffer memory means stores external data and the other buffer memory means stores the data. The operation of outputting data to the outside is performed in parallel.

A sixth system according to the present invention, in the first system, comprises a plurality of said buffer memory means, and stores continuous data sent together with a continuous data transfer request from outside in said plurality of buffer memory means. It is characterized by receiving by switching the destination.

[0028]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention inputs data supplied through an input- side data transfer path 20 to an input register 1. The input- side data transfer request signal provided via the line 41 is a signal that is valid from the start of transfer of a data block (hereinafter, referred to as a burst) corresponding to one horizontal parity to the end of transfer.

In this embodiment, one burst has a maximum of 256
No more than one word, and one word is composed of four bytes.
A buffer for storing one burst uses a space of 1 kilobyte regardless of the size of the burst. Also,
The memory constituting the buffer has a space of 4112 bytes per system and can store four sets of bursts and associated error check codes. Therefore, the start address of burst read / write is 4
It is limited only to the type and can be decoded from a 2-bit address register.

Referring to FIGS. 1 and 2, when an input-side data transfer request signal provided via a line 41 becomes valid, data provided via an input- side data transfer path 20 is transferred as shown in FIG. The data is stored in the input register 1 in synchronization with the synchronization clock.

In one embodiment of the present invention, there is provided a pair of buffer memories 3 and 4 for storing data including an error check code for verifying the consistency of data consisting of a plurality of words.

In response to an input-side data transfer request signal applied in synchronization with data input to the input register 1, the buffer switching controller 9
Select the buffer memories 3 and 4 for temporary storage of data given via Selected buffer memory 3
In response , buffer switching controller 9 transmits a write buffer designation signal to buffer access controller 8 via write buffer designation line 51. The buffer access controller 8 designates the buffer memory 3 via the line 46 as a data write buffer memory for storing data in the designated buffer memory 3. In addition,
Buffer access controller 8 communicates the data writing for the start address and the address generation start timing to the buffer memory 3 to the memory write address generator 10 via line 61.

Referring to FIGS. 1 and 2, data is first stored in input register 1 via line 20. In response to the request dropping of the input data transfer request signal supplied via the line 41 in synchronization with the supply of the data, the data supplied via the line 20 in response to the withdrawal of the request from the input side is transferred to the data verification horizontal parity bit group. Before this switching, the data stored in the input register 1 is supplied to a horizontal parity generation circuit including an exclusive OR circuit 5 and a register 6, and the horizontal parity generation circuit generates a horizontal parity.

The line 41 terminates the data transfer by the withdrawal of the input side transfer request signal et is supplied through is detected. In response to this detection, the horizontal parity error check circuit 7
Checks the presence or absence of the error.

The feature of one embodiment of the present invention resides in the operation when the horizontal parity error detection circuit 7 detects an error.

That is, the horizontal parity error detection circuit 7
When an error is detected, an error detection notification signal is output to the buffer access controller 8, the buffer switching controller 9 and the outside of the device via the line 50.

In response to the error detection notification signal, the buffer access controller 8 and the buffer switching controller 9 suppress the data input to the buffer memory, and store one burst of data in which an error is detected and the horizontal parity corresponding to the data. Is to ensure.

The buffer access controller 8 which plays an important role in the first and second embodiments of the present invention described below will be described in detail with reference to FIGS.

Referring to FIG. 3, buffer access controller 8 has register groups 31, 32, 33 and 34 for controlling a first-system memory and register groups 73 and 74 for controlling a second-system memory. , 75 and 76 are provided. One of the register groups holds data for controlling one memory space.

The detailed contents of each register will be described in detail with reference to FIG. 81 is part of a flip-flop or register for storing a flag indicating that the data stored is the error data (hereinafter referred to as "flag 81".). A register 82 indicates whether or not the written data has been read. 83 is part of a flip-flop or register for storing a flag indicating whether data written is continuous with data stored in the previous block of memory of the same type (hereinafter "flag 83 " ).

It is now assumed that a memory of a system controlled by the contents of the register groups 31-34 has been designated as a memory to be written.

In response to the end of one burst transfer, the register controller 71 supplies a register selection signal to the cyclic counter 38 via the line 133. In response to this signal, the content of the cyclic counter 38 is incremented and the control register is shifted. Immediately after the shift, the register controller 71 has already read the data in the buffer area controlled by the contents of the control register, and the data can be overwritten on the buffer area.
Be sure. As long as the write side memory switching is not notified by the buffer switch controller 9 shown in FIG. 1, a line 41 shown in FIG. 1, that is, the input-side data transfer request signal via line 118 shown in FIG. 3 provided , the register controller 71 sent the start address from the currently selected register. At the same time, the register controller 71, and instructs the count start the word counter 72, line 41, i.e. in response to withdrawal of the data transfer request signal provided via line 118 waits for stopping the data flows. The data length counted by the word counter 72 in response to the withdrawal of the data transfer request signal is stored in the data length holding area of the currently selected register via the data length transmission line 104. If the saved data does not cause an error,
The register controller 71 sets "0" to the read flag 82 shown in FIG. 4, and prohibits data overwriting in this area. When data is continuously written to one memory as in this example, "1" is set in the data chain flag 83 shown in FIG. Indicates the existence of data.

[0044] When reading the data, waits for the buffer value given through the write side buffer specified line 119 is controlled by the contents of the switching instead register 3 1- 3 4 that switched to the read side, rhinoceros The contents of the click counter 38 are incremented, and a register in which the read flag 82 becomes "0" for the first time is searched. If such a register exists, the buffer address and the number of data words are notified from the address register and the data length register to the read address generation circuit 11, and after data transmission, the read flag 82 is set to "1", and the data chain flag 83 Is set to "0", the content of the counter 38 is incremented. After the increment of the counter 38, if the data chain flag 83 is "1" in the selected register, the data corresponding to this register is subsequently transmitted. An error flag is transmitted on lines 110 and 113, a read flag is transmitted on lines 111 and 114, and a data chain flag is transmitted on lines 112 and 115. Lines 111 and 114 shown in FIG. 3 correspond to line 5 shown in FIG.
Lines 112 and 115 shown in FIG. 3 correspond to lines 55 and 56 shown in FIG. These lines 53-56 are connected to the buffer switching controller 9 shown in FIG. 1, and the read flag 82 and the data chain flag 83 from the buffer access controller 8 are transmitted to the buffer switching controller 9.

The buffer switching controller 9 shown in FIG. 1 determines the buffer switching timing in response to the presence / absence of read data, the state of the data chain flag 83, and the input side data transfer request signal given via the line 41. I do.

Also in the first embodiment of the present invention and the second embodiment to be described below, when data is written into the buffer and then the presence of an error is notified by the error detection circuit 7 as shown in FIG. Register controller 71
“1” is set in the error flag 81 shown in FIG. 4 in the register for controlling the buffer area holding the data.

Referring to FIG. 3, the signal provided on line 118 is an input data transfer request signal provided via line 41 shown in FIG. Line 121 shown in FIG.
Is an output-side data transfer request signal provided via the line 45 shown in FIG. The signal provided on line 122 shown in FIG. 3 is the line 4 shown in FIG.
7, an error data transfer request signal is provided.

Referring to FIGS. 1 and 3, during normal operation, the buffer access controller responds to an input data transfer request signal provided via line 118 and an output data transfer request signal provided via line 121. 8
Checks the error flag 81 shown in FIG. By this check, the buffer access controller 8
It is possible to skip checking the register that controls the error data storage buffer area, prevent overwriting of error data, and prevent transmission of error data during normal operation.

The error data protected by such a method is output in response to an error data transfer request signal 122 provided via a line 122. In response to the error data transfer request signal provided via line 122, register controller 71 increments counters 38 and 70 to provide registers 31-34,7.
The register in which the error flag shown in FIG. 4 is set is scanned from 3-76. By detecting the register in which the error flag is set to "1", the buffer access controller 8 calls the storage location and data length of the data in which the error is detected, and can output the error data. In response to the end of the output of the error data, the buffer access controller 8 resets the error flag of the register for controlling the buffer storing the output error data from “1” to “0” and reads the read flag 82. To end. With these actions,
During the subsequent normal operation, the buffer storing the error data becomes available.

Under the control of the buffer access controller 8, the first embodiment of the present invention operates as follows.

Referring to FIG. 1, the output of the data in which an error is detected and the horizontal parity corresponding to this data are performed by receiving an error information transfer request signal provided via line 47. In response to the error information transfer request signal, the buffer access controller 8 specifies the buffer storing the error data and the address in the buffer, and issues an instruction to read the error data from the buffer memory to the memory read address generation circuit 11.
Notify. At the same time, the buffer access controller 8 switches the input of the selector 12 to the data transfer line 24 side, and outputs the detected data and the corresponding horizontal parity to the error information collection transfer line 29 via the output register 13. After outputting the data and the horizontal parity, the input of the selector 12 is switched to the transfer line 27 side, and the horizontal parity generated in the device is output to the error information collecting transfer line 29.

In the first embodiment of the present invention, there is shown a technique for suppressing all writing to the buffer memory in order to secure data in which an error is detected. In this technique, the apparatus shown in FIG. All functions as an interface will be stopped.

On the other hand, the feature of the second embodiment of the present invention is that, assuming that the apparatus logically has a plurality of buffers 3 and 4 like the apparatus shown in FIG. Without prohibiting writing to all buffer memories,
The object of the present invention is to suppress the writing of new data only in a buffer containing data in which an error is detected and the corresponding horizontal parity, and to use a buffer memory containing no error data. With this technique, the function as the interface device can be maintained. Further, in the second embodiment of the present invention, when an error is detected, the register 14 holds the horizontal parity generated in the device until the horizontal parity is read in response to the error information transfer request, and the buffer access controller 8 Has the following effects by controlling to store the storage area of the data in which the error is detected. That is, it is also possible to secure only an area in which the error-detected data and the corresponding error check code of the data are stored, and to write data in the same buffer memory other than the area.
In one embodiment of the present invention, a horizontal parity is separately generated based on the secured error detection data, and the input side data transfer path 2 is generated.
Compare the horizontal parity obtained through 0 with the horizontal parity generated by the horizontal parity generation circuits 5 and 6. According to these operations, the embodiment of the present invention can classify the error into three cases, that is, the case due to data destruction, the case due to the failure of the horizontal parity generation circuit, and the case due to the failure of the horizontal parity error check circuit.

Referring to FIG. 1, when the end of data transfer is detected in response to the withdrawal of the input transfer request signal applied via line 41, horizontal parity error check circuit 7 checks for an error. .

The operation when no error is detected will be described below.

If no error is detected, the input data is stored as output-capable data, and the stored data is stored in line 24, in response to a valid output data transfer request signal provided via line 45. Output to the outside via the output register 2 and the line 25. If it is determined that there is no error, the buffer access controller 8 returns to line 4
A register reset signal is applied to registers 6 and 14 via 2 and 43 to reset the contents of registers and 14 and prepare for the next burst input. The horizontal parity corresponding to one burst of data and the burst input to the buffer memory 3 or 4 by the above operation is supplied with a valid output-side data transfer request signal via the line 45, and the data and the horizontal parity are changed. Guaranteed until output. However, after the data and the horizontal parity are output once, the buffer area storing the data and the horizontal parity is used for storing newly input data.

In the device shown in FIG. 1, the memory read address generation circuit 11 and the write address generation circuit 10
Even if data is being input from the input side, if the data to be output is in a memory different from the buffer memory where the input data is to be stored, the data is output simultaneously with the input operation. Operation is possible.

When a valid input-side data transfer request signal is continuously supplied via the line 41, the buffer switching controller 9 searches for an available buffer memory area and performs switching. Reception is possible.

[0059]

The present invention has the effect that the cause of the horizontal parity error in the interface device can be easily determined. The present invention has an effect that a failure of the horizontal parity generation circuit and the horizontal parity error check circuit itself can be found. The present invention has the further advantage that data input and data output can be performed in parallel to the interface device. According to the present invention, overwriting of error data stored in the buffer can be prevented, and transmission of error data during normal operation can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of one embodiment of the present invention.

FIG. 3 is a buffer access controller 8 in FIG. 1;
FIG. 3 is a diagram showing a detailed configuration of the embodiment.

FIG. 4 shows registers 31-34 and 73- in FIG.
FIG. 76 is a diagram for describing the contents of 76.

[Explanation of symbols]

Reference Signs List 1 input register 2 output register 3, 4 buffer memory 5 exclusive OR 6 register 7 horizontal parity error detection circuit 8 buffer access controller 9 buffer memory switching controller 10 memory write address generation circuit 11 memory read address generation circuit 12 selector 13 output register 14, 31, 32, 33, 34, 73, 74, 75, 7
6 register 35, 36 selector 37, 39 decoder 38, 70 counter 71 register controller 72 word counter

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 13/08 H04L 13/08

Claims (1)

(57) [Claims] 1. A buffer memory means for storing a plurality of areas including a data block provided from a data transfer path and an error check code associated with the data block, and an error occurrence in each of the areas of the buffer memory means. and the error flag to be displayed, the error detection means for the errors in the data block to display the occurrence of an error in the error flag corresponding to detected by the error check code, before in a region in which a plurality stored in said buffer memory means
And a storage inhibiting means for inhibiting writing to the buffer memory means only in an area where the occurrence of the error flag is indicated .