JPS6180427A - Information processor - Google Patents

Abstract

PURPOSE:To attain a continuous operation of a system by converting the address of an uncorrectable error if detected in a control memory mode and therefore reading automatically a microprogram out of a main memory. CONSTITUTION:When an error is reported from a check circuit 3 of a control memory circuit 4, the input fetched by a microprogram word register 6 from a control memory 1 via a switch means 5 is suppressed. Then an executing circuit 2 stops the execution of the relevant program. The address of a microprogram address register 7 is converted into an address of a main memory 12 by a shift circuit 8. Then a new microprogram having the same contents is extracted out of the memory 12 with the address of the memory 12 and by a request given from the circuit 4 and then set to the register 6 whose suppression is released by the circuit 4. Thus the circuit 2 restarts an operation with the normal microprogram control and according to a new program.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control device in an information processing device.

(Prior Art) Conventionally, in a microprogram-controlled information processing device, detection and processing of a control memory failure has been performed as follows. In other words, some devices add parity pits to the control memory and check whether the number of bits whose logical value is %11 in the data read from the control memory is an odd number, round, or even. In information processing apparatuses that are required to detect errors and have high reliability, Hamming codes, which have the functions of correcting 1-bit errors and detecting 2-bit errors, which have been used in the past, have been adopted in the main memory.

(Problems to be Solved by the Invention) However, there are faults that cannot be corrected by any of the above methods, and when such faults occur, there is a drawback that the operation of the information processing device cannot be continued.

An object of the present invention is to check the microprogram word read from the control memory, and when an uncorrectable error is detected, to instruct the circuit controlled by the microprogram to inhibit execution, and to change the microprogram address to the main memory address. The above-mentioned drawbacks are eliminated by converting the microprogram word into a main memory address and reading the microprogram word from the main memory device, and switching between the read microprogram word and the microprogram read from the control memory to release the inhibition of execution. An object of the present invention is to provide an information processing apparatus configured to continue operation even when an uncorrectable fault in control memory is detected.

(Means for Solving the Problems) An information processing apparatus according to the present invention includes a control memory, a checking means, and! I! The control memory is for storing control information consisting of a first microprogram word. be.

The checking means are for checking the first microprogram word read from the control store.

The execution control means temporarily inhibits execution of the circuit controlled by the microprogram when an uncorrectable error condition is detected by the checking means, and releases the inhibition when the error condition is eliminated. belongs to.

The address conversion means is for converting the address of the microprogram into a main memory address of the main memory so that when an error occurs, the microprogram can be read from the main memory and the error can be canceled.

The memory access means is for reading a second microprogram word having the same contents as the first microprogram word from the main memory device using the main memory address when an error occurs. This is for switching and selecting either the second microprogram word read out from the control memory or the first microprogram word read out from the control memory.

(Implementation row) Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the information processing apparatus of the present invention includes a control memory 1 and a microprogram address register 7 for providing a read address of the control memory 1.
, a switching means 5 for switching between the read data of the control memory 1 and the main memory read data, a microprogram word register 6 which receives the output of the switching means 5 as an input, and a microprogram word register 6 which receives the output of the microprogram word register 6 as an input. A check circuit 3, a control memory control circuit 4 which receives the check output from the check circuit 3, a shift circuit 8 which receives the output of the microprogram address register 7 and generates a main memory address, and a main memory 12. , a microprogram word pointer register 9 for giving the beginning of the microprogram word area on the main memory 12. It consists of an adder circuit 10, an execution circuit 2 controlled by a microprogram, and a memory access address register 11.

Next, the operation of the implementation sequence of the information processing apparatus according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is an explanatory diagram showing the arrangement relationship between the main memory device 12 and the control memory 1 in one embodiment of the present invention. In FIG. 2, 201 indicates an area of the entire main memory, and 202 indicates an area where microprogram words are stored. In this implementation sequence, there is a complete one-to-one correspondence with the microprogram word group 203 inside the control memory 1.

In this embodiment, all copies of the microprogram word group 203 in the control memory 1 are stored in the area 2 in the main memory 12.
It is stored in 02. However, in applications where the price and size of the internal area of the main memory 12 are an issue, depending on the importance of the microprogram, it may be necessary to copy only part of the microprogram word, for example, only a certain address range. It is also possible to store it on the main storage device 12.

In this case, if an error occurs in the read data of the control memory 1, which has no copy on the main memory 12, the operation will be the same as the conventional one.

In this embodiment, as already explained, since there is a complete one-to-one correspondence between the microprogram words inside the control memory 1 and the inside of the main memory 12, the microprogram words inside the control memory 1 Letting the address be X, the corresponding main memory address y is expressed as follows.

y=α+βX·φ··畢(1) Here, α indicates the contents of the microprogram word pointer register 9 that indicates the beginning of the microprogram word group inside the main storage device 12. β is determined by using the address of the main memory 12 as a byte address, and an address conversion coefficient for configuring one microprogram word with a plurality of bytes. Actual implementation? In +3, it is assumed that one microprogram word consists of 4 bytes, and β is assumed to be 4.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

The address of microprogram address register 7 is
It is sent to the control memory via the data signal line 100, and one word inside the control memory 1 is read out and input to one input terminal of the switching means 5 via the data signal line 101. At this time, the selection signal sent from the check circuit 6 to the switching means 5 via the control signal line 102 selects the read data from the control memory 1. Switching means 5
The output is set in the microprogram word register 6 via the data signal line 10. Subsequently, the output of the microprogram word register 6 is sent to the execution circuit 2 controlled by the microprogram via the data signal line 104.
sent to. The execution circuit 2 executes the operation specified by the contents of the microprogram word register 6. on the other hand,
The data signal line 104 is also connected to a check circuit B, which checks the contents of the microprogram word register 6 by a known method such as a parity check or a Hamming code check. As a result,
If no error is detected, the selection signal on the control signal line 102 only requests the switching means 5 to select the read data of the control memory 1 as it was, and in particular, it performs a different operation from the conventional device. There's nothing to do. However, if an error is detected, the check circuit 3 instructs the switching means 5 to select the read data from the main memory 12 via the control signal ll1102. The check circuit also sends an inhibit signal to the execution circuit 2 via the control signal line 105 in order to inhibit the operation specified by the contents of the microprogram word register 6. Furthermore, the control signal line 10
5 reports the detection of an error to the control storage control circuit 4.

Next, after receiving the error report from the check circuit 6 of the control memory control circuit 4, the input that is taken from the control memory 1 to the microprogram word register 6 via the switching means 5 is normally read every machine cycle. Deter. Furthermore, the microprogram word address inside the microprogram address register 7 is sent via the data signal [00 to the shift circuit 8 and shifted by two bits. This is a conversion in which the main memory address is a byte address and the microprogram word is composed of 4 bytes. Further, the output of the shift circuit 8 is transmitted to the data signal line 10.
6 to one terminal of the adder circuit 1o, and the output of the microprogram word pointer register 9 is input to the other terminal of the adder circuit 1o via a data signal line 107.

As already explained, the output of the adder circuit 10 indicates the microprogram word address in the main memory 12 corresponding to the microprogram word in which the error occurred due to the above operation. The output of the adder circuit 10 is set in the memory access register 11 via the data signal line 108. The control memory control circuit 4 generates a memory access request code for the main memory 12 and sends it to the control signal line 11.
It is sent to the main storage device 12 via G. At this time, the output of the memory access register 11 is the data signal i! 11
09 to the main storage device 12.

Thereafter, the main memory device 12 executes a read operation using a known method based on the above request, and upon completion of the above operation, sends a memory access reply signal to the control storage control circuit 4 via the control signal line 111. , and sends the read data to the switching means 5 via the data signal line 112. Therefore, the control storage control circuit 4 releases the inhibition of data acquisition into the microprogram word register 6. At this time, since the switching means 5 selects the read data from the main memory device 12, the read data from the main memory device 12 is taken into the microprogram word register 6. Therefore, the output of the microprogram word register 6 is the output of the execution circuit 2.
, and normal microprogram-controlled operation resumes.

(Effects of the Invention) As explained above, the present invention enables continuous operation of the system by automatically reading out the microprogram words inside the main memory even when an error occurs in the control memory. It has the effect of making

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. FIG. 2 is an explanatory diagram showing the correlation between microprogram words contained in the control memory and the main memory. 1...Control memory 2...-Execution circuit command...Check circuit 4...Control memory control circuit 5--Switching means 6...ΦMicro program word register 7...Fist micro program address register 8...・・Shift circuit 9・・Lower microprogram word pointer system 10・Salary-addition circuit 11・・Memory address register 12・・・Main storage device

Claims (1)

[Claims] a control memory for storing control information consisting of a first microprogram word; a check means for checking the first microprogram word read from the control memory; and an error that cannot be corrected by the check means. Execution control means for temporarily inhibiting execution of a circuit controlled by a microprogram when the error state is detected, and releasing the inhibition when the error state is released; an address conversion means for converting the address of the microprogram to a main memory address of the main memory so that the error can be canceled by reading the microprogram from the main memory at times, and when the error occurs, a memory access means for reading a second microprogram word having the same content as the first microprogram word from the main memory according to the main memory address; and a second microprogram word read by the memory access means. An information processing apparatus comprising: switching means for switching and selecting a microprogram word or the first microprogram word read from the control memory.