JPH03142537A - Pseudo fault generating circuit - Google Patents

Abstract

PURPOSE:To detect a fault and to check whether the correct fault processing is possible or not by generating the production timing and the production code of a pseudo fault with use of the random numbers and producing the pseudo fault. CONSTITUTION:A random number generating circuit 1 sends the 1st random number data 101 to a production timing deciding circuit 2 and the 2nd random number data 105 to a code designating register 4 respectively. The circuit 2 holds the F-rank data obtained by dividing the data 101 into two parts when a pseudo fault instruction mode signal 103 is equal to logic 1. This held value is compared with the higher ranks of the data 101 divided into two. When the coincidence is obtained with the comparison, a production timing signal 102 is sent to an AND circuit 5. A pseudo fault generation instruction mode register 3 is set at 1 when a pseudo fault instruction signal 100 is equal to logic 1 and sends the signal 103 to the circuit 5. The circuit 5 sends a pseudo fault generation instruction signal 104 to the register 4 and a pseudo fault generation instruction register 6 when both signals 102 and 103 are equal to logic 1. Then the register 4 holds the value of the data 105 and then sends it as a pseudo fault code 106 when the signal 104 is equal to logic 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a pseudo-failure generating circuit for testing a fault detection processing circuit.

[Conventional technology]

Conventionally, pseudo-failure generation circuits were configured using firmware, etc.
A pseudo-fault is occurring due to the pseudo-fault generation code or occurrence timing code.

[Problem to be solved by the invention]

The above-mentioned conventional pseudo-fault generation circuit uses firmware etc. to generate a pseudo-fault after a command is generated at a certain timing, so pseudo-faults cannot be generated truly randomly. However, there is a drawback in that it is not possible to detect failures and test whether or not correct failure handling can be performed for failures that occur randomly during the operation of the processing device.

[Means to solve the problem]

The pseudo-fault generation circuit of the present invention includes a random number generation circuit and a pseudo-fault occurrence mode flag indicating a pseudo-fault generation mode, and includes a first one generated by the random number generation circuit when the pseudo-fault occurrence mode flag is set. an occurrence timing determination circuit that determines the timing of occurrence of a pseudo failure based on random number data; and a code designation register that stores second random number data generated by the random number generation circuit as a code for specifying the location where the pseudo failure occurs. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, one embodiment of the present invention shows random number generation times 1i1
81, an occurrence timing determining circuit 2 that determines the timing of occurrence of a pseudo fault using first random number data 101 generated by the random number generation circuit 1, and a pseudo fault occurrence instruction mode register 3 that holds a pseudo fault instruction signal 100. , an output signal 10 obtained by ANDing the second random number data 105 generated by the random number generation circuit 1, the output signal 102 of the generation timing determination circuit 2, and the output signal 103 of the pseudo fault occurrence instruction mode register 3.
4, a code designation register 4 stores the pseudo fault code as a pseudo fault code, and a pseudo fault occurrence instruction register 6 holds the value of the pseudo fault occurrence instruction signal 104 for one tarlock cycle and outputs an enable signal 107 for the decoder of the logic circuit. It is configured.

Random number generation circuit 1 sends first random number data 101 to generation timing determination circuit 2 and second random number data 105 to code instruction register 4.

When the pseudo-failure instruction mode signal 103 is logic 1, the occurrence timing determining circuit 2 holds lower data obtained by dividing the first random number data 101 into two, and divides the held value and the first random number obtained by dividing into two. If the data 101 is compared with the upper order of the data 101 and they match, the generation timing signal 102 is sent to the AND circuit 5.

The pseudo fault occurrence instruction mode register 3 receives the pseudo fault instruction signal 1.
When 00 is logic 1, it is set to "1" and sends the pseudo fault indication mode signal 103 to the AND circuit 5. The AND circuit 5 sends a pseudo fault occurrence instruction signal 104 to the code designation register 4 and the pseudo fault occurrence instruction register 6 when both the occurrence timing signal 102 and the pseudo fault instruction mode signal 103 are logic 1. The code designation register 4 holds the value of the second random number data 105 when the pseudo fault occurrence instruction signal 104 is logic 1. The held value is sent to the logic circuit 7 as a pseudo fault code 106. The pseudo fault occurrence instruction register 6 holds the pseudo fault occurrence instruction signal 104 for one clock cycle and sends an enable signal 107 to the logic circuit 7 and the pseudo fault occurrence instruction mode register 3. In the false fault occurrence instruction mode register 3, the reset signal 107 is set to logic 1.
When the enable signal 107 is logic 1, the logic circuit 7 decodes the pseudo fault code 106, performs an OR with the normal fault signal 108, and sets the fault indication register.

FIG. 2 is a circuit diagram of the generation timing determining circuit 2 of FIG. 1. In FIG. 2, the first random number data 101 is divided into upper and lower parts. Lower storage register 8 is 2
The lower part of the divided first random number data is held when the pseudo fault indication mode signal 10B is logic 1. The comparison circuit 10 is
When the lower data 109 of the first random number data and the upper data 110 of the first random number data match, a generation timing signal 102 is sent to the AND circuit 5 and the upper storage register 9. The upper storage register 9 receives the generation timing signal 10
When 2 is logical 1, the first random number data 101 divided into two
Keep the upper value of .

〔Effect of the invention〕

As explained above, the present invention can generate pseudo failures at random by determining the occurrence timing and generation code of pseudo failures using random numbers, and generating pseudo failures.
For failures that randomly occur during the operation of processing equipment,
This has the effect of detecting failures and testing whether correct failure handling is possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a pseudo fault generation circuit according to an embodiment of the present invention, and FIG. 2 is a circuit configuration diagram showing the generation timing determination circuit 2 of the second construction drawing. ■... Random number generation circuit, 2... Occurrence timing determining circuit, 3... False fault occurrence instruction mode register, 4... Code designation register, 5... AND circuit, 6... False fault Occurrence instruction register, 7...Logic circuit, 8...Lower storage register, 9...Upper storage register, 10...Comparison circuit, 100...Pseudo fault instruction signal, 101...
First random number data, 103... generation timing signal,
103...Pseudo fault instruction mode signal, 104...Pseudo fault occurrence instruction signal, 105...Second random number data,
106... Pseudo fault code, 107... Enable signal, reset signal, 108... Normal fault display signal,
109...Lower data of the first random number data, 110...
... Upper data of the first random number data.

Claims (1)

[Claims] A random number generation circuit and a pseudo failure occurrence mode flag indicating a pseudo failure occurrence mode are provided, and when the pseudo failure occurrence mode flag is set, the timing of occurrence of a pseudo failure is determined by first random number data generated by the random number generation circuit. A pseudo-failure generation circuit comprising: a generation timing determination circuit for determining the occurrence timing; and a code designation register for storing second random number data generated by the random number generation circuit as a code for specifying the location where the pseudo-fault has occurred. .