JPH01292444A - Pseudo fault generating system - Google Patents

Abstract

PURPOSE:To increase apparent pseudo fault generating positions and to improve the evaluation capacity of a fault processing function by suppressing the detection of an error during the period of a specified period. CONSTITUTION:When the generation of a fault in a register 3 is intended, a pseudo fault generation instructing circuit 4 sends a fault generation instructing signal 20 held at a high level and sends a suppressing time specifying signal 21 by setting up a suppressing time to two machine cycles. Thereby, an error is generated in an output of a register 1 by a parity inversion circuit 7. The error is detected by an error detecting circuit 8. Since the output '2' of a decoder is turned to a high level and the output of an AND circuit 52 is also turned to a high level, a suppression signal 22 is turned to a high level and a flip flop 56 is set up. Since an output from an inverter 60 in a fault display circuit 6 is low level, the error of the register 1 is not registered in the register 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a simulated failure departure system, and more particularly to a simulated failure generation system that generates a simulated failure within an information processing device.

2. Description of the Related Art Generally, information processing devices, especially large-sized information processing devices, have a failure detection circuit and a failure processing function such as retry processing when a failure is detected. Like normal processing functions, these failure processing functions also need to be evaluated to determine whether they operate normally as intended.

As a method for evaluating this, there is a method of causing a pseudo failure in a circuit within the device and checking whether the subsequent failure handling function is performed correctly. Conventionally, there have been three methods for generating this pseudo-fault:

The first method is to physically set a signal to a fixed value from the outside while the actual device is operating.

In order to improve the effectiveness of the test, this method requires implementation supplements that can physically set various external signals to fixed values. However, in the crisis processing device, L
SI (Large 5cale Integrat
This method has the drawback of being difficult as the number of circuits (ed circuits) increases.

The second method is to incorporate in advance a logic circuit that causes a pseudo-failure in multiple circuits within the device, and cause a failure to occur in a designated circuit by an instruction to generate a W-simulated failure from the outside. . In this case, the fault is generated by, for example, inverting the parity bit of the circuit specified by the pseudo-fault generation instruction. When the failure detection circuit detects a parity error, the device enters a failure state and then performs failure processing.

In this method, by changing the configuration of the pseudo-fault occurrence instruction circuit, for example, a pseudo-failure can be caused to occur when a specific microinstruction address is executed, or a pseudo-fault can be caused to occur at random timing instructed from the outside. A failure can occur at a relatively arbitrary timing. However, there is a drawback in that it is difficult to provide a large number of circuits that are subject to failures due to the burden on the hardware.

The third method is to cause a failure in a specified circuit on a simulation model rather than on an actual device, and check the failure handling function through simulation. but,
With this method, it is possible to generate a pseudo-fault in any circuit, but since it is a simulation model that is used to check failures such as retry processing after failure detection, it has the disadvantage that it takes too much execution time. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a simulated failure generation system that can simulate failures at many locations on an actual device.

Structure of the Invention The pseudo-fault generation system of the present invention includes a plurality of registers that are connected in multiple stages and in which internally held information is propagated to the next stage at every predetermined period (T), and a register that responds to a pseudo-error generation command. pseudo-error generating means for generating a pseudo-error on information held in a first-stage register of the plurality of registers; and a pseudo-error generating means provided corresponding to each of the plurality of registers and responsive to a detection command. an error detecting means for detecting an error in information held in a register; and an error detecting means for detecting an error in information held in a register; and an error detection means for detecting an error in information held in a register; The present invention is characterized by comprising an error detection control means for enabling the error detection means corresponding to the N-th register after TN.

K1j Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system diagram showing the configuration of an embodiment of a pseudo fault generation system according to the present invention. In FIG. 0, the pseudo fault generation system according to an embodiment of the present invention includes a pseudo fault generation instruction circuit 4, The circuit includes a circuit 5, a failure display circuit 6, a parity inversion circuit 7, and parity error detection circuits 8, 9, and 10. Note that register 1.
2 and 3 and the combinational circuit 11 are circuits used for normal processing inside the device.

The output of register 1 is input to register 2, and the output of register 2 is input to register 3 via combinational circuit 11. Therefore, data in register 1 is propagated to If in the order of register 2 → register 3 → . . . every cycle (machine cycle) of a clock pulse for operating the device.

Therefore, if an error occurs in register 1, the error will propagate to register 2 one cycle later, and then to register 3 one cycle later.

This embodiment takes advantage of this, and a parity inversion circuit 7 is provided between registers 1 and 2 to invert the parity bit in order to generate a pseudo error. This parity inversion [11G7 is to invert the parity bit P of the register 1 to generate a pseudo fault only when the fault occurrence instruction signal 20 from the pseudo fault generation support circuit 4 is at a high level.

Further, the error detection circuits 8, 9 . and 10 detect errors in the data in the corresponding registers 1, 2 and 3 by parity check, and their output group 23
is input to the failure display circuit 6. When the occurrence of an error is registered in the failure display circuit 6, failure processing such as retry processing is performed.

Furthermore, the pseudo fault occurrence instruction circuit 4 sets the fault occurrence instruction signal 20 to a high level to cause the parity inversion circuit 7 to generate a parity error in the register 1, and also sends the inhibition time designation signal 21 to the inhibition signal generation circuit 5. The inhibition signal generation circuit 5 inhibits the registration of the occurrence of an error in the failure display circuit 6 for a period corresponding to the inhibition time designation signal 21 using the inhibition signal 22 .

Therefore, one of the error detection circuits 8.9 and 10
Even if an error is detected, the error is not registered in the failure display circuit 6 during the period in which it is inhibited by the inhibition signal 22.
Failure handling is not performed.

Next, the configuration of the inhibition signal generation circuit 5 and the failure indication circuit 6 will be explained using FIG. 2. FIG. 4 shows the inhibition signal generation circuit 5.
In FIG. 0, which is a system diagram showing a configuration example of the failure display circuit 6, the inhibition signal generation circuit 5 includes a decoder 50, AND circuits 51, 52, and 53, OR circuits 54 and 57,
It is configured to include flip-flops (F/F) 55 and 56.

The inhibition time designation signal 21 from the pseudo fault generation circuit 4 is input to the decoder 50 . This inhibition time designation signal 21 is input in an encoded state to designate the time to inhibit failure detection. In this embodiment, for simplicity, the inhibition time is in the range of 0 to 3 machine cycles. Among the four outputs of the decoder 50, the output "1" is output from the AND circuit 51.
The signal is then input to the failure display port 1i6 as the inhibition signal 22 via the OR circuit 57.

Further, the output "2" is the AND circuit 52 and the OR circuit 54.
57 as the inhibition signal 22 to the fault display circuit 6, and the AND circuit F! ! I52 and OR circuit 54
The signal is inputted to the flip-flop 56 via.

Furthermore, the output "3" is input to the failure display circuit 6 as the inhibit signal 22 via the AND circuit R53 and the OR circuit 57, and is also input to the flip-flop 55. The output of the flip-flop 55 is input to the failure indicating circuit 6 via the OR circuits 54 and 57 as the inhibit signal 22, and is also input to the flip-flop 56. The output of the flip-flop 56 is inputted to the failure indicating circuit 6 via an OR circuit 57 as an inhibition signal 22. Note that the AND circuit 51
．． The other inputs of 52 and 53 each receive a failure occurrence instruction signal 2.
0 is input.

On the other hand, the failure display circuit 6 includes an inverter 60, a plurality of AND circuits 61, and a register 62 for failure indication. Output groups 23 from a plurality of error detection circuits provided in the device are each connected to a corresponding bit in a register 62 via an AND circuit 61.

The register 62 is composed of a plurality of bits, and an AND circuit 61 is provided corresponding to each bit. The AND circuit 61 receives the output group 23 from a plurality of error detection circuits provided in the device as well as the inhibition signal 22 from the inhibition signal generation circuit 5 via the inverter 60 . Therefore, the value of output group 23 is written to the corresponding bit in register 62 only when inhibit signal 22 is at a low level.

In such a configuration, when it is desired to cause a fault to occur in the register 3, the pseudo-fault occurrence instruction circuit 4 sends out the fault occurrence instruction signal 20 at a high level and sets the suppression time to 2.
The inhibition time designation signal 21 is sent out as a machine cycle. Then, an error occurs in the output of the register 1 by the parity inversion circuit 7, and the error is detected by the error detection circuit 8.

At this time, the output "2" of the decoder becomes high level,
Since the output of the AND circuit 52 becomes high level, the inhibition signal 22 becomes high level and the flip-flop 5
6 is set. In this case, since the output of the inverter 6o in the failure display circuit 6 is at a low level, the error in the register 1 is not registered in the register 62.

In the next machine cycle, the fault occurrence instruction signal 2° becomes low level, but the output of the inverter 60 in the failure display circuit 6 is low level since the output of the flip-flop 56 is high level. Therefore, even if an error propagated to register 2 is detected by error detection circuit 9, register 6
2 is not registered.

In the next machine cycle, the flip-flop 56
is set to a low level, the inhibition signal 22 is at a low level, and the output of the inverter 60 in the failure indicating circuit 6 is at a high level. Therefore, the error propagated to the register 3 is detected for the first time by the error detection circuit 10 in this machine cycle, and is registered in the corresponding bit of the register 62 in the failure display circuit 6. As a result, retry processing and the like are performed.

In addition, when an error is not generated in register 1, if the inhibition time is set to "0" machine cycle and the inhibition time designation signal 21 is sent, the error detection circuit 8 detects the error in register 1, and the failure indication circuit is immediately activated in this machine cycle. 6 will be registered.

Furthermore, when it is desired to generate an error in the register 2, if the inhibition time is set to "1" machine cycle and the inhibition time designation signal 21 is sent, the error detection circuit 9 detects the error in the register 2 after one machine cycle, and a failure is displayed. Registered in circuit 6.

Similarly, the inhibition time designation signal 2 is set as "3" machine cycle.
If 1 is sent, it will be registered in the failure display circuit 6 as an error in the register (not shown) following register 3.

As described above, by providing an error detection circuit in advance at a location where a failure is desired to occur and inputting its output to the failure display circuit 6, pseudo failures can be generated at various locations within the device. It is.

Note that even if there are a plurality of locations where a pseudo-fault occurs, the pseudo-fault generation instruction circuit, inhibit signal generation circuit, and fault display circuit 6 are all common, so only a small amount of hardware is required.

As explained above, the present invention can increase the number of apparent pseudo-failure occurrences by suppressing the detection of errors during a specified period, so it is difficult to evaluate the failure handling function. It has the effect of improving abilities.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of a pseudo-fault generation system according to an embodiment of the present invention, and FIG. 2 is a system diagram showing the configuration of the inhibit signal generation circuit 5 and the failure display circuit 6 of FIG. Explanation of symbols of main parts 1.2.3...Register 4...Pseudo fault occurrence instruction circuit 5...Suppression signal generation circuit 6...Fault indication Circuit 7...Parity inversion circuit

Claims (1)

[Claims] (1) A plurality of registers that are connected in multiple stages and whose internally held information is propagated to the next stage at every predetermined period (T), and a register that is connected to the first stage of the plurality of registers in response to a pseudo error generation command. pseudo-error generating means for pseudo-generating an error on information held in a register; and an error in information held in the register in response to a detection command, provided corresponding to each of the plurality of registers. and an error detection means for detecting the error detection means corresponding to the N-th register in response to information instructing to generate an error in the N-th register of the plurality of registers (N is an integer). A pseudo-failure generation system comprising: error detection control means for enabling the error detection means after T/N.