JPH04330700A - Designated fail number address search circuit of memory tester - Google Patents

Abstract

PURPOSE:To search an X-address or a Y-address having a fail address more than a prescribed value as a relief address in short time. CONSTITUTION:A memory 2 stores fail data in the same address as the fail address of a memory for tested object. The memory 2 is read at high speed by an address signal from an address generator 1. A comparator 4 adds fail data which is read from the memory 2 as to the same X-address or the same Y-address and compares an added value with the prescribed value stored in a register 3. The comparator 4 outputs a write enable signal to a memory 5 when the added value of fail data is large. The memory 5 stores the address signal outputted from the address generator 1 as data at timing when the write enable signal is inputted.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a specified fail number address search circuit of a memory tester, and in particular, an X address (row address) or a Y address (column address) having more fail addresses than a predetermined value is set as a relief confirmed address. The present invention relates to a specified fail number address search circuit for a memory tester suitable for completing a search in a short time when searching.

0002

2. Description of the Related Art In the prior art, in order to improve the yield of memories cut out from wafers, a plurality of spare memory columns (hereinafter referred to as redundant (referred to as a line memory column), and when the memory address in the X address column or the Y address column is in a fail state,
The memory is now operated normally by replacing the redundant line memory column.

[0003] In the above conventional technology, for example, if the number of memory addresses in a fail state is greater than a predetermined value,
Alternatively, when searching for a Y address in which the number of memory addresses in a fail state is greater than a predetermined value as a repair confirmed address, the conventional method is as follows. First, specific data is written to each address of the memory, then the data is read from the memory, and it is determined whether the read data and the written data match. If they do not match, the address is determined to have failed. Next, the memory addresses determined as failures in this way (hereinafter referred to as fail addresses) are sequentially stored in the fail memory. That is, "1" is stored at the same address as the fail address in the fail memory. The fail address recorded in the fail memory is C
The PU sequentially reads out the fail addresses, and the number of fail addresses existing at the same X address or the same Y address is recognized by the CPU.

0004

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the fail address stored in the fail memory is
Since hardware is used that sequentially reads data by the PU, there is a problem in that it takes a lot of time to recognize the number of fail addresses that exist at the same X address or the same Y address.

The present invention has been made in view of the problems of the prior art described above, and when searching for an X address or a Y address having more fail addresses than a predetermined value as a relief confirmed address, the search can be performed in a short time. It is an object of the present invention to provide a specified fail count address search circuit for a memory tester suitable for completion.

[0006]

[Means for Solving the Problems] A designated fail number address search circuit of a memory tester of the present invention includes a register that stores a predetermined value as a designated fail number, and a register that stores fail data at the same address as the fail address of the memory under test. The same X
A comparator that counts addresses or the same Y address, determines whether the counted value is greater than the specified fail number read from the register, and outputs a write enable signal if it is larger, and a comparator that receives the write enable signal and writes It is composed of a designated fail number address registration memory that stores the address signal output from the address generator at the timing when the enable signal is output.

[0007]

[Operation] According to the present invention, the fail data stored in the fail memory is read out using an address generator that operates at high speed without being read out by the CPU. When searching for the Y address as a relief confirmed address, the search can be completed in a short time.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to embodiments shown in the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 1 is an address generator, 2 is a fail memory, 3 is a designated fail number register, 4 is a comparator, 5 is a designated fail number address registration memory, 6 is an address bus, and 7 is a tester bus.

In FIG. 1, a fail address is input as an address signal to the fail memory 2, and fail data (for example, "1") is input in synchronization with the fail address.
is input. Here, the method for detecting the fail address is the same as the method described in the related art. As a result, the fail data is stored at the same address as the fail address in the fail memory 2.

When the writing of fail data into the fail memory 2 is completed, the address generator 1 sequentially outputs address signals starting from address 1. This address signal is
It is input to the fail memory 2 and the designated fail number address registration memory 5. Therefore, fail memory 2 is
The data stored at the address indicated by the input address signal is read out and output to the comparator 4.

On the other hand, a predetermined value is stored in the designated fail number register 3 from a CPU (not shown) via a tester bus 7. That is, an X address or a Y address having more fail addresses than this value is set as a relief confirmed address.

The comparator 4 counts the fail data read from the fail memory 2 for the same X address or the same Y address, and compares it with the designated fail number output from the designated fail number register 3. As a result of the comparison, if the count value is larger than the designated fail number, a write enable signal is output to the designated fail number address registration memory 5. As a result, the specified fail count address registration memory 5 is configured to register the address generator 1 at the timing when the write enable signal is output.
The address signal output from the memory is stored as data. The address signals are stored in the designated fail number address registration memory 5 in order from address 1 of the designated fail number address registration memory.

When all the data in the fail memory 2 has been read out, the CPU (not shown) reads out the address stored in the specified fail number address registration memory 5,
Detect addresses that should be rescued.

As is clear from the above description, according to the above embodiment, the fail memory 2 is read out based on the address signal output from the address generator 1. This enables high-speed reading and completes the search for a relief address in a short time compared to the case where the data is stored in the memory.

[0015]

According to the present invention, when an X address or a Y address having more fail addresses than a predetermined value is searched as a repair confirmed address, the search can be completed in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

1 Address Generator, 2 Fail Memory, 3 Specified Fail Number Register, 4 Comparator, 5 Specified Fail Number Address Registration Memory, 6 Address Bus, 7 Tester Bus

Claims (1)

[Claims] 1. A register that stores a specified number of failures, a fail memory that stores fail data at the same address as a fail address of a memory under test, and an address generator that outputs an address signal to the fail memory. The fail data read from the fail memory based on the address signal output from the address generator is counted for the same X address or the same Y address, and whether the counted value is greater than the specified fail number read from the register. a comparator that determines whether or not the write enable signal is present and outputs a write enable signal if it is larger; and a specified fail number that receives the write enable signal and stores the address signal output from the address generator at the timing when the write enable signal is output. A designated fail number address search circuit for a memory tester, comprising an address registration memory.