JPH0792230A - Integrated circuit and circuit for detecting trouble of integrated circuit - Google Patents

Abstract

PURPOSE:To provide an integrated circuit and a circuit for detecting a trouble of the integrated circuit which can indicate a troubled circuit for every integrated circuit by dividing a plurality of integrated circuits. CONSTITUTION:A comparing means 43 of a trouble-detecting circuit 4 compares a holding means 41 for holding expected values with a holding means 42 for holding state values sequentially from an integrated circuit 1, with holding the comparing number of times. A trouble-detecting means 44 notifies an indicating means 45 of a signal indicative of s disagreement of the means 41 and 42 when a comparing result by the comparing means 43 detects the disagreement. Upon receipt of the notification, the indicating means 45 indicates that the integrated circuit 1 is a troubled circuit if the number of times for comparison is '1' when the disagreement is detected, an integrated circuit 2 is a troubled circuit if the number of times for comparison is '2', or an integrated circuit 3 is a troubled circuit if the number of times for comparison is '3'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit and an integrated circuit failure detection circuit, and more particularly to an integrated circuit having a scan path therein and an integrated circuit failure detection circuit.

[0002]

2. Description of the Related Art As shown in the block diagram of FIG. 4, a conventional integrated circuit and a failure detection circuit for the integrated circuit are provided with respective integrated circuits 5.
In each of 1, 52 and 53, a plurality of stages of flip-flops that form a scan path are provided, and are connected in cascade at the time of a test by a circuit (not shown) and each of them is controlled under the control of the failure detection circuit 54. The logic states of the integrated circuits 51, 52 and 53 are output via the scan path 55. Further, at this time, the failure detection circuit 54 holds scan control means 56 for controlling whether the data of each integrated circuit 51, 52, 53 is scanned in or out, and scan out data received from the scan control means 56. State value holding means 57, expected value holding means 58 that holds in advance two data groups whose logical values of all data are "0" and "1", and state value holding means 5
7 and the expected value holding means 58 compare the data held by the comparison means 59, which outputs a signal indicating a mismatch when the results do not match, and the signal indicating a mismatch from the comparison means 59. The failure detection means 60 that detects a failure occurrence and generates a failure notification signal, and the integrated circuit 51, 52, by receiving the failure notification signal from the failure detection means 60.
And a pointing means 61 for pointing out the defective integrated circuit in 53.

Next, an actual failure detection operation will be described.

The failure detection circuit 54 is comprised of the scan control means 5
6, the expected value holding means 5 is provided in order to detect the fixed failure of the logical value "1" in each integrated circuit 51, 52, 53.
The data group whose logical value of all data from "8" is "0" is scanned into the flip-flops of the integrated circuits 51, 52 and 53 on the scan path 55, and then the scan out is performed to store the scan-out data in the state value holding means. 57 and the comparison means 59 is instructed to compare. The comparing means 59 is a data group in which the logical values of the scan-out data of all the flip-flops on the scan path 55 stored in the state value holding means 57 and all the data stored in the expected value holding means 58 are “0”. Compare with. If the comparison results are in agreement, the scan control means next detects the fixed failure of the logical value "0" from the expected value holding means 58 by using the data group in which the logical values of all the data are "1". After scanning in the flip-flops of the integrated circuits 51, 52, 53 on the scan path 55, scanning is performed, scan-out data is stored in the state value holding means 57, and the comparing means 5
9 gives a comparison instruction. The comparison means 59 is the state value holding means 5
7 and the scan-out data of all the flip-flops on the scan path 55, and the expected value holding means 58.
The logical value of all the data stored in is compared with the data group of "1". When the compared results do not match, the indicating means 61 receives the data of the comparison result and indicates the defective integrated circuit.

[0005]

The above-described conventional integrated circuit and the failure detection circuit for the integrated circuit described above have a fixed failure and a logic value of "1" even if the integrated circuit is a large-scale integrated circuit. In order to detect the fixed failure of the value "0", the data group having the logical value "0" and the data group having the logical value "1" of all the data are transferred from the expected value holding means to the flip-flop of each integrated circuit on the scan path. Since scan-in was performed after scan-in and comparison was performed by the comparison means, if a failure occurs in the scan path, all the scan-out data related to this will go wrong and many simulated circuits will be generated. There is a problem that it may be pointed out.

An object of the present invention is to provide an integrated circuit and a failure detection circuit for the integrated circuit, which are capable of distinguishing a plurality of integrated circuits and indicating a failure generating circuit in units of the integrated circuits.

[0007]

SUMMARY OF THE INVENTION An integrated circuit of the present invention is an integrated circuit having a scan path therein, which comprises a plurality of flip-flops having a reset function for scanning data in and out. In the configuration, a flip-flop that takes a logical value "1" at the time of reset is provided in the previous stage.

A failure detection circuit of an integrated circuit according to the present invention is a scan for controlling scan-in and scan-out of data to each integrated circuit by a scan path for a large scale integrated circuit composed of a plurality of integrated circuits having the same scan path. Control means, state value holding means for holding scan-out data given by the scan control means, expected value holding means for holding the state value output by the integrated circuit in advance, the state value holding means, and the The occurrence of a failure is detected by comparing the held value held by the expected value holding means and outputting a signal indicating a mismatch when there is a mismatch and a signal indicating a mismatch from this comparing means. A failure detection unit that generates a failure notification signal, and a failure notification signal from the failure detection unit is received to detect a failure in the large-scale integrated circuit. In a failure detection circuit for an integrated circuit, which includes pointing means for pointing out an integrated circuit, the integrated circuit includes a flip-flop that takes a logical value "1" at the time of reset, in the preceding stage of a scan path composed of a plurality of flip-flops having a reset function. And a function of resetting all the flip-flops forming the scan path to the scan control means, a function of scanning out the state values of all the flip-flops after the reset, and a state holding the result of the scan-out. Means for storing the expected values when all the lip flops are reset in advance in the expected value holding means, and the contents of the state value holding means and the expected value holding means in the comparing means. A function of comparing in each integrated circuit unit and counting the number of comparisons in each integrated circuit unit Provided, it is configured to point out integrated circuit failed by referring to the contents of the number as compared to each integrated circuit units by the failure notification from the failure detection means to the indicated means.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the integrated circuit of the present invention.

The integrated circuit 1 has a scan path inside. This scan path is composed of a plurality of flip-flops 10, 11, 12, 13, and 14. Among them, the flip-flops 10, 11, 12, and 13 have a logical value “0” at the time of reset, and the flip-flops have a logic value of “0”. 14
Has a logical value of "1" at reset.

FIG. 2 is a block diagram of an embodiment of a failure detection circuit for an integrated circuit according to the present invention.

The plurality of integrated circuits 1, 2 and 3 having the same scan path are respectively flip-flops 10 to 1.
4, 20 to 24, 30 to 34, and the failure detection circuit 4
Is connected to the integrated circuits 1, 2 and 3 via the scan path 5 and is capable of sending the reset signal 6.
Further, the failure detection circuit 4 includes scan control circuit means 40, expected value holding means 41, state value holding means 42, and comparison means 43.
And a failure detecting means 44 and an indicating means 45.
The scan control means 40 scans out the state value after resetting the flip-flops 10-14, 20-24, 30-34 of the integrated circuits 1, 2, 3 by the scan path 5 and supplies it to the state value holding means 42. State value holding means 4
2 holds the state value of each integrated circuit given by the scan control means 40. The expected value holding means 41 holds in advance the state value after being reset when the flip-flops 10-14, 20-24, 30-34 are in the normal state. The comparison unit 43 sequentially compares the expected value holding unit 41 and the state value holding unit 42 from the integrated circuit 1 and holds the number of times of comparison. When the failure detecting means 44 detects a mismatch according to the comparison result by the comparing means 43, it notifies the pointing means 45 of a signal indicating the mismatch. Receiving this notification, the pointing means 45 detects the integrated circuit 1 when the number of comparisons when the mismatch is detected is "1", and the number of comparisons is "2".
In the case of, the integrated circuit 2 is indicated as a defective circuit, and in the case of the comparison number being "3", the integrated circuit 3 is indicated as a defective circuit.

Next, the details of the operation will be described with two examples.

FIG. 3 is an explanatory diagram for comparing and displaying the state value stored in the state value holding means and the state value stored in the expected value holding means at the time of a fixed failure. 3A shows a case where the flip-flop 13 of the integrated circuit 1 has a fixed failure of a logical value "0", and FIG. 3B shows a flip-flop 24 of the integrated circuit 2 has a logical value "0". It is explanatory drawing explaining the case where there is a fixed failure.

As a first example, a case where the flip-flop 13 of the integrated circuit 1 has a fixed failure of a logical value "0" will be described with reference to FIG.

The scan control means 40 uses the reset signal 6
After resetting all the flip-flops of the integrated circuits 1, 2 and 3, the scan path 5 scans out the state values of all the flip-flops and supplies them to the state value holding means 42. Next, the comparison means 43 compares the contents of the expected value holding means 41 corresponding to the flip-flops 10, 11, 12, 13, 14 of the integrated circuit 1 with the contents of the state value holding means 42, and the number of times of comparison is " 1 ". Since the failure detection circuit 44 detects that the compared contents do not match, the failure detection circuit 44 notifies the pointing means 45 of a signal indicating the mismatch. Upon receiving this notification, the pointing means 45 confirms the number of times the comparing means 43 has compared, and points out the integrated circuit 1 as a faulty circuit because the number of times is "1".

As a second example, a case where the flip-flop 24 of the integrated circuit 2 has a fixed failure of logical value "0" will be described with reference to FIG.

The scan control means 40 uses the reset signal 6
After resetting all the flip-flops of the integrated circuits 1, 2 and 3, the scan path 5 scans out the state values of all the flip-flops and supplies them to the state value holding means 42. Next, the comparison means 43 is the expected value holding means 4 corresponding to the flip-flops 10 to 14 of the integrated circuit 1.
The content of 1 is compared with the content of the state value holding means 42, and the number of comparisons is set to "1". The failure detection circuit 44 detects that the compared contents match each other, and requests the comparison means 43 to compare the next integrated circuit 2. The comparison circuit 43 receiving this comparison request compares the contents of the expected value holding means 41 and the contents of the state value holding means 42 corresponding to the flip-flops 20, 21, 22, 23, 24 of the integrated circuit 2 and compares them. The number of times of doing is set to “2”. Here, since the failure detection circuit 44 detects that the compared contents do not match, the failure detection circuit 44 notifies the pointing means 45 of a signal indicating the mismatch. Upon receiving this notification, the pointing means 45 confirms the number of times the comparing means 43 has compared, and since the number of times is "2", the pointing means 45 points out the integrated circuit 2 as a faulty circuit.

[0020]

As described above, according to the present invention, a logic value at the time of reset is provided in the preceding stage of the scan path constituted by a plurality of flip-flops having a reset function for scanning data in and scanning out in the integrated circuit. A flip-flop that takes "1" is provided, the function of resetting all the flip-flops forming the scan path to the scan control means in the failure detection circuit, the function of scanning out the state values of all the flip-flops after the reset, and the scan A function of storing the output result in the state holding means is provided, the expected value when all the lip flops are reset is held in advance in the expected value holding means, and the contents of the state value holding means and the expected value holding means in the comparing means It has a function to compare each integrated circuit unit and to count the number of each integrated circuit unit. By providing a function to point out the failed integrated circuit by referring to the number of contents compared to each integrated circuit unit by the failure notification from the failure detection means, a plurality of integrated circuits can be divided and the failure occurrence circuit can be pointed out. There is an effect that it can be performed for each integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an integrated circuit of the present invention.

FIG. 2 is a block diagram of an embodiment of a failure detection circuit for an integrated circuit according to the present invention.

FIG. 3 is an explanatory diagram for comparing and displaying a state value stored in a state value holding unit and a state value stored in an expected value holding unit when a fixed failure occurs.

FIG. 4 is a block diagram of a conventional integrated circuit and a failure detection circuit for the integrated circuit.

[Explanation of symbols]

1, 2 and 3 integrated circuit 4 failure detection circuit 5 scan path 6 reset signal 10 to 14, 20 to 24, 30 to 34 flip-flop 40 scan control circuit means 41 expected value holding means 42 state value holding means 43 comparison means 44 failure Detection means 45 Pointing means

Claims (2)

[Claims] 1. In an integrated circuit having a scan path inside, a logical value "1" is taken at the time of reset in the preceding stage of the scan path composed of a plurality of flip-flops having a reset function for scanning data in and out. An integrated circuit having a flip-flop. 2. A scan control means for controlling scan-in and scan-out of data to each integrated circuit by a scan path for a large scale integrated circuit composed of a plurality of integrated circuits having the same scan path, and the scan control means of the scan control means. State value holding means for holding the given scan-out data, expected value holding means for holding the state value output by the integrated circuit in advance, and holding held by the state value holding means and the expected value holding means Comparing means for comparing values and outputting a signal indicating non-coincidence in the case of non-coincidence, and fault detection means for detecting fault occurrence and receiving a fault notification signal by receiving a signal indicating non-coincidence from the comparing means And pointing means for pointing out the faulty integrated circuit in the large scale integrated circuit by receiving the fault notification signal from the fault detecting means. In the failure detection circuit of the integrated circuit, the integrated circuit has a flip-flop that takes a logical value "1" at the time of reset in the preceding stage of the scan path composed of a plurality of flip-flops having a reset function, and the scan control means is provided with the flip-flop. A function of resetting all the flip-flops forming the scan path, a function of scanning out the state values of all the flip-flops after the reset, and a function of storing the scan-out result in the state holding means are provided. The expected value holding means holds the expected values in the case of resetting all the lip flops in advance, and the comparing means compares the contents of the state value holding means and the expected value holding means for each integrated circuit. The integrated circuit unit is provided with a function for counting the number of comparisons, and the pointing means is provided with the failure detection. Failure detection circuit of the integrated circuit, characterized in that to point out integrated circuit failed by referring to the contents of the number as compared to each integrated circuit units by failure notification from stage.