CN113253796B - Asynchronous input signal synchronization method and device, central processing unit and chip - Google Patents
Asynchronous input signal synchronization method and device, central processing unit and chip Download PDFInfo
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Abstract
The invention relates to the field of chips, and provides a synchronization method and device of asynchronous input signals, a central processing unit and a chip. The method for synchronizing the asynchronous input signals is used for a dual-core step locking system, the dual-core step locking system comprises a first core and a second core, and the method comprises the following steps: inputting an asynchronous input signal into a first synchronizer and a second synchronizer simultaneously; and checking the output signal of the first synchronizer and the output signal of the second synchronizer. The dual-core lockstep system adopts the two synchronizers for comparison and detection, can capture the fault of any one synchronizer according to the comparison and verification result information of the output signals of the two synchronizers, and ensures the safety and the reliability of the dual-core lockstep system.
Description
Technical Field
The present invention relates to the field of chips, and in particular, to a method for synchronizing an asynchronous input signal, a device for synchronizing an asynchronous input signal, a central processing unit, and a chip.
Background
With the development and progress of integrated circuit technology, the application of embedded CPU (central processing unit) in the field of industrial control is also becoming more widespread. In this field, the safety and reliability of the CPU are one of the core indicators, and the dual-core lockstep technique has the most significant effect in many design ways for improving the safety and reliability of the CPU. The dual-core lockstep technology adopts two CPU kernels with completely consistent hardware circuits, the executed instructions are completely consistent, and the input signals are also completely consistent. In the dual core lockstep design, the input signal is divided into a synchronous input signal and an asynchronous input signal. The synchronous input signal is an input signal in the same clock domain with the CPU core, and can be directly sent to the dual cores. The asynchronous input signal is in a different clock domain with the CPU core, and can be sent to the CPU core only after being synchronized by the synchronizer.
In the dual core lock step design, the conventional way of synchronously processing the asynchronous input signal is as follows: the asynchronous input signal is fed into a synchronizer, and then the synchronous signal generated by the synchronizer is fed into the dual core. Although the dual cores receive the same synchronous signal, when the synchronizer fails and outputs an error signal, the dual cores receive the same error signal, and the output result of the dual cores is the same, so that the failure of the synchronizer cannot be found.
Disclosure of Invention
An object of embodiments of the present invention is to provide a method and an apparatus for synchronizing an asynchronous input signal, so as to at least solve the problem that a synchronizer failure cannot be found in the above-mentioned method for synchronously processing the asynchronous input signal.
In order to achieve the above object, a first aspect of the present invention provides a synchronization method for asynchronous input signals, which is used for a dual-core lockstep system, where the dual-core lockstep system includes a first core and a second core, and the method includes: inputting an asynchronous input signal into a first synchronizer and a second synchronizer simultaneously, wherein the first synchronizer is the same as the second synchronizer; and checking the output signal of the first synchronizer and the output signal of the second synchronizer.
Further, the method further comprises: inputting an output signal of the first synchronizer to the first core and the second core simultaneously; and checking the output signal of the first core and the output signal of the second core.
Further, the verifying the output signal of the first synchronizer and the output signal of the second synchronizer includes: judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not; and generating a warning signal under the condition that the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer.
Further, the verifying the output signal of the first synchronizer and the output signal of the second synchronizer includes: judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not; and generating a warning signal under the conditions that the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer, and the state duration time of the output signal of the first synchronizer is not equal to or longer than the preset threshold time.
Further, the verifying the output signal of the first synchronizer and the output signal of the second synchronizer further includes: and generating a synchronizer check signal according to the warning signal.
Further, the method further comprises: and continuously inputting the synchronizer checking signal into a chip.
Further, the verifying the output signal of the first core and the output signal of the second core includes: and comparing the output signal of the first kernel with the output signal of the second kernel, and generating a check signal according to the comparison result.
Further, the method further comprises: continuously inputting the check signal into a chip
A second aspect of the present invention provides a synchronization apparatus for asynchronous input signals, which is used in a dual-core lockstep system, where the dual-core lockstep system includes a first core and a second core, and the apparatus includes:
the first synchronizer is used for synchronizing the input asynchronous input signals and outputting signals to the first kernel, the second kernel and the synchronous detection module;
the second synchronizer is used for synchronizing the input asynchronous input signal and outputting a signal to the synchronous detection module;
the synchronous detection module is used for verifying the output signal of the first synchronizer and the output signal of the second synchronizer;
wherein the first synchronizer is the same as the second synchronizer.
Further, the apparatus further comprises: and the checking module is used for checking the output signal of the first core and the output signal of the second core.
Further, the synchronization detection module includes: the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not; and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer.
Further, the synchronization detection module includes: the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not; and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer and the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer are different is greater than or equal to a preset threshold time.
Further, the synchronization detection module further includes: and the verification generating module is used for generating a synchronizer verification signal according to the warning signal.
Further, the check generating module is further configured to continuously input the synchronizer check signal to a chip.
Further, the verifying the output signal of the first core and the output signal of the second core includes: and the checking module compares the output signal of the first kernel with the output signal of the second kernel and generates a checking signal according to the comparison result.
Further, the check module is also used for continuously inputting the check signal into the chip.
A third aspect of the present invention provides a central processing unit, including a first core and a second core, the central processing unit further including:
the first synchronizer is used for synchronizing the input asynchronous input signals and outputting signals to the first kernel, the second kernel and the synchronous detection module;
the second synchronizer is used for synchronizing the input asynchronous input signal and outputting a signal to the synchronous detection module;
the synchronous detection module is used for verifying the output signal of the first synchronizer and the output signal of the second synchronizer;
wherein the first synchronizer is the same as the second synchronizer.
Further, the central processing unit further includes: and the checking module is used for checking the output signal of the first core and the output signal of the second core.
Further, the synchronization detection module includes: the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not; and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer.
Further, the synchronization detection module includes: the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not; and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer and the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer are different is greater than or equal to a preset threshold time.
Further, the synchronization detection module further includes: and the verification generating module is used for generating a synchronizer verification signal according to the warning signal.
Further, the verifying the output signal of the first core and the output signal of the second core includes: and the checking module compares the output signal of the first kernel with the output signal of the second kernel and generates a checking signal according to the comparison result.
The invention also provides a chip, which comprises the asynchronous input signal synchronization device or the central processing unit.
According to the asynchronous input signal synchronization method, two synchronizers are adopted, the output signal of the first synchronizer is used as the input of the first kernel and the second kernel, the output signal of the second synchronizer is used as the comparison reference of the first synchronizer, the fault of any synchronizer can be captured according to the verification result information (namely synchronizer verification signals) of the first and second synchronizers, and the important point is that the fault of the first synchronizer providing the input signal for the two kernels can be found. In addition, the method of the invention detects the state duration time that the output signal of the first synchronizer is different from the output signal of the second synchronizer, and generates the warning signal under the condition that the state duration time exceeds the preset threshold time, thereby solving the problem of error warning caused by the misalignment of the output signals of the two same synchronizers.
In addition, the asynchronous input signal synchronization method of the embodiment of the invention adopts double verification to verify the output signals of the two synchronizers and simultaneously verify the output signals of the two kernels, thereby ensuring that the synchronizers or the kernels can be effectively perceived when problems occur, and further ensuring the safety and reliability of the dual-core lockstep system.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a block diagram of a conventional dual core lockstep central processing unit;
FIG. 2 is a flow chart of a method for synchronizing an asynchronous input signal according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for synchronizing an asynchronous input signal according to a second embodiment of the present invention;
FIG. 4 is a block diagram of a synchronization apparatus for asynchronous input signals provided by an embodiment of the present invention;
FIG. 5 is a block diagram of a synchronization detection module of a synchronization apparatus for asynchronous input signals provided by an embodiment of the present invention;
fig. 6 is a block diagram of a central processing unit according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a block diagram of a conventional dual core lockstep central processing unit. As shown in fig. 1, in the dual core lockstep design, another way to perform synchronous processing on asynchronous input signals is: the asynchronous input signals are sent to two synchronizers (a first synchronizer and a second synchronizer), and then the two synchronizers respectively send the synchronous signals output by the synchronizers to two cores (a first core and a second core). In this way, when any one of the two synchronizers fails, the synchronization signals output by the two synchronizers are inconsistent, that is, the input signals of the two cores are inconsistent, and finally the output signals of the two cores are inconsistent. The checking module detects whether the output signals of the two cores are consistent, if the output signals of the two cores are inconsistent, a checking signal representing an alarm can be generated, and the fault of the synchronizer can be found according to the checking signal representing the alarm. However, due to the circuit characteristics of the synchronizers, for the same asynchronous input signals, the output signals of two identical synchronizers may not be aligned, i.e. not pulled up or pulled down at the same time, which is normal and does not represent that the synchronizers fail, but this may cause the two cores to receive inconsistent input signals, and eventually generate an incorrect check signal (false alarm).
The present invention addresses the above-identified problems by providing an improved method of synchronizing asynchronous input signals.
Example one
Fig. 2 is a flowchart of a method for synchronizing an asynchronous input signal according to an embodiment of the present invention. The synchronization method of the asynchronous input signal of the embodiment is used for a dual-core step locking system, and the dual-core step locking system comprises a first core and a second core. As shown in fig. 2, the method comprises the steps of:
and S1, inputting the asynchronous input signal into a first synchronizer and a second synchronizer at the same time, wherein the first synchronizer is the same as the second synchronizer in structure, function and parameter.
And S2, verifying the output signal of the first synchronizer and the output signal of the second synchronizer.
Step S2 includes the following substeps:
and S21, judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer.
And S22, generating a warning signal when the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer.
Alternatively, step S2 includes the following substeps:
and S21, judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer.
And S22, generating a warning signal when the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer and the state duration time of the output signal of the first synchronizer is different from the state duration time of the output signal of the second synchronizer is larger than or equal to the preset threshold time. In the case where the output signal of the first synchronizer is the same as the output signal of the second synchronizer, a warning signal is not generated.
Due to the circuit characteristics of the synchronizers themselves, the output signals of two identical synchronizers may not be aligned for the same asynchronous input signal, and may differ by one clock cycle, but may not differ by two or more clock cycles. In a preferred embodiment, the preset threshold time is two clock cycles. And if the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer which are different is more than or equal to two clock cycles, indicating that one synchronizer is in failure, and generating a warning signal.
The method for synchronizing asynchronous input signals provided by this embodiment checks the output signal of the first synchronizer and the output signal of the second synchronizer, and further includes the following substeps:
and S23, generating a synchronizer check signal according to the warning signal.
Specifically, the warning signal is stored, a synchronizer check signal is generated according to the warning signal, and the synchronizer check signal is continuously transmitted to the outside (for example, a soc (system on chip).
In the method for synchronizing asynchronous input signals of the embodiment, two synchronizers are adopted, an output signal of the first synchronizer is used as an input of the first kernel and the second kernel, an output signal of the second synchronizer is used as a comparison reference of the first synchronizer, a fault occurring in any one synchronizer can be captured according to verification result information (namely synchronizer verification signals) of the first and second synchronizers, and importantly, the fault of the first synchronizer providing the input signal for the two kernels can be found. In addition, the method generates the warning signal under the condition that the state duration time exceeds the preset threshold time by detecting the state duration time that the output signals of the first synchronizer and the second synchronizer are different, and solves the problem of error warning caused by the fact that the output signals of the two same synchronizers are not aligned.
Example two
Fig. 3 is a flowchart of a synchronization method for asynchronous input signals according to a second embodiment of the present invention. The synchronization method of the asynchronous input signal of the embodiment is used for a dual-core step locking system, and the dual-core step locking system comprises a first core and a second core. As shown in fig. 3, the method comprises the steps of:
and S1, inputting the asynchronous input signal into a first synchronizer and a second synchronizer at the same time, wherein the first synchronizer is the same as the second synchronizer in structure, function and parameter.
And S2, verifying the output signal of the first synchronizer and the output signal of the second synchronizer.
Step S2 includes the following substeps:
and S21, judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer.
And S22, generating a warning signal when the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer.
Alternatively, step S2 includes the following substeps:
and S21, judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer.
And S22, generating a warning signal when the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer and the state duration time of the output signal of the first synchronizer is different from the state duration time of the output signal of the second synchronizer is larger than or equal to the preset threshold time. In the case where the output signal of the first synchronizer is the same as the output signal of the second synchronizer, a warning signal is not generated.
Due to the circuit characteristics of the synchronizers themselves, the output signals of two identical synchronizers may not be aligned for the same asynchronous input signal, and may differ by one clock cycle, but may not differ by two or more clock cycles. In a preferred embodiment, the preset threshold time is two clock cycles. And if the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer which are different is more than or equal to two clock cycles, indicating that one synchronizer is in failure, and generating a warning signal.
And S23, generating a synchronizer check signal according to the warning signal.
Specifically, the warning signal is saved, a synchronizer check signal is generated according to the warning signal, and the synchronizer check signal is continuously transmitted to the outside (for example, an SoC chip).
The method for synchronizing asynchronous input signals provided by the embodiment further comprises the following steps:
s3, inputting the output signal of the first synchronizer to the first core and the second core simultaneously, and checking the output signal of the first core and the output signal of the second core.
Specifically, the output signal of the first core is compared with the output signal of the second core, a check signal is generated according to the comparison result, and the check signal is sent to the outside (for example, an SoC chip). For example, the output signal of the first core is the same as the output signal of the second core, and a "0" signal is transmitted, and the output signal of the first core is different from the output signal of the second core, and a "1" signal is transmitted.
In the method for synchronizing asynchronous input signals of the embodiment, two synchronizers are adopted, an output signal of the first synchronizer is used as an input of the first kernel and the second kernel, an output signal of the second synchronizer is used as a comparison reference of the first synchronizer, a fault occurring in any one synchronizer can be captured according to verification result information (namely synchronizer verification signals) of the first and second synchronizers, and importantly, the fault of the first synchronizer providing the input signal for the two kernels can be found. Furthermore, the method of the invention detects the state duration time that the output signal of the first synchronizer is different from the output signal of the second synchronizer, and generates the warning signal under the condition that the state duration time exceeds the preset threshold time, thereby solving the problem of error warning caused by the misalignment of the output signals of the two same synchronizers.
In addition, the asynchronous input signal synchronization method of the embodiment adopts double verification to verify the output signals of the two synchronizers and simultaneously verify the output signals of the two kernels, so that the synchronizers or the kernels can be effectively perceived when problems occur, and the safety and the reliability of the dual-core lockstep system are further ensured.
Fig. 4 is a block diagram of a synchronization apparatus for asynchronous input signals according to an embodiment of the present invention. As shown in fig. 4, the synchronization apparatus of asynchronous input signals according to the embodiment of the present invention is used in a dual-core lockstep system, where the dual-core lockstep system includes a first core and a second core, the apparatus includes a first synchronizer, a second synchronizer, a synchronous detection module, and a verification module, and the first synchronizer is the same as the second synchronizer. The first synchronizer is used for synchronizing the input asynchronous input signals and outputting signals to the first kernel, the second kernel and the synchronous detection module. The second synchronizer is used for synchronizing the input asynchronous input signal and outputting the signal to the synchronous detection module. The synchronous detection module is used for verifying the output signal of the first synchronizer and the output signal of the second synchronizer. The verification module is configured to verify an output signal of the first core and an output signal of the second core, and specifically, compare the output signal of the first core with the output signal of the second core, generate a verification signal according to a comparison result, and send the verification signal to an external device (e.g., an SoC chip).
Fig. 5 is a block diagram of a synchronization detection module of a synchronization apparatus for asynchronous input signals according to an embodiment of the present invention. As shown in fig. 5, the synchronization detection module includes a comparison module, a signal width detection module, and a check generation module. The comparison module is used for comparing and judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer. The signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer. In a specific embodiment, the signal width detection module is configured to generate a warning signal when the comparison module determines that the output signal of the first synchronizer is different from the output signal of the second synchronizer, and a state duration time when the output signal of the first synchronizer is different from the output signal of the second synchronizer is greater than or equal to a preset threshold time. Preferably, the preset threshold time is two clock cycles. And if the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer which are different is more than or equal to two clock cycles, indicating that one synchronizer is in failure, and generating a warning signal. The verification generation module is configured to generate a synchronizer verification signal according to the warning signal, specifically, store the warning signal, generate the synchronizer verification signal according to the warning signal, and continuously send the synchronizer verification signal to an external (e.g., soc (system on chip)) chip.
The asynchronous input signal synchronization device adopts two synchronizers, the output signal of the first synchronizer is used as the input of a first kernel and a second kernel, the output signal of the second synchronizer is used as the comparison reference of the first synchronizer, the output signals of the two synchronizers are verified through a synchronous detection module, the fault of any one synchronizer can be captured according to the verification result information (namely synchronizer verification signal) of the two synchronizers, and the fault of the first synchronizer providing the input signal for the two kernels can be found. Furthermore, the output signals of the first synchronizer and the second synchronizer are detected by the synchronous detection module to generate the warning signal under the condition that the state duration time exceeds the preset threshold time, so that the problem of error warning caused by the fact that the output signals of the two same synchronizers are not aligned is solved.
In addition, the asynchronous input signal synchronization device adopts double verification to verify the output signals of the two synchronizers and simultaneously verify the output signals of the two kernels, so that the synchronizers or the kernels can be effectively perceived when problems occur, and the safety and the reliability of a dual-core lockstep system are further guaranteed. Moreover, it can be determined which synchronizer fails through double checking of the synchronization detection module and the check module, for example, if the synchronization detection module issues an alarm and the check module also issues an alarm, it is determined that the first synchronizer fails; and if the synchronous detection module sends out the warning but the verification module does not send out the warning, determining that the second synchronizer has a fault.
Fig. 6 is a block diagram of a central processing unit according to an embodiment of the present invention. As shown in fig. 6, the central processing unit according to the embodiment of the present invention includes a first core, a second core, a first synchronizer, a second synchronizer, a synchronization detection module, and a verification module, where the first synchronizer is the same as the second synchronizer. The first synchronizer is used for synchronizing the input asynchronous input signals and outputting signals to the first kernel, the second kernel and the synchronous detection module. The second synchronizer is used for synchronizing the input asynchronous input signal and outputting the signal to the synchronous detection module. The synchronous detection module is used for verifying the output signal of the first synchronizer and the output signal of the second synchronizer. The verification module is configured to verify an output signal of the first core and an output signal of the second core, and specifically, compare the output signal of the first core with the output signal of the second core, generate a verification signal according to a comparison result, and send the verification signal to an external device (e.g., an SoC chip).
The synchronous detection module comprises a comparison module, a signal width detection module and a check generation module. The comparison module is used for comparing and judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer. The signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer. In a specific embodiment, the signal width detection module is configured to generate a warning signal when the comparison module determines that the output signal of the first synchronizer is different from the output signal of the second synchronizer, and a state duration time when the output signal of the first synchronizer is different from the output signal of the second synchronizer is greater than or equal to a preset threshold time. Preferably, the preset threshold time is two clock cycles. And if the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer which are different is more than or equal to two clock cycles, indicating that one synchronizer is in failure, and generating a warning signal. The verification generation module is configured to generate a synchronizer verification signal according to the warning signal, specifically, store the warning signal, generate the synchronizer verification signal according to the warning signal, and continuously send the synchronizer verification signal to an external device (e.g., an SoC chip).
The embodiment of the invention also provides a chip, which comprises the synchronous device of the asynchronous input signal, or comprises the central processing unit.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, systems and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (20)
1. A synchronization method of asynchronous input signals is used for a dual-core lockstep system, the dual-core lockstep system comprises a first core and a second core, and the method comprises the following steps:
inputting an asynchronous input signal into a first synchronizer and a second synchronizer simultaneously, wherein the first synchronizer is the same as the second synchronizer;
verifying an output signal of the first synchronizer and an output signal of the second synchronizer;
the method further comprises the following steps:
inputting an output signal of the first synchronizer to the first core and the second core simultaneously;
and checking the output signal of the first core and the output signal of the second core.
2. The method for synchronizing asynchronous input signals according to claim 1, wherein said verifying the output signal of the first synchronizer and the output signal of the second synchronizer comprises:
judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not;
and generating a warning signal under the condition that the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer.
3. The method for synchronizing asynchronous input signals according to claim 1, wherein said verifying the output signal of the first synchronizer and the output signal of the second synchronizer comprises:
judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not;
and generating a warning signal under the conditions that the output signal of the first synchronizer is judged to be different from the output signal of the second synchronizer, and the state duration time of the output signal of the first synchronizer is not equal to or longer than the preset threshold time.
4. The method for synchronizing asynchronous input signals according to claim 2 or 3, wherein said checking the output signal of the first synchronizer and the output signal of the second synchronizer further comprises:
and generating a synchronizer check signal according to the warning signal.
5. The method for synchronizing asynchronous input signals according to claim 4, characterized in that said method further comprises:
and continuously inputting the synchronizer checking signal into a chip.
6. The method for synchronizing asynchronous input signals according to claim 1, wherein said checking the output signals of the first core and the second core comprises:
and comparing the output signal of the first kernel with the output signal of the second kernel, and generating a check signal according to the comparison result.
7. The method for synchronizing asynchronous input signals according to claim 6, said method further comprising:
and continuously inputting the verification signal into the chip.
8. A synchronization apparatus of asynchronous input signals for a dual core lockstep system, the dual core lockstep system including a first core and a second core, the apparatus comprising:
the first synchronizer is used for synchronizing the input asynchronous input signals and outputting signals to the first kernel, the second kernel and the synchronous detection module;
the second synchronizer is used for synchronizing the input asynchronous input signal and outputting a signal to the synchronous detection module;
the synchronous detection module is used for verifying the output signal of the first synchronizer and the output signal of the second synchronizer;
wherein the first synchronizer is the same as the second synchronizer;
the device further comprises:
and the checking module is used for checking the output signal of the first core and the output signal of the second core.
9. The apparatus for synchronizing asynchronous input signals according to claim 8, wherein said synchronization detection module comprises:
the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not;
and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer.
10. The apparatus for synchronizing asynchronous input signals according to claim 9, wherein said synchronization detection module comprises:
the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not;
and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer and the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer are different is greater than or equal to a preset threshold time.
11. The apparatus for synchronizing asynchronous input signals according to claim 9 or 10, wherein said synchronization detection module further comprises:
and the verification generating module is used for generating a synchronizer verification signal according to the warning signal.
12. The apparatus for synchronizing asynchronous input signals according to claim 11, wherein said verification generation module is further configured to continuously input said synchronizer verification signal to a chip.
13. The apparatus for synchronizing asynchronous input signals according to claim 8, wherein said verifying the output signal of the first core and the output signal of the second core comprises:
and the checking module compares the output signal of the first kernel with the output signal of the second kernel and generates a checking signal according to the comparison result.
14. The apparatus for synchronizing asynchronous input signals according to claim 13, wherein said check module is further configured to continuously input said check signal to a chip.
15. A central processing unit comprising a first core and a second core, the central processing unit further comprising:
the first synchronizer is used for synchronizing the input asynchronous input signals and outputting signals to the first kernel, the second kernel and the synchronous detection module;
the second synchronizer is used for synchronizing the input asynchronous input signal and outputting a signal to the synchronous detection module;
the synchronous detection module is used for verifying the output signal of the first synchronizer and the output signal of the second synchronizer;
wherein the first synchronizer is the same as the second synchronizer;
the central processing unit further comprises:
and the checking module is used for checking the output signal of the first core and the output signal of the second core.
16. The cpu of claim 15, wherein the synchronization detection module comprises:
the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not;
and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer.
17. The cpu of claim 15, wherein the synchronization detection module comprises:
the comparison module is used for judging whether the output signal of the first synchronizer is the same as the output signal of the second synchronizer or not;
and the signal width detection module is used for generating a warning signal under the condition that the comparison module judges that the output signal of the first synchronizer is different from the output signal of the second synchronizer and the state duration time of the output signal of the first synchronizer and the state duration time of the output signal of the second synchronizer are different is greater than or equal to a preset threshold time.
18. The cpu of claim 16 or 17, wherein the synchronization detection module further comprises:
and the verification generating module is used for generating a synchronizer verification signal according to the warning signal.
19. The cpu of claim 15, wherein said verifying the output signal of the first core and the output signal of the second core comprises:
and the checking module compares the output signal of the first kernel with the output signal of the second kernel and generates a checking signal according to the comparison result.
20. A chip comprising a synchronization device for asynchronous input signals according to any of claims 8 to 14 or comprising a central processor according to any of claims 15 to 19.
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