JPH03136395A - Insulating board using wiring circuit - Google Patents

Insulating board using wiring circuit

Info

Publication number
JPH03136395A
JPH03136395A JP27568389A JP27568389A JPH03136395A JP H03136395 A JPH03136395 A JP H03136395A JP 27568389 A JP27568389 A JP 27568389A JP 27568389 A JP27568389 A JP 27568389A JP H03136395 A JPH03136395 A JP H03136395A
Authority
JP
Japan
Prior art keywords
conductor
dimensionally
substrate
conductor circuits
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27568389A
Other languages
Japanese (ja)
Other versions
JP2863219B2 (en
Inventor
Toshiichi Takenouchi
竹之内 敏一
Fumio Miyagawa
文雄 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP1275683A priority Critical patent/JP2863219B2/en
Publication of JPH03136395A publication Critical patent/JPH03136395A/en
Application granted granted Critical
Publication of JP2863219B2 publication Critical patent/JP2863219B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To easily and rapidly form an insulating board of one or more layer structure without labor and facility cost by providing viaholes or through holes of conductors for connecting between crossing conductor circuits on sections in which the conductor circuits, of the board are stereoscopically crossed. CONSTITUTION:Latticelike conductor circuits 20 of front and rear surfaces of a board 10a are formed in the same size of the same shape, stereoscopically crossed, and stereoscopically superposed. Viaholes 30 are provided at every other one through the board 10a at sections in which the circuits 20 of the front and rear surfaces of the board 10a are stereoscopically crossed, and the circuits 20 are connected at every other ones therebetween by the viaholes 30. Holes 40 are so provided at sections having no viaholes 30 of the sections in which the circuits 20 of the front and rear surfaces of the board 10a are stereoscopically crossed, i.e., at every other ones in the sections in which the circuits 20 are stereoscopically crossed through the board 10a.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、絶縁基板に備えた導体回路や導体であるヴィ
アフィルまたはスルーホールや絶縁体であるホールを用
いて、その絶縁基板に各種の配線回路を自在に形成でき
る、配線回路を持つ絶縁基板に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses a conductor circuit, a conductor via fill or a through hole, or an insulator hole provided on an insulating substrate, and various types of The present invention relates to an insulating substrate having a wiring circuit, on which a wiring circuit can be freely formed.

[従来の技術] 電子部品実装用の絶縁基板として、セラミ、り基板やプ
ラスチック基板などがある。
[Prior Art] Examples of insulating substrates for mounting electronic components include ceramic substrates, resin substrates, and plastic substrates.

2この絶縁基板のうち、配線回路を持つ多層構造のセラ
ミック基板は、次のようにして、形成している。
2 Among these insulating substrates, a multilayered ceramic substrate having a wiring circuit is formed as follows.

グリーンシートを所定形状に裁断して、そのグリーンシ
ート表面にタングステン粉末などを混入した配線回路形
成用の導体ペーストを印刷したり、そのグリーンシート
表面につ゛イアホールを穿設して、そのダイアホールに
上記導体ページストを充填したヴィアフィルを印刷した
りする。次に、そのグリーンシートを複数枚積層して、
炉内に入れて焼成し、セラミ、り基板を形成すると同時
に、その基板に配線回路を形成している。
A green sheet is cut into a predetermined shape, and a conductive paste for forming a wiring circuit mixed with tungsten powder is printed on the surface of the green sheet, or a hole is drilled in the surface of the green sheet, and a hole is inserted into the hole. A via fill filled with the above-mentioned conductor pagest is printed. Next, stack multiple green sheets,
It is placed in a furnace and fired to form a ceramic substrate, and at the same time, a wiring circuit is formed on the substrate.

ところで、上記多層構造のセラミ、り基板に、特定の配
線回路を形成する場合は、従来は、その形成しようとす
る配線回路に合わせて、グリーンシート表面などに上記
導体ペーストを印刷するための特殊のプリントマスクを
形成したり、グリーンシート表面に上記グイアワイル形
成用のつ゛イアホールを穿設するための特殊の金型など
を形成したりしている。
By the way, when forming a specific wiring circuit on the above-mentioned multilayered ceramic substrate, conventionally, a special method was used to print the above-mentioned conductive paste on the surface of a green sheet, etc., in accordance with the wiring circuit to be formed. A print mask is formed, and a special mold is formed on the surface of the green sheet to form the wire hole for forming the wire wire.

[発明が解決しようとする課題1 しかしながら、セラミック基板に特定の配線回路を形成
する場合に、それに合わせて、特殊のプリントマスクや
金型などを形成することは、多大な手数と時間を要し、
その製造コストを大幅にアップさせていた。このことは
特に、近時の多種少量生産向きのセラミック基板におい
て著かった。
[Problem to be Solved by the Invention 1] However, when forming a specific wiring circuit on a ceramic substrate, it takes a lot of effort and time to form a special print mask, mold, etc. ,
This significantly increased manufacturing costs. This is particularly noticeable in recent ceramic substrates that are suitable for high-mix, low-volume production.

またこのことは、1層構造のセラミック基板や1層また
は多層構造のプラスチック基板などにおいても同様であ
った。
This also applies to ceramic substrates with a single layer structure, plastic substrates with a single layer or multilayer structure, and the like.

本発明は、このような課題を解消した、絶縁基板を提供
することを目的としている。
An object of the present invention is to provide an insulating substrate that solves these problems.

[課題を解決するための手段] 上記目的のために、本発明の第1の絶縁基板は、絶縁基
板の表裏面に、連続する導体回路または中途部を分断し
た導体回路を、その絶縁基板表裏面の導体回路が立体的
に交差するように、またはその絶縁基板表裏面の導体回
路の少なくとも一部が立体的に重なり合うように、備え
るとともに、その絶縁基板の前記導体回路が立体的に交
差する部分または立体的に重なり合う部分に、その交差
する導体回路間または重なり合う導体回路間を接続する
導体であるグイアフィルまたはスルーホール、または貫
通穴状または盲穴状をした絶縁体であるホールを備えて
なることを特徴としている。
[Means for Solving the Problems] For the above purpose, the first insulating substrate of the present invention has a continuous conductor circuit or a conductor circuit cut in the middle on the front and back surfaces of the insulating substrate. Provided so that the conductor circuits on the back surface intersect three-dimensionally, or so that at least a portion of the conductor circuits on the front and back surfaces of the insulating substrate overlap three-dimensionally, and the conductor circuits of the insulating substrate intersect three-dimensionally. A part or three-dimensionally overlapping part is provided with a guiafil or through hole, which is a conductor that connects the intersecting conductor circuits or between the overlapping conductor circuits, or a hole, which is an insulator in the shape of a through hole or a blind hole. It is characterized by

また、本発明の第2の絶縁基板は、多層構造の絶縁基板
の複数の層部材表面に、連続する導体回路または中途部
を分断した導体回路を、その絶縁基板の複数の層部材表
面の導体回路が立体的に交差するように、またはその絶
縁基板の複数の層部材表面の導体回路の少なくとも一部
が立体的に重なり合うように、備えるとともに、その絶
縁基板の前記導体回路が立体的に交差する部分または立
体的に重なり合う部分に、その交差する導体回路間また
は重なり合う導体回路間を接続する導体であるグイアフ
ィルまたはスルーホール、または貫通穴状または盲穴状
をした絶縁体であるホールを備えてなることを特徴とし
ている。
Further, the second insulating substrate of the present invention includes a continuous conductor circuit or a conductor circuit cut in the middle on the surface of the plurality of layer members of the insulating substrate with a multilayer structure. It is provided so that the circuits intersect three-dimensionally, or so that at least a portion of the conductor circuits on the surfaces of the plurality of layer members of the insulating substrate overlap three-dimensionally, and the conductor circuits of the insulating substrate intersect three-dimensionally. A guiafil or through hole, which is a conductor that connects the intersecting conductor circuits or overlapping conductor circuits, or a hole, which is an insulator in the form of a through hole or a blind hole, is provided in the part or the part that overlaps three-dimensionally. It is characterized by becoming.

さらに、上記第1、第2の本発明の絶縁基板においては
、絶縁基板の表裏面、または多層構造の絶縁基板の複数
の層部材表面に、導体回路を複数本格子状に備えること
好適としている。
Furthermore, in the insulated substrates of the first and second aspects of the present invention, it is preferable to provide a plurality of conductor circuits in a lattice shape on the front and back surfaces of the insulated substrate or on the surfaces of a plurality of layer members of an insulated substrate having a multilayer structure. .

「作用] 前記構成の第1の絶縁基板においては、絶縁基板表裏面
の連続する所定部位の導体回路中途部を、エツチングな
どにより、分断したり、または絶縁基板表裏面の分断し
た状態にある所定部位の導体回路中途部を、はんだなど
により、接続したり、または絶縁基板の所定部位のホー
ルにはんだ等の導体または導体と絶縁粉等の絶縁体とを
層状に充填して、絶縁基板表裏面の所定部位の立体的に
交差する導体回路間または立体的に重なり合う導体回路
間を接続したり、絶縁基板表裏面またはそのいずれか一
方の面のホールで分断した状態にある所定部位の導体回
路中途部を接続したり、または絶縁基板の所定部位にそ
の表面またはその裏面から、ドリルなどにより、貫通穴
または盲穴を穿設して、その貫通穴または盲穴で絶縁基
板表裏面またはそのいずれか一方の面の所定部位の導体
回路中途部を分断したり、さらにその穿設した所定部位
の貫通穴または盲穴に導体または導体と絶縁体とを層状
に充填して、絶縁基板表裏面の所定部位の立体的に交差
する導体回路間または立体的に重なり合う導体回路間を
接続したり、前記貫通穴または盲穴で分断した絶縁基板
表裏面またはそのいずれか一方の面の所定部位の導体回
路中途部を接続したりすることにより、絶縁基板の表裏
面に亙って特定の配線回路を立体的に形成できる。
"Function" In the first insulating substrate having the above configuration, the midway portion of the conductor circuit at a continuous predetermined portion on the front and back surfaces of the insulating substrate is separated by etching or the like, or a predetermined portion in a separated state on the front and back surfaces of the insulating substrate is separated. The middle part of the conductor circuit of the part is connected with solder, etc., or the hole in the predetermined part of the insulating board is filled with a conductor such as solder or a layer of a conductor and an insulator such as insulating powder, and the front and back surfaces of the insulating board are Connecting conductor circuits that intersect three-dimensionally or overlap conductor circuits three-dimensionally at a predetermined location, or midway through a conductor circuit at a predetermined location that is separated by a hole on the front and back surfaces of an insulating substrate or on either side. or by drilling a through hole or a blind hole in a predetermined part of the insulating board from the front or back side of the insulating board using a drill etc. By cutting the conductor circuit midway at a predetermined location on one surface, and filling the through hole or blind hole at the predetermined location with a conductor or a conductor and an insulator in a layered manner, Connecting conductor circuits that three-dimensionally intersect or three-dimensionally overlap conductor circuits at a location, or midway through a conductor circuit at a predetermined location on the front and back surfaces of an insulating substrate, or either surface separated by the through hole or blind hole. By connecting the parts, a specific wiring circuit can be three-dimensionally formed over the front and back surfaces of the insulating substrate.

前記構成の第2の絶縁基板においては、絶縁基板外側に
露出する層部材表面の連続する所定部位の導体回路中途
部を、エツチングなどにより、分断したり、または絶縁
基板外側に露出する層部材表面の分断した状態にある所
定部位の導体回路中途部を、はんだなどにより、接続し
たり、または絶縁基板の所定部位のホールに導体または
導体と絶縁体とを層状に充填して、絶縁基板の複数の層
部材表面の所定部位の立体的に交差する導体回路間また
は立体的に重なり合う導体回路間を接続したり、絶縁基
板の層部材表面のホールで分断した状態にある所定部位
の導体回路中途部を接続したり、または絶縁基板の所定
部位にその表面またはその裏面から貫通穴または盲穴を
穿設して、その貫通穴または盲穴で絶縁基板の層部材表
面の所定部位の連続する導体回路中途部を分断したり、
さらにその穿設した所定部位の貫通穴または盲穴に導体
または導体と絶縁体とを層状に充填して、絶縁基板の複
数の層部材表面の所定部位の立体的に交差する導体回路
間または立体的に重なり合う導体回路間を接続したり、
前記貫通穴または盲穴で分断した絶縁基板の層部材表面
の所定部位の導体回路中途部を接続したりすることによ
り、絶縁基板の複数の層部材表面に亙って特定の配線回
路を立体的に形成できる。
In the second insulating substrate having the above structure, the midway portion of the conductor circuit at a continuous predetermined portion of the surface of the layer member exposed to the outside of the insulating substrate is separated by etching or the like, or the surface of the layer member exposed to the outside of the insulating substrate is separated. Connect the middle parts of the conductor circuits at predetermined parts of the insulating board, which are in a separated state, by soldering or the like, or fill the holes in the predetermined parts of the insulating board with a conductor or a layer of conductors and insulators to connect multiple parts of the insulating board. Connecting conductor circuits that three-dimensionally intersect or three-dimensionally overlap at a predetermined location on the surface of a layer member, or midway through a conductor circuit at a predetermined location separated by a hole on the surface of a layer member of an insulating substrate. or by drilling a through hole or a blind hole in a predetermined part of the insulating substrate from the front or back side thereof, and using the through hole or blind hole to connect a continuous conductor circuit in a predetermined part of the surface of the layer member of the insulating board. Divide the middle part,
Furthermore, the conductor or the conductor and the insulator are filled in layers in the through holes or blind holes in the predetermined portions of the insulating substrate, and conductor circuits or three-dimensional Connecting overlapping conductor circuits,
By connecting the midway portions of the conductor circuits at predetermined locations on the surface of the layer members of the insulating substrate separated by the through holes or blind holes, a specific wiring circuit can be formed three-dimensionally over the surfaces of multiple layer members of the insulating substrate. can be formed into

[実施例] 次に、本発明の実施例を図面に従い説明する。[Example] Next, embodiments of the present invention will be described with reference to the drawings.

第1図ないし第5図は本発明の第1の絶縁基板の好適な
実施例を示し、第1図はその斜視図、第2図はその使用
状態を示す斜視図、第3図はその使用状態を示す平面図
、第4図は第3図のA−A断面図、第5図は第3図のB
−B断面図である。
1 to 5 show preferred embodiments of the first insulating substrate of the present invention, FIG. 1 is a perspective view thereof, FIG. 2 is a perspective view showing its use, and FIG. 3 is a perspective view showing its use. A plan view showing the state, Fig. 4 is a sectional view taken along line A-A in Fig. 3, and Fig. 5 is a sectional view taken along line B in Fig. 3.
-B sectional view.

以下、これらの図中の実施例を説明する。The embodiments shown in these figures will be described below.

図において、1−Oaは、1層構造のセラミック基板で
ある。
In the figure, 1-Oa is a ceramic substrate with a single layer structure.

20は、タングステンメタライズ等からなる連続する帯
状の導体回路である。
20 is a continuous band-shaped conductor circuit made of tungsten metallization or the like.

この導体回路20を、上記基板10a表面とその裏面と
に、縦横に複数本格子状に並べて備えている。また、基
板103表裏面の格子状の導体回路20を同一形状をし
た同一大きさに形成していて、基板108表裏面の導体
回路20が、立体的に交差するとともに、立体的に重な
り合うようにしている。
A plurality of conductor circuits 20 are arranged in a lattice pattern vertically and horizontally on the front and back surfaces of the substrate 10a. Further, the grid-like conductor circuits 20 on the front and back surfaces of the substrate 103 are formed to have the same shape and the same size, and the conductor circuits 20 on the front and back surfaces of the substrate 108 intersect three-dimensionally and overlap three-dimensionally. ing.

30は、タングステンメタライズ等の導体を充填した導
体であるつ゛イアフィルである。このヴィアフィル30
を、前記基板tOa表裏面の格子状の導体回路20が立
体的に交差する部分に一つおきごとに基板tOaを貫通
させて備えていて、その立体的に交差する導体回路20
間を一つおきごとに上記ヴィアフィル30で接続してい
る。
Reference numeral 30 denotes a wire fill, which is a conductor filled with a conductor such as tungsten metallized material. This viafil 30
The substrate tOa is penetrated every other part where the lattice-shaped conductor circuits 20 on the front and back surfaces of the substrate tOa intersect three-dimensionally, and the conductor circuits 20 intersect three-dimensionally.
Every other gap is connected by the via fill 30.

40は、上記導体回路20の幅より小径な貫通穴状をし
た絶縁体であるホールである。このホール40を、基板
10a表裏面の格子状の導体回路20が立体的に交差す
る部分のうちの、上記ヴィアフィル30を備えていない
部分に、即ち上記格子状の導体回路20が立体的に交差
する部分の一つおきごとに、基板tOaを貫通させて備
えている。
Reference numeral 40 denotes a hole which is an insulator and has a through-hole shape smaller in diameter than the width of the conductor circuit 20. This hole 40 is placed in a portion where the via fill 30 is not provided among the portions where the lattice-shaped conductor circuits 20 intersect in three dimensions on the front and back surfaces of the substrate 10a. A substrate tOa is provided to pass through every other intersection.

第1図に示したは絶縁基板は、以上のように構成してい
て、第2図や第3図に示したように、基板10a表裏面
の連続する所定部位の導体回路中途部20bを、エツチ
ングなどにより、分断したり、第4図に示したように、
基板10aの所定部位のホール40に導体50を充填し
て、基板10a表裏面の所定部位の立体的に交差する導
体回路20間を接続したり、第4図や第5図に示したよ
うに、基板10aの所定部位にその表面または裏面から
、ドリルなどにより、導体回路20の幅より大径または
小径の貫通穴60または盲穴70を穿設して、基板10
8表裏面またはそのいずれか一方の面の所定部位の導体
回路20中途部を上記貫通穴60または盲穴70で分断
したり、第5図に示したように、さらにその穿設した所
定部位の貫通穴60または盲穴70に導体50または導
体50と絶縁体80とを層状に充填して、基板10a表
裏面の所定部位の立体的に交差する導体回路20間また
は立体的に重なり合う導体回路20間を接続したり、上
記貫通穴60または盲穴70で分断した基板10a表裏
面またはそのいずれか一方の面の所定部位の導体回路2
0中途部を接続したりすることにより、基板10aの表
裏面に亙って、特定の配線回路を立体的に形成できる。
The insulating substrate shown in FIG. 1 is constructed as described above, and as shown in FIG. 2 and FIG. It can be separated by etching, etc., or as shown in Figure 4.
Holes 40 at predetermined locations on the substrate 10a are filled with conductors 50 to connect conductor circuits 20 intersecting three-dimensionally at predetermined locations on the front and back surfaces of the substrate 10a, or as shown in FIGS. 4 and 5. , a through hole 60 or a blind hole 70 having a diameter larger or smaller than the width of the conductor circuit 20 is drilled at a predetermined portion of the board 10a from the front or back surface thereof using a drill or the like.
8. The middle part of the conductor circuit 20 at a predetermined portion on the front and back surfaces or one of the surfaces is divided by the through hole 60 or the blind hole 70, or as shown in FIG. The through hole 60 or the blind hole 70 is filled with the conductor 50 or the conductor 50 and the insulator 80 in a layered manner so that the conductor circuits 20 intersect three-dimensionally or the conductor circuits 20 overlap three-dimensionally at predetermined portions on the front and back surfaces of the substrate 10a. Conductor circuits 2 at predetermined locations on the front and back surfaces of the substrate 10a, or on either side of the substrate 10a, which are connected between or separated by the through hole 60 or the blind hole 70.
By connecting the middle portions of the substrate 10a, a specific wiring circuit can be three-dimensionally formed over the front and back surfaces of the substrate 10a.

第6図ないし第1O図は、本発明の第1の絶縁基板の他
の好適な実施例を示し、第6図はその斜視図、第7図は
その使用状態を示す斜視図、第8図はその使用状態を示
す平面図、第9図は第8図のC−C断面図、第10図は
第8図のD−D断面図である。以下、これらの図中の実
施例を一説明する。
6 to 1O show other preferred embodiments of the first insulating substrate of the present invention, FIG. 6 is a perspective view thereof, FIG. 7 is a perspective view showing its usage state, and FIG. 8 9 is a sectional view taken along the line CC in FIG. 8, and FIG. 10 is a sectional view taken along the line DD in FIG. 8. The embodiments shown in these figures will be explained below.

図の絶縁基板では、そのセラミツク基板10b表裏面の
格子状の導体回路20の各格子目四辺の導体回路中途部
20bを分断している。
In the illustrated insulating substrate, the middle portions 20b of the conductor circuits on the four sides of each grid of the grid-shaped conductor circuits 20 on the front and back surfaces of the ceramic substrate 10b are separated.

その他は、既述実施例の第1の絶縁基板と同様に構成し
ていて、第7図や第8図に示したように、基板10b表
裏面の分断した状態にある所定部位の導体回路中途部2
0bを、はんだ90などにより、接続したり、第9図に
示したように、基板IQbの所定部位のホール40に導
体50を充填して、基板10b表裏面の所定部位の立体
的に交差する導体回路20間を接続したり、第7図や第
8図や第9図に示したように、基板10bの所定部位に
その表面またはその裏面から導体回路20の幅より大径
または小径の貫通穴60または盲穴70を穿設して、そ
の貫通穴60または盲穴70で基板10b表裏面または
そのいずれか一方の面の所定部位の導体回路20中途部
を分断したり、第10図に示したように、さらにその穿
設した所定部位の貫通穴60または盲穴70に導体50
または導体50と絶縁体80とを層状に充填して、基板
10b表裏面の所定部位の立体的に交差する導体回路2
0間または立体的に重なり合う導体回路20間を接続し
たり、貫通穴60または盲穴70で分断した基板10b
表裏面またはそのいずれか一方の面の所定部位の導体回
路20中途部を接続したりすることにより、基板10b
の表裏面に亙って、特定の配線回路を立体的に形成でき
る。
The rest of the structure is the same as that of the first insulating substrate of the previously described embodiment, and as shown in FIGS. Part 2
0b with solder 90 or the like, or as shown in FIG. 9, conductors 50 are filled in holes 40 at predetermined portions of the substrate IQb so as to intersect three-dimensionally at predetermined portions on the front and back surfaces of the substrate 10b. To connect between the conductor circuits 20, or as shown in FIG. 7, FIG. 8, or FIG. A hole 60 or a blind hole 70 is drilled, and the conductor circuit 20 at a predetermined portion on the front and back surfaces of the substrate 10b or one of the surfaces is separated by the through hole 60 or the blind hole 70, as shown in FIG. As shown, the conductor 50 is further inserted into the through hole 60 or the blind hole 70 at the predetermined location.
Alternatively, the conductor circuit 2 is filled with a conductor 50 and an insulator 80 in a layered manner and intersects three-dimensionally at a predetermined portion on the front and back surfaces of the substrate 10b.
0 or between conductor circuits 20 that overlap three-dimensionally, or are separated by a through hole 60 or a blind hole 70.
The substrate 10b
A specific wiring circuit can be formed three-dimensionally over the front and back surfaces of the device.

なお、上述各実施例において、基板10a、10b表裏
面のいずれか一方の面に、連続する導体回路を格子状に
備えるとともに、その他方の面に中途部を分断した導体
回路を格子状に備えたり、または基板10a、10b表
裏面に、それぞれ連続する導体回路と中途部を分断した
導体回路とを組み合わせた導体回路を格子状に備えたり
して、基板10a、10b表裏面またはそのいずれか一
方の面の所定部位の連続する導体回路中途部を、エツチ
ングなどにより、分断したり、基板10a。
In each of the above-mentioned embodiments, one of the front and back surfaces of the substrates 10a and 10b is provided with a continuous conductor circuit in a grid pattern, and the other surface is provided with a conductor circuit with a part cut in the middle in a grid pattern. Alternatively, the front and back surfaces of the substrates 10a, 10b may be provided with conductor circuits in a lattice shape, each of which is a combination of a continuous conductor circuit and a conductor circuit that is cut in the middle. The intermediate portion of the continuous conductor circuit at a predetermined portion of the surface of the substrate 10a is divided by etching or the like.

10b表裏面またはそのいずれか一方の面の分断した状
態にある所定部位の導体回路中途部を、はんだなどによ
り、接続したりできるようにしても良い。
It may also be possible to connect intermediate portions of the conductor circuit at predetermined portions on the front and back surfaces of 10b or one of the surfaces with solder or the like.

第11図ないし第15図は本発明の第2の絶縁基板の好
適な実施例を示し、第11図はその分解斜視図、第12
図はその使用状態を示す平面図、第13図は第12図の
E−E断面図、第14図は第12図のF−F断面図、第
15図はその分解斜視図である。以下、これらの図中の
実施例を説明する。
11 to 15 show preferred embodiments of the second insulating substrate of the present invention, FIG. 11 is an exploded perspective view thereof, and FIG.
13 is a sectional view taken along line EE in FIG. 12, FIG. 14 is a sectional view taken along line FF in FIG. 12, and FIG. 15 is an exploded perspective view thereof. The embodiments shown in these figures will be described below.

図において、10cは、グリーンシートを複数枚積層し
て焼成してなる、多層構造(図では、3層構造としてい
る)のセラミック基板である。
In the figure, 10c is a ceramic substrate having a multilayer structure (in the figure, it has a three-layer structure) formed by laminating and firing a plurality of green sheets.

20は、タングステンメタライズ等からなる連続する帯
状の導体回路である。この導体回路20を、上記基板1
0Cを形成している各層部材100a、100b、10
0c表面に、縦横に複数本格子状に並べて形成している
。またそれとともに、上記各層部材表面の格子状の導体
回路20を、同一形状をした同一大きさに形成していて
、その各層部材100a、100b、1ooc表面の導
体回路20が、立体的に交差するとともに、立体的に重
なり合うようにしている。
20 is a continuous band-shaped conductor circuit made of tungsten metallization or the like. This conductive circuit 20 is connected to the substrate 1.
Each layer member 100a, 100b, 10 forming 0C
On the 0c surface, a plurality of them are arranged vertically and horizontally in a grid pattern. At the same time, the lattice-shaped conductor circuits 20 on the surface of each layer member are formed to have the same shape and size, and the conductor circuits 20 on the surface of each layer member 100a, 100b, 1ooc intersect three-dimensionally. At the same time, they are made to overlap three-dimensionally.

なお、第15図に示したように、基板10C外側に露出
する層部材100a表面の格子状の導体回路20は、そ
の各格子目四辺の導体回路中途部20bを、分断してお
いても良い。
Incidentally, as shown in FIG. 15, the lattice-shaped conductor circuit 20 on the surface of the layer member 100a exposed to the outside of the substrate 10C may be separated at the middle portions 20b of the conductor circuit on the four sides of each lattice. .

30は、タングステンメタライズ等の導体を充填したつ
゛イアフィルである。このグイアフイル30を、上記基
板10cの各層部材表面の導体回路20が立体的に交差
する部分の一つおきごとに、基板の各層部材100a、
1oob、100cを貫通させて備えている。そして、
基板IOCの各層部材表面の立体的に交差する導体回路
20間を一つおきごとに上記ダイアフイル30で接続し
ている。
30 is a wire fill filled with a conductor such as tungsten metallization. This Guia foil 30 is applied to every other part where the conductor circuits 20 on the surface of each layer member of the substrate 10c three-dimensionally intersect, each layer member 100a of the substrate,
100c and 100c are provided. and,
Every other conductor circuit 20 intersecting three-dimensionally on the surface of each layer member of the substrate IOC is connected by the diaphragm 30.

なお、第15図に示したように、上記グイアフィル30
を基板10cの一部の層部材+00bのみに貫通させて
備えて、基板10Cの一部の層部材100b、100c
表面の立体的に交差する導体回路20間または立体的に
重なり合う導体回路20間のみをつ゛イアフィル30で
接続するようにしても良い。
In addition, as shown in FIG. 15, the above-mentioned guiafil 30
is provided by penetrating only part of the layer members +00b of the substrate 10c, so that some of the layer members 100b, 100c of the board 10C are provided.
The wire fill 30 may be used to connect only between the conductor circuits 20 that three-dimensionally intersect on the surface or between the conductor circuits 20 that three-dimensionally overlap.

40は、導体回路20の幅より小径の貫通穴状をした絶
縁体であるホールである。このホール40を、上記ヴィ
アフィル30を備えていない基板10cの各層部材表面
の導体回路20が立体的に交差する部分の一つおきごと
に、基板の各層部材100a、IC)Ob、100cを
貫通させて備えている。
Reference numeral 40 denotes a hole which is an insulator and has a through-hole shape smaller in diameter than the width of the conductor circuit 20. This hole 40 is passed through each layer member 100a, IC) Ob, 100c of the board at every other place where the conductor circuits 20 on the surface of each layer member of the board 10c not provided with the via fill 30 intersect three-dimensionally. I'm ready.

第11図や第15図に示した絶縁基板は、以上のように
構成していて、第12図に示したように、基板10c外
側に露出する層部材100a表面の所定部位の導体回路
中途部20bを、エツチングなどにより、分断したり、
第15図に示したように、基板10c外側に露出する層
部材100a表面の分断した状態にある所定部位の導体
回路中途部20bを、はんだ90などにより、接続した
り、第13図や第14図に示したように、基板10cの
所定部位のホール40に導体50または導体50と絶縁
体80とを層状に充填して、基板10cの各層部材また
はその一部の層部材表面の所定部位の立体的に交差する
導体回路20間を接続したり、第12図や第13図や第
14図に示したように、基板10Cの所定部位にその表
面または裏面から導体回路20の幅より大径または小径
の貫通穴60または盲穴70を穿設して、その貫通穴6
0または盲穴70で基板10Cの各層部材またはその一
部の層部材表面の所定部位の導体回路20中途部を分断
したり、第14図に示したように、さらにその穿設した
所定部位の貫通穴60または盲穴7oに導体50または
導体50と絶縁体80とを層状に充填して、基板10c
の各層部材またはその一部の層部材表面の所定部位の立
体的に交差する導体回路20間または立体的に重なり合
う導体回路20間を接続したり、基板10Cの各層部材
またはその一部の層部材表面の上記貫通穴60または盲
穴70で分断した所定部位の導体回路20中途部を接続
したりすることにより、基板10Cの各層部材100a
、100b、100c表面に亙って、特定の配線回路を
立体的に形成できる。
The insulating substrates shown in FIGS. 11 and 15 are constructed as described above, and as shown in FIG. 20b by etching or the like,
As shown in FIG. 15, the midway portions 20b of the conductor circuit at predetermined portions of the surface of the layer member 100a exposed to the outside of the substrate 10c are connected with solder 90 or the like. As shown in the figure, a conductor 50 or a conductor 50 and an insulator 80 are filled in the holes 40 at a predetermined portion of the substrate 10c in a layered manner, and a predetermined portion of the surface of each layer member or a part of the layer member of the substrate 10c is filled. The conductor circuits 20 that intersect three-dimensionally can be connected, or as shown in FIGS. Or, by drilling a small diameter through hole 60 or a blind hole 70,
The conductor circuit 20 can be cut in the middle of a predetermined part of the surface of each layer member or a part of the layer member of the board 10C with the zero or blind hole 70, or as shown in FIG. The through hole 60 or the blind hole 7o is filled with the conductor 50 or the conductor 50 and the insulator 80 in a layered manner to form the substrate 10c.
Connecting conductor circuits 20 that three-dimensionally intersect or three-dimensionally overlap conductor circuits 20 at predetermined portions of the surface of each layer member or a part thereof, or connecting each layer member of the substrate 10C or a part of the layer member thereof. Each layer member 100a of the substrate 10C is connected by connecting the midway portions of the conductor circuit 20 at predetermined portions separated by the through hole 60 or the blind hole 70 on the surface.
, 100b, and 100c, a specific wiring circuit can be three-dimensionally formed.

第16図ないし第19図は本発明の第2の絶縁基板の他
の好適な実施例を示し、第16図はその分解斜視図、第
17図はその使用状態を示す平面図、第18図は第17
図のG−G断面図、第19図は第17図のH−H断面図
である。以下、これらの図中の実施例を説明する。
16 to 19 show other preferred embodiments of the second insulating substrate of the present invention, FIG. 16 is an exploded perspective view thereof, FIG. 17 is a plan view showing its usage state, and FIG. 18 is the 17th
19 is a sectional view taken along line GG in the figure, and FIG. 19 is a sectional view taken along line HH in FIG. 17. The embodiments shown in these figures will be described below.

図の絶縁基板では、セラミック基板10dを形成してい
る各層部材100a、100b、100C表面の格子状
の導体回路20の各格子目の四辺中途部に、導体回路2
0の幅より大径の絶縁体であるホール40を、各層部材
100a、100b。
In the insulated substrate shown in the figure, a conductor circuit 2 is placed in the middle of each of the four sides of each lattice of the lattice-shaped conductor circuit 20 on the surface of each layer member 100a, 100b, 100C forming the ceramic substrate 10d.
A hole 40, which is an insulator having a diameter larger than the width of 0, is formed in each layer member 100a, 100b.

100cを貫通させて備えている。そして、上記ホール
40で基板10の各層部材表面の導体回路20の各格子
目の四辺中途部を分断している。
100c is provided through it. The hole 40 divides the conductive circuit 20 on the surface of each layer member of the substrate 10 at the middle of each grid on four sides.

その他は既述実施例の第2の絶縁基板と同様に構成して
いて、第17図に示したように、基板10d外側に露出
する層部材100a表面の所定部位の導体回路中途部2
0bを、エツチングなどにより、分断したり、第18図
や第19図に示したように、基板10dの所定部位のホ
ール40に導体50または導体50と絶縁体80とを層
状に充填して、基板10dの各層部材またはその一部の
層部材表面の所定部位の立体的に交差する導体回路20
間または立体的に重なり合う導体回路間20間を接続し
たり、基板10dの各層部材またはその一部の層部材表
面のホール40で分断した状態にある所定部位の導体回
路20中途部を接続したり、第17図や第18図や第1
9図に示したように、基板10dの所定部位にその表面
または裏面から導体回路20の幅より大径または小径の
貫通穴60または盲穴70を穿設して、その貫通穴60
または盲穴70で基板10dの各層部材またはその一部
の層部材表面の所定部位の導体回路20中途部を分断し
たり、第18図に示したように、さらにその穿設した所
定部位の貫通穴60または盲穴70に導体50または導
体50と絶縁体80とを層状に充填して、基板10dの
各層部材またはその一部の層部材表面の所定部位の立体
的に交差する導体回路20間または立体的に重・なり合
う導体回路20間を接続したり、基板10dの各層部材
またはその一部の層部材表面の上記貫通穴60または盲
穴70で分断した所定部位の導体回路20中途部を接続
したりすることにより、基板10dの各層部材100a
、100b、1ooc表面に亙って、特定の配線回路を
立体的に形成できる。
The rest of the structure is the same as that of the second insulating substrate of the previously described embodiment, and as shown in FIG.
0b by etching or the like, or by filling the hole 40 at a predetermined portion of the substrate 10d with a conductor 50 or a conductor 50 and an insulator 80 in a layered manner as shown in FIGS. 18 and 19. Conductor circuits 20 that three-dimensionally intersect at predetermined portions on the surface of each layer member or a part of the layer member of the substrate 10d
Connecting conductor circuits 20 that overlap or three-dimensionally overlapping conductor circuits 20, or connecting conductor circuits 20 at predetermined locations that are separated by holes 40 on the surface of each layer member or a part of the layer member of the substrate 10d. , Figure 17, Figure 18, Figure 1
As shown in FIG. 9, a through hole 60 or a blind hole 70 having a diameter larger or smaller than the width of the conductor circuit 20 is bored at a predetermined portion of the substrate 10d from the front or back surface thereof.
Alternatively, a blind hole 70 may be used to cut off the middle part of the conductor circuit 20 at a predetermined portion on the surface of each layer member or a part of the layer member of the substrate 10d, or as shown in FIG. The conductor 50 or the conductor 50 and the insulator 80 are filled in the hole 60 or the blind hole 70 in a layered manner, and the conductor circuits 20 intersect three-dimensionally at a predetermined portion on the surface of each layer member or a part of the layer member of the substrate 10d. Alternatively, a midway portion of the conductor circuit 20 at a predetermined portion is connected between the conductor circuits 20 that overlap or overlap three-dimensionally, or is separated by the through hole 60 or blind hole 70 on the surface of each layer member or a part of the layer member of the substrate 10d. By connecting each layer member 100a of the substrate 10d,
, 100b, and 1ooc, a specific wiring circuit can be three-dimensionally formed.

なお、既述各実施例において、基板10a、10b表裏
面または基板toc、10dの各層部材表面の格子状の
導体回路20は、その格子目の大きさを大小異なった大
きさに形成したり、斜めに歪んだ形状に形成したりして
も良い。そして、基板10a、10b表裏面または基板
10c、10dの各層表面の一部の導体回路20のみが
、立体的に交差したり、立体的に重なり合ったりするよ
うに、基板10a、10.b表裏面または基板10c、
lodの各層表面に導体回路20を形成しても良い。
In each of the embodiments described above, the lattice-shaped conductor circuits 20 on the front and back surfaces of the substrates 10a and 10b or on the surfaces of each layer member of the substrates toc and 10d are formed so that the lattice sizes are different in size, It may also be formed into a diagonally distorted shape. Then, the substrates 10a, 10... b front and back surfaces or substrate 10c,
A conductive circuit 20 may be formed on the surface of each layer of the lod.

また、基板10a、lOb表裏面またはそのいずれか一
方の面や基板10C,10dの各層部材表面またはその
一部の層部材表面に、該面の格子状の導体回路20の交
差部分を斜めに横切る連続する導体回路または中途部を
分断した導体回路を備えて、基板10c、10d表裏面
または基板IQc、10dの各層部材表面に亙って、よ
り複雑な高密度の配線回路を立体的に形成できるように
しても良い。
In addition, on the front and back surfaces of the substrates 10a and 1Ob, or on the surface of each layer member of the substrates 10C and 10d, or on the surface of a part of the layer members thereof, diagonally cross the intersection of the lattice-shaped conductor circuits 20 on the surfaces. A more complex high-density wiring circuit can be formed three-dimensionally over the front and back surfaces of the substrates 10c, 10d or the surfaces of each layer member of the substrates IQc, 10d, by providing a continuous conductor circuit or a conductor circuit with a conductor circuit separated in the middle. You can do it like this.

また、基板10a、lob表裏面またはそのいずれか一
方の面や基板10c、10.dの各層部材表面またはそ
の一部の層部材表面の導体回路20を、格子状でなく、
円弧などの曲線または曲線と直線との連なりからなる導
体回路または折れ曲がった直線または曲線からなる導体
回路または放射状をした導体回路などに形成しても良い
Also, the substrate 10a, the front and back surfaces of the lob, or one of the surfaces thereof, the substrates 10c, 10. The conductor circuit 20 on the surface of each layer member d or a part of the layer member surface is not in a grid shape,
It may be formed into a conductor circuit consisting of a curve such as a circular arc or a series of curves and straight lines, a conductor circuit consisting of a bent straight line or curve, a radial conductor circuit, or the like.

また、基板10a、10b、10c、10dに単純な配
線回路を形成しようとする場合は、基板10a、fob
表裏面または基板10C,lodの各層部材表面に、導
体回路20を、その基板lQa、10b表裏面または基
板10c、lodの各層部材表面の導体回路20が立体
的に交差するようにまたはその少な(とも一部が立体的
に重なり合うように、単に縦または横方向などに一本ま
たは複数本並べて形成しても良い。
Moreover, when trying to form a simple wiring circuit on the substrates 10a, 10b, 10c, and 10d, the substrate 10a, fob
Conductor circuits 20 are placed on the front and back surfaces or on the surfaces of each layer member of the substrates 10C and lod, so that the conductor circuits 20 on the front and back surfaces of the substrates lQa and 10b or on the surfaces of each layer member of the substrates 10c and lod intersect three-dimensionally, or in a manner that the conductor circuits 20 intersect in three dimensions ( It is also possible to simply form one or more of them in a vertical or horizontal direction so that some of them overlap three-dimensionally.

また、基板10a、10b、10c、lodの立体的に
交差する導体回路20間または立体的に重なり合う導体
回路20間を、ヴィアフィル30でな(、内周面にタン
グステンメタライズ等からなる導体層を備えた導体であ
るスルーホール(図示せず)で接続したり、基板10a
、IOb、IQc、lodのホール40や基板10a、
10b。
In addition, the conductor circuits 20 of the substrates 10a, 10b, 10c, and LOD that intersect three-dimensionally or between the conductor circuits 20 that overlap three-dimensionally are connected with a via fill 30 (a conductor layer made of tungsten metallization or the like is formed on the inner peripheral surface). It is possible to connect with a through hole (not shown) which is a conductor provided on the board 10a.
, IOb, IQc, lod holes 40 and substrate 10a,
10b.

10C,lOdに穿設した貫通穴60または盲穴70に
、リング状の導体またはリング状の導体と絶縁体とを充
填して、基板10a、10b、10c、lOdの立体的
に交差する導体@路20問または立体的に重なり合う導
体回路20間を接続したり、基板LOa、10b表裏面
またはそのいずれか一方の面や基板10c、lodの各
層部材表面またはその一部の層部材表面のホール40で
分断した状態にある導体回路20中途部や貫通穴60ま
たは盲穴70で分断した導体回路20中途部を接続した
りしても良い。
A ring-shaped conductor or a ring-shaped conductor and an insulator are filled in the through holes 60 or blind holes 70 drilled in the substrates 10a, 10b, 10c, and 10d to form three-dimensionally intersecting conductors @ Holes 40 can be used to connect conductor circuits 20 that overlap three-dimensionally, or to connect the front and back surfaces of the substrates LOa and 10b, or the surfaces of each layer member of the substrates 10c and LOD, or the surface of a part of the layer members. It is also possible to connect the conductor circuit 20 in the middle where it is divided by the through hole 60 or the blind hole 70.

また、基板10a、10b、10c、10dのホール4
0を備えた部分に、前述ホール40と異なる導体回路2
0の幅より大径または小径の貫通穴状または盲穴状をし
たホールを備えたり、あるいは基板10a、Job、1
0c、10dの導体回路20が立体的に交差する部分ま
たは立体的に重なり合う部分であって、前述ホール40
を備えた部分と異なる部分に、導体回路20の幅より大
径または小径の貫通穴状または盲穴状をしたホールを備
えたりして、そのホールに導体または導体と絶縁体とを
層状に充填することにより、基板lQa、IOb表裏面
や基板10C,10dの各層部材表面またはその一部の
層部材表面の立体的に交差する導体回路20間または立
体的に重なり合う導体回路20間を接続したり、上記ホ
ールで分断した状態にある基板10a、10b表裏面ま
たはそのいずれか一方の面や基板10G、lodの各層
部材表面またはその一部の層部材表面の導体回路20中
途部を接続したりできるようにしても良い。
In addition, the holes 4 of the substrates 10a, 10b, 10c, 10d
0, a conductor circuit 2 different from the hole 40 described above is provided.
The substrate 10a, Job, 1 may have a through-hole or a blind hole with a diameter larger or smaller than the width of
A portion where the conductor circuits 20 of 0c and 10d three-dimensionally intersect or three-dimensionally overlap, and where the above-mentioned hole 40
A through hole or a blind hole having a diameter larger or smaller than the width of the conductor circuit 20 is provided in a portion different from the portion provided with the conductor circuit 20, and the hole is filled with a conductor or a conductor and an insulator in a layered manner. By doing so, the conductor circuits 20 intersecting three-dimensionally or the conductor circuits 20 overlapping three-dimensionally on the front and back surfaces of the substrates lQa and IOb, the surface of each layer member of the substrates 10C and 10d, or a part of the layer member surface thereof can be connected. , it is possible to connect the midway portion of the conductor circuit 20 on the front and back surfaces of the substrates 10a and 10b, or either one of the front and back surfaces of the substrates 10a and 10b, which are separated by the holes, and the surface of each layer member of the substrate 10G and lod, or the surface of a part of the layer member. You can do it like this.

また、基板10a、fob、10c、10dの導体回路
20が立体的に交差する部分または立体的に重なり合う
部分に導体であるグイアフイル30またはスルーホール
や絶縁体であるホール4゜の一方のみを備えたり、また
はその導体回路20が立体的に交差する部分または立体
的に重なり合う部分の2つ以上おきごとに導体であるグ
イアフィル30またはスルーホールや絶縁体であるホー
ル40を備えたり、またはその導体回路20が立体的に
交差する部分または立体的に重なり合う部分の一部のみ
に偏って導体であるダイアフイル30またはスルーホー
ルや絶縁体であるホール40を備えたりしても良い。
In addition, only one of the guia foil 30 which is a conductor, the through hole, or the hole 4° which is an insulator is provided at the portion where the conductor circuits 20 of the substrates 10a, fob, 10c, and 10d intersect three-dimensionally or overlap three-dimensionally. , or the conductor circuit 20 is provided with a guiafil 30 that is a conductor or a through hole or a hole 40 that is an insulator at every two or more parts where the conductor circuit 20 three-dimensionally intersects or three-dimensionally overlaps, or the conductor circuit 20 The diaphragm 30 which is a conductor, the through hole, or the hole 40 which is an insulator may be provided only in a part of the part where the two three-dimensionally intersect or three-dimensionally overlap.

また、多層構造の基板10C,10dにおいては、その
一部の複数の例えば層部材100a、100C表面のみ
に導体回路20を、その基板の複数の層部材100a、
100c表面の導体回路20が立体的に交差するように
、またはその基板の複数の層部材100a、100c表
面の導体回路20の少なくとも一部が立体的に重なり合
うように、備えるとともに、その基板10c、10dの
導体回路20が立体的に交差する部分または立体的に重
なり合う部分にヴィアフィル30またはスルーホールや
ホール40を備えて、その基板10c、lQdの一部の
複数の層部材100a、100C表面に亙って、特定の
配線回路を立体的に形成できるようにしても良い。
In addition, in the multilayer structure substrates 10C and 10d, the conductor circuit 20 is provided only on the surface of some of the layer members 100a and 100C, for example, the plurality of layer members 100a and 100C of the substrate.
The substrate 10c is provided so that the conductor circuits 20 on the surface of the substrate 100c intersect three-dimensionally, or so that at least a portion of the conductor circuits 20 on the surface of the plurality of layer members 100a and 100c of the substrate overlap three-dimensionally, and the substrate 10c, A via fill 30 or a through hole or a hole 40 is provided at a portion where the conductor circuits 20 of 10d three-dimensionally intersect or three-dimensionally overlap, and a plurality of layer members 100a, 100C of a part of the substrate 10c, lQd are provided on the surface. Additionally, a specific wiring circuit may be formed three-dimensionally.

さらに、本発明の第1、第2の絶縁基板は、1層または
多層構造のプラスチック基板にも利用可能である。
Furthermore, the first and second insulating substrates of the present invention can also be used as plastic substrates with a single layer or multilayer structure.

[発明の効果] 以上説明したように、本発明の第1、第2の絶縁基板に
よれば、基板表裏面または基板の複数の層部材表面に備
えた導体回路、および基板に備えた上記導体回路間を接
続する導体であるヴィアフィルまたはスルーホールや絶
縁体であるホールを用いて、基板表裏面または基板の複
数の層部材表面に亙って、特定の配線回路を自在に立体
的に形成できる。
[Effects of the Invention] As explained above, according to the first and second insulating substrates of the present invention, the conductor circuits provided on the front and back surfaces of the substrate or the surfaces of the plurality of layer members of the substrate, and the conductor circuits provided on the substrate. Using viafill or through holes, which are conductors that connect circuits, and holes, which are insulators, specific wiring circuits can be freely formed three-dimensionally over the front and back surfaces of the board or the surfaces of multiple layer members of the board. can.

そのため、本発明の第1、第2の絶縁基板によれば、基
板表裏面または基板の複数の層部材表面に亙って特定の
配線回路を形成する場合に、その配線回路形成用の特殊
のプリントマスクやヴィアフィルまたはスルーホール形
成用の特殊の金型などを形成せずとも、基板に目的とす
る特定の配線回路を立体的に形成できる。そして、試験
装置用や多種少量生産向けなどの特定の配線回路を持つ
1層または多層構造の絶縁基板を、手数や設備費を掛け
ずに、容易かつ迅速に形成することが可能となる。
Therefore, according to the first and second insulating substrates of the present invention, when a specific wiring circuit is formed over the front and back surfaces of the substrate or the surfaces of a plurality of layer members of the substrate, a special A desired specific wiring circuit can be three-dimensionally formed on a substrate without the need for a print mask, via fill, or special mold for forming through holes. Furthermore, it becomes possible to easily and quickly form a single-layer or multi-layer structure insulating substrate having a specific wiring circuit for use in test equipment or for high-mix, low-volume production without incurring any labor or equipment costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の絶縁基板の斜視図、第2図と第
3図と第4図と第5図はそれぞれ第1図の絶縁基板の使
用状態を示す斜視図とその平面図とそのΔ−A断面図と
そのB−B断面図、第6図は本発明の他の第1の絶縁基
板の斜視図、第7図と第8図と第9図と第10図はそれ
ぞれ第6図の絶縁基板の使用状態を示す斜視図とその平
面図とそのC−C断面図とそのD−D断面図、第11図
は本発明の第2の絶縁基板の分解斜視図、第12図と第
13図と第14図はそれぞれ第11図の絶縁基板の使用
状態を示す平面図とそのE−E断面図とそのF−F断面
図、第15図は本発明の他の第2の絶縁基板の分解斜視
図、第16図は本発明のもう一つの第2の絶縁基板の分
解斜視図、第17図と第18図と第19図はそれぞれ第
16図の絶縁基板の使用状態を示す平面図とそのG−G
断面図とそのH−H断面図である。 10a、IOb、10c、10d=−絶縁基板、20・
・・導体回路、 30・・・ダイアフイル、40・・・
ホール、 50・・・導体、 60・・貫通穴、70・
・・盲穴、 80・・・絶縁体。
FIG. 1 is a perspective view of the first insulating substrate of the present invention, and FIGS. 2, 3, 4, and 5 are a perspective view and a plan view of the insulating substrate of FIG. 1, respectively, showing the state in which it is used. and its Δ-A sectional view and its BB sectional view, FIG. 6 is a perspective view of another first insulating substrate of the present invention, and FIGS. 7, 8, 9, and 10, respectively. FIG. 6 is a perspective view showing the usage state of the insulating substrate, its plan view, its CC sectional view, and its D-D sectional view; FIG. 11 is an exploded perspective view of the second insulating substrate of the present invention; 12, 13, and 14 are a plan view, an E-E sectional view, and an FF sectional view of the insulating substrate shown in FIG. 11, respectively, and FIG. 15 shows another example of the present invention. FIG. 16 is an exploded perspective view of another second insulating substrate of the present invention, and FIGS. 17, 18, and 19 show the use of the insulating substrate of FIG. 16, respectively. A plan view showing the state and its G-G
They are a cross-sectional view and its HH cross-sectional view. 10a, IOb, 10c, 10d=-insulating substrate, 20.
...Conductor circuit, 30...Diafil, 40...
Hole, 50...Conductor, 60...Through hole, 70...
...Blind hole, 80...Insulator.

Claims (3)

【特許請求の範囲】[Claims] 1.絶縁基板の表裏面に、連続する導体回路または中途
部を分断した導体回路を、その絶縁基板表裏面の導体回
路が立体的に交差するように、またはその絶縁基板表裏
面の導体回路の少なくとも一部が立体的に重なり合うよ
うに、備えるとともに、その絶縁基板の前記導体回路が
立体的に交差する部分または立体的に重なり合う部分に
、その交差する導体回路間または重なり合う導体回路間
を接続する導体であるヴィアフィルまたはスルーホール
、または絶縁体であるホールを備えてなる、配線回路を
持つ絶縁基板。
1. Continuous conductor circuits or conductor circuits separated in the middle are placed on the front and back surfaces of the insulating substrate so that the conductor circuits on the front and back surfaces of the insulating substrate intersect in three dimensions, or at least one of the conductor circuits on the front and back surfaces of the insulating substrate is placed. The parts of the insulating substrate are provided so that the conductor circuits overlap three-dimensionally, and a conductor is provided in the part where the conductor circuits of the insulating substrate three-dimensionally intersect or three-dimensionally overlap, to connect between the intersecting conductor circuits or between the overlapping conductor circuits. An insulating substrate with a wiring circuit comprising a via fill or through hole, or a hole that is an insulator.
2.多層構造の絶縁基板の複数の層部材表面に、連続す
る導体回路または中途部を分断した導体回路を、その絶
縁基板の複数の層部材表面の導体回路が立体的に交差す
るように、またはその絶縁基板の複数の層部材表面の導
体回路の少なくとも一部が立体的に重なり合うように、
備えるとともに、その絶縁基板の前記導体回路が立体的
に交差する部分または立体的に重なり合う部分に、その
交差する導体回路間または重なり合う導体回路間を接続
する導体であるヴィアフィルまたはスルーホール、また
は絶縁体であるホールを備えてなる、配線回路を持つ絶
縁基板。
2. Continuous conductor circuits or conductor circuits separated in the middle are placed on the surfaces of multiple layer members of an insulating substrate with a multilayer structure so that the conductor circuits on the surfaces of the multiple layer members of the insulating substrate intersect three-dimensionally, or so that at least a portion of the conductor circuits on the surfaces of the plurality of layer members of the insulating substrate overlap three-dimensionally,
In addition, a via fill or through hole, which is a conductor that connects the intersecting conductor circuits or the overlapping conductor circuits, or insulation is provided in the portion of the insulating substrate where the conductor circuits three-dimensionally intersect or three-dimensionally overlap. An insulating substrate with wiring circuits and holes that form the body.
3.絶縁基板の表裏面、または多層構造の絶縁基板の複
数の層部材表面に、導体回路を複数本格子状に備えた、
請求項1または2記載の配線回路を持つ絶縁基板。
3. A lattice-shaped conductor circuit is provided with a plurality of conductor circuits on the front and back surfaces of an insulating substrate, or on the surfaces of multiple layer members of an insulating substrate with a multilayer structure.
An insulating substrate having the wiring circuit according to claim 1 or 2.
JP1275683A 1989-10-23 1989-10-23 Method of forming wiring board Expired - Lifetime JP2863219B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1275683A JP2863219B2 (en) 1989-10-23 1989-10-23 Method of forming wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1275683A JP2863219B2 (en) 1989-10-23 1989-10-23 Method of forming wiring board

Publications (2)

Publication Number Publication Date
JPH03136395A true JPH03136395A (en) 1991-06-11
JP2863219B2 JP2863219B2 (en) 1999-03-03

Family

ID=17558897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1275683A Expired - Lifetime JP2863219B2 (en) 1989-10-23 1989-10-23 Method of forming wiring board

Country Status (1)

Country Link
JP (1) JP2863219B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003507900A (en) * 1999-08-25 2003-02-25 クゥアルコム・インコーポレイテッド Bidirectional interface tool for printed wiring board development
JP2016025182A (en) * 2014-07-18 2016-02-08 大日本印刷株式会社 Through electrode substrate, wiring board and semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4889355A (en) * 1972-03-01 1973-11-22
JPS60180187A (en) * 1984-01-26 1985-09-13 松下電器産業株式会社 Dry processing universal substrate
JPS613119A (en) * 1984-06-16 1986-01-09 Canon Inc Display device
JPS61272991A (en) * 1985-05-28 1986-12-03 関口 忠 Universal printed circuit board
JPH01185994A (en) * 1988-01-21 1989-07-25 Sumitomo Electric Ind Ltd Multilayer interconnection substrate
JPH02140988A (en) * 1988-06-10 1990-05-30 Kei Shii Lee Jon Printed wiring board and manufacture thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4889355A (en) * 1972-03-01 1973-11-22
JPS60180187A (en) * 1984-01-26 1985-09-13 松下電器産業株式会社 Dry processing universal substrate
JPS613119A (en) * 1984-06-16 1986-01-09 Canon Inc Display device
JPS61272991A (en) * 1985-05-28 1986-12-03 関口 忠 Universal printed circuit board
JPH01185994A (en) * 1988-01-21 1989-07-25 Sumitomo Electric Ind Ltd Multilayer interconnection substrate
JPH02140988A (en) * 1988-06-10 1990-05-30 Kei Shii Lee Jon Printed wiring board and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003507900A (en) * 1999-08-25 2003-02-25 クゥアルコム・インコーポレイテッド Bidirectional interface tool for printed wiring board development
JP2016025182A (en) * 2014-07-18 2016-02-08 大日本印刷株式会社 Through electrode substrate, wiring board and semiconductor device

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Publication number Publication date
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