WO2021009865A1

WO2021009865A1 - High-density multilayer substrate and method for manufacturing same

Info

Publication number: WO2021009865A1
Application number: PCT/JP2019/028058
Authority: WO
Inventors: 光昭戸田; 光生岩本; 金光永井
Original assignee: 株式会社メイコー
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2021-01-21
Also published as: JPWO2021009865A1; TW202110293A

Abstract

A high-density multilayer substrate 1, which replaces a multilayer substrate 2 having through-vias including an interstitial via hole (IVH), is provided with: a multilayer wiring board 10 in which a plurality of insulating layers R1 to R5 and a plurality of wiring layers L1 to L6 are stacked alternately; a chip component 20 which has a first electrode terminal 22 and a second electrode terminal 23 on both ends and is embedded in an insulating layer R3 in an orientation such that the electrode terminals are spaced apart from each other in a direction perpendicular to a stacking direction of the multilayer wiring board 10; and a stack via 30 which provides electrical continuity between each of the wiring layers L1 and L6 formed on both sides of the multilayer wiring board 10 and at least one of the first electrode terminal 22 and the second electrode terminal 23, and which is formed of a plurality of laser vias stacked upon one another.

Description

High-density multilayer substrate and its manufacturing method

The present invention relates to a high-density multilayer substrate and a method for manufacturing the same.

Circuit boards used in electrical and electronic equipment are laminated with a plurality of wiring layers due to the recent increase in functionality and miniaturization, and penetrate through a plurality of conductive vias and boards connecting the wiring layers to each other. There is a tendency for a plurality of through holes to be provided to be formed at a gorge pitch. Here, the through hole penetrating the multilayer board has a larger diameter of the through hole according to the length of the through hole formed in the multilayer board, which presses the mounting area. Therefore, in a multilayer board that requires a gorgeous pitch, through holes can be replaced with through holes to save space by making the outer layer wiring layers on both sides of each other via a plurality of via holes that connect each wiring layer. Often formed.

In the high-density multilayer board as described above, when the spacing between the wiring layers is relatively small, the interlayer connection can be performed by laser vias, but when the spacing is relatively large, the laser via cannot be formed due to the limitation of the aspect ratio. There is. Therefore, in a multilayer substrate having a relatively thick insulating layer, through holes are formed in the insulating layer by mechanical means such as drilling, and the wiring layers on both sides of the insulating layer are made conductive with each other. By providing a non-penetrating via hole (IVH: Interstitial Via Hole), a conductive path can be formed in the outer layer wiring layers on both sides.

More specifically, in IVH, for example, as disclosed in Patent Document 1, a hole is drilled in a double-sided plate by drilling, and the inner wall of the hole is plated to be conductive with the wiring layers on both sides. At the same time, it is formed by filling the inside of the hole with a resin. Further, in IVH, by forming a lid plating that seals the resin inside the pores, the conductive vias provided in the adjacent insulating layers can be arranged side by side in the stacking direction.

Further, as disclosed in Patent Document 1, IVH eliminates the need for lid plating and reduces the manufacturing cost by arranging the conductive vias connected via the insulating layer laminated on the double-sided plate in a staggered manner. It can be suppressed.

Japanese Unexamined Patent Publication No. 2014-208751

However, when IVH is formed by the mechanical drilling holes as described above, a load is applied to the insulating layer, so that minute cracks are generated along the glass cloth contained in the insulating layer, and IVH is generated. There is a risk of leading to migration in which the IVH is short-circuited with an adjacent component such as a built-in component or a conductive via placed in the vicinity of the IVH. Therefore, in the high-density multilayer substrate on which the IVH is formed, the IVH and the adjacent component must be arranged apart from each other in order to suppress a short circuit, which may hinder the pitching of the gorge. In particular, when two IVHs are arranged adjacent to each other, the possibility of migration occurring between the two IVHs increases.

The present invention has been made in view of such a situation, and an object of the present invention is to replace a multilayer substrate on which a penetrating via containing IVH is formed with a gorge pitch while suppressing the occurrence of migration. It is an object of the present invention to provide a possible high-density multilayer substrate and a method for manufacturing the same.

The high-density multilayer substrate according to the present invention is a high-density multilayer substrate that replaces a multilayer substrate on which a through via containing IVH is formed, and is a multilayer wiring board in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated. , A pair of electrode terminals are provided at both ends, and a chip component embedded in the insulating layer in a direction in which the pair of electrode terminals are separated in a direction perpendicular to the stacking direction of the multilayer wiring board, and both sides of the multilayer wiring board. Each of the outer layer wiring layers formed in the above is conductive with at least one of the pair of electrode terminals, and a stack via is formed in which a plurality of laser vias are overlapped.

Further, the method for manufacturing a high-density multilayer substrate according to the present invention is a method for manufacturing a high-density multilayer substrate that replaces a multilayer substrate on which a through via containing IVH is formed, and is formed by being laminated on a first wiring layer. A chip component having a pair of electrode terminals provided at both ends is embedded in the insulating layer in a direction in which the pair of electrode terminals are separated in a direction perpendicular to the stacking direction, and a second wiring layer is provided on the surface of the insulating layer. The double-sided plate forming step of forming the double-sided plate and the multi-layering step of forming the multi-layer wiring board by multi-layering the double-sided plate are included, and in the multi-layering step, the outer layers formed on both sides of the multi-layer wiring board are included. A stack via is formed by stacking a plurality of laser vias so that each of the wiring layers conducts with at least one of the pair of electrode terminals.

According to the present invention, instead of the multilayer substrate on which the through via containing IVH is formed, it is possible to provide a high-density multilayer substrate capable of forming a gorge pitch while suppressing the occurrence of migration, and a method for manufacturing the same.

It is sectional drawing of the high density multilayer substrate which concerns on 1st Embodiment of this invention. It is sectional drawing which shows the component mounting process of the high density multilayer board which concerns on 1st Embodiment. It is sectional drawing which shows the double-sided plate forming process of the high-density multilayer substrate which concerns on 1st Embodiment. It is sectional drawing which shows the drilling process of the high density multilayer substrate which concerns on 1st Embodiment. It is sectional drawing which shows the plating process of the high density multilayer substrate which concerns on 1st Embodiment. It is sectional drawing which shows the patterning process of the high density multilayer substrate which concerns on 1st Embodiment. It is sectional drawing explaining the operation effect of the high density multilayer substrate which concerns on 1st Embodiment. It is sectional drawing of the multilayer substrate which concerns on the prior art in which the penetration via containing IVH was formed. It is sectional drawing of the high density multilayer substrate which concerns on 2nd Embodiment of this invention. It is sectional drawing of the multilayer substrate which concerns on the prior art in which the penetration via containing IVH was formed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described below, and the present invention can be arbitrarily modified and implemented without changing the gist thereof. In addition, the drawings used for explaining the embodiments are all schematically showing the constituent members, and are partially emphasized, enlarged, reduced, or omitted in order to deepen the understanding of the constituent members. It may not accurately represent the scale or shape.

Further, IVH (Interstitial Via Hole: non-penetrating via hole) in the present application means a conductive via formed by mechanical means such as drilling with a drill, and will be described as not including an interlayer connection such as a laser via.

<First Embodiment>
FIG. 1 is a cross-sectional view of the high-density multilayer substrate 1 according to the first embodiment of the present invention. The high-density multilayer board 1 includes a multilayer wiring board 10, chip components 20, and stack vias 30. The high-density multilayer board 1 can be used, for example, as an in-vehicle printed wiring board having excellent mechanical strength by mounting various electronic components (not shown) and appropriately forming a wiring circuit and a solder resist.

In the present embodiment, the multilayer wiring board 10 is formed by alternately laminating a plurality of insulating layers R1 to R5 and a plurality of wiring layers L1 to L6, but the number of layers is limited to this. It is not a thing and various changes are possible. Further, in the multilayer wiring board 10 of the present embodiment, the central insulating layer R3 is formed thicker than the others among the plurality of insulating layers R1 to R5.

The chip component 20 is a square chip component for burying a substrate embedded in the insulating layer R3 of the multilayer wiring board 10. For example, in this embodiment, it is a multilayer ceramic capacitor (MLCC: Multi-Layer Ceramic Capacitor). The dimensions of the chip component 20 are selected from standard products. For example, the so-called "0402" having a dimension of 0.4 mm x 0.2 mm or a so-called "0402" having a dimension of 0.3 mm x 0.15 mm when viewed in a plan view. "03015" can be adopted.

The stack via 30 is formed by stacking a plurality of laser vias on a straight line to form an interlayer connection in the multilayer wiring board 10. The stack via 30 in the present embodiment includes a first stack via 30a, a second stack via 30b, a third stack via 30c, and a fourth stack via 30d, and includes a pair of electrode terminals of the chip component 20 and a multilayer wiring board 10. It conducts with the outer layer wiring layer formed on both sides.

More specifically, the first stack via 30a connects one electrode terminal of the chip component 20 and a first land 31 provided at a position facing the one electrode terminal in the wiring layer L1 to each other. The second stack via 30b connects one electrode terminal of the chip component 20 and a second land 32 provided at a position facing the one electrode terminal in the wiring layer L6 to each other. That is, in the high-density multilayer board 1, the wiring layer L1 and the wiring layer L6 as the outer layer wiring layer are electrically conducted with each other via the first stack via 30a, one electrode terminal, and the second stack via 30b.

Further, the third stack via 30c connects the other electrode terminal of the chip component 20 and the third land 33 provided at a position facing the other electrode terminal in the wiring layer L1 to each other. The fourth stack via 30d connects the other electrode terminal of the chip component 20 and the fourth land 34 provided at a position facing the other electrode terminal in the wiring layer L6 to each other. That is, in the high-density multilayer board 1, the wiring layer L1 and the wiring layer L6 as the outer layer wiring layer are electrically conducted with each other via the third stack via 30c, the other electrode terminal, and the fourth stack via 30d.

That is, the high-density multilayer substrate 1 has a through hole that linearly connects the first land 31 and the second land 32 and a through hole that linearly connects the third land 33 and the fourth land 34 adjacent to each other. When it is necessary to form the structure, the structure of FIG. 1 composed of the chip component 20 and the stack via 30 is formed on the multilayer wiring board 10, so that the conductive paths corresponding to the two through holes are formed at a gorge pitch. .. The reason why the gorge pitching is possible will be described in detail later.

Subsequently, an example of the above-mentioned manufacturing method of the high-density multilayer substrate 1 will be described with reference to FIGS. 2 to 6. In the production of the high-density multilayer board 1, first, a component mounting step of mounting the chip component 20 on the copper foil 11 to be the wiring layer L4 is performed in a later step. FIG. 2 is a cross-sectional view showing a component mounting process of the high-density multilayer substrate 1 according to the first embodiment.

As shown in FIG. 2, the chip component 20 is mounted on the copper foil 11 via an adhesive 12 printed on the surface of the copper foil 11 as a "first wiring layer". Here, the adhesive 12 is made of an insulating material such as resin, and is provided on the surface of the copper foil 11 at a place where the chip component 20 is arranged with a predetermined thickness.

More specifically, the chip component 20 is composed of a component body 21 and a first electrode terminal 22 and a second electrode terminal 23 as "a pair of electrode terminals" formed of copper plating on both ends of the component body 21. To. Then, the chip component 20 is mounted so that both the first electrode terminal 22 and the second electrode terminal 23 are in contact with the adhesive 12.

Next, a double-sided plate containing the chip component 20 is formed by laminating a resin layer and a metal layer on the copper foil 11 on which the chip component 20 is mounted. FIG. 3 is a cross-sectional view showing a double-sided plate forming step of the high-density multilayer substrate 1 according to the first embodiment.

In the double-sided plate forming step, the chip component 20 mounted on the copper foil 11 is embedded by the insulating layer R3, and the copper foil 13 as the "second wiring layer" is provided on the surface of the insulating layer R3. A double-sided plate having a copper foil 11 and a copper foil 13 is formed on both sides of the insulating layer R3.

Here, the insulating layer R3 is, for example, a glass epoxy resin formed by impregnating a glass cloth with an epoxy resin, but a prepreg that does not contain the glass cloth may be adopted. Further, the insulating layer R3 may be embedded with an electronic component (not shown) other than the chip component 20.

Next, a drilling process is performed to secure a conductive path for the chip component 20 built in the double-sided plate. FIG. 4 is a cross-sectional view showing a drilling step of the high-density multilayer substrate 1 according to the first embodiment.

In the drilling step, as shown in FIG. 4, via holes are made from the copper foil 11 and the copper foil 13 toward the first electrode terminal 22 and the second electrode terminal 23 of the chip component 20, for example, by a CO ₂ laser. 14 is formed. As a result, the metal surfaces of the first electrode terminal 22 and the second electrode terminal 23 are exposed. In forming the via hole 14, it is preferable to appropriately perform a desmear treatment to remove the insulating resin remaining inside the hole. Further, it is preferable that each electrode terminal exposed by the formation of the via hole 14 is further subjected to a soft etching treatment to remove oxides and organic substances on the exposed surface. As a result, the surface of the metal is exposed without forming a coating, and the adhesion with the metal precipitated in the subsequent plating treatment is enhanced, and as a result, the electrical connection reliability is improved.

Next, the copper foil 11 and the copper foil 13 are made conductive with the first electrode terminal 22 and the second electrode terminal 23, and the copper foil 11 and the copper foil 13 are plated to form the wiring layer L3 and the wiring layer L4, respectively. Is done. FIG. 5 is a cross-sectional view showing a plating process of the high-density multilayer substrate 1 according to the first embodiment.

In the plating process, the copper foil 11 and the copper foil 13 of the double-sided plate and the via hole 14 are plated with copper to form a filled via 15 in which the via hole 14 is filled with copper plating, and the via hole 14 is electrically connected to the filled via 15. The thickness of the copper foil 11 and the copper foil 13 increases.

Then, a patterning process is performed to form a circuit on the thickened copper foil 11 and the copper foil 13 to form the wiring layer L3 and the wiring layer L4. FIG. 6 is a cross-sectional view showing a patterning process of the high-density multilayer substrate 1 according to the first embodiment.

In the patterning step, as shown in FIG. 6, the wiring layer L3 and the wiring layer L4 are formed by processing the conductor layer composed of the copper foil 11 and the copper foil 13 into a desired circuit pattern by, for example, known photolithography. be able to.

At this time, a land 16 is formed in the portion of the wiring layer L3 and the wiring layer L4 connected to the filled via 15 in order to form the stack via 30 in a later step.

Then, by applying a known build-up method of laminating a plurality of resin layers and a plurality of metal layers to the double-sided wiring board shown in FIG. 6, the multilayer wiring board 10 shown in FIG. 1 is formed. That is, a multi-layering step of repeating the addition of wiring layers on both sides of the double-sided wiring board shown in FIG. 6 by a series of steps of laminating resin layers, laminating copper foils, forming laser vias, copper plating treatment, and patterning treatment. The multilayer wiring board 10 can be formed. Since a conventional known technique can be adopted for the multi-layered substrate, detailed description thereof will be omitted here.

However, in the high-density multilayer substrate 1 of the present invention, the stack via 30 is formed at a position corresponding to the first electrode terminal 22 and the second electrode terminal 23 of the chip component 20 in the multilayering step. More specifically, the high-density multilayer board 1 shown in FIG. 1 conducts linearly with respect to the first electrode terminal 22 and the second electrode terminal 23 of the chip component 20 each time a layer is added by build-up. By forming the field vias 15 on top of each other, four stack vias 30 are formed. As a result, in the high-density multilayer substrate 1, two independent conductive paths conducting the wiring layer L1 and the wiring layer L6 are formed via the first electrode terminal 22 and the second electrode terminal 23, respectively.

Subsequently, the action and effect of the present invention will be described. FIG. 7 is a cross-sectional view illustrating the operation and effect of the high-density multilayer substrate 1 according to the first embodiment. In FIG. 7, the configuration of the high-density multilayer substrate 1 similar to that in FIG. 1 is shown.

In the high-density multilayer substrate 1 according to the first embodiment of the present invention, as described above, each of the pair of electrode terminals of the chip component 20 is connected to both outer layer wiring layers. That is, in the high-density multilayer board 1, one through via is formed by the first stack via 30a, the first electrode terminal 22, and the second stack via 30b, and the third stack via 30c, the second electrode terminal 23, and the second stack via 30b are formed. The other penetrating via is formed by the four stack vias 30d.

Here, each of the stack vias 30 can be formed by, for example, a laser via diameter W1 of 75 μm, a land 16 diameter W2 of 150 μm, and an adjacent land spacing W3 of 100 μm by a conventional laser via forming means.

Then, in the high-density multilayer board 1, two penetrating vias formed via the first electrode terminal 22 and the second electrode terminal 23 of the chip component 20 are arranged at intervals according to the dimensions of the chip component 20. It will be. At this time, since both through vias are electrically cut off due to the characteristics of the chip component 20 as a capacitor, they are configured as independent conductive paths without causing a short circuit even when the applied potentials are different from each other. Will be done. The capacitor as the chip component 20 is set so that the rated voltage is larger than the maximum potential difference assumed between both through vias, so that a short circuit can be prevented more reliably.

As a result, in the high-density multilayer board 1, for example, when the standard of the chip component 20 is "0402", the pitch P1 of the penetrating vias of each other can be suppressed to about 250 μm. Further, in the high-density multilayer board 1, for example, when the standard of the chip component 20 is "03015", the pitch P1 of the penetrating vias of each other can be suppressed to about 200 μm.

Further, since the above-mentioned through via is formed in the high-density multilayer substrate 1 without using IVH formed by mechanical means, damage to the insulating layer R3 in the manufacturing process can be prevented. Therefore, in the high-density multilayer board 1, even if other electronic components or the like are arranged around the chip component 20, the possibility of migration occurring between them can be suppressed, and the possibility of hindering the pitching of the gorge is reduced. can do.

Next, as a comparative example with respect to the high-density multilayer substrate 1 according to the present invention, a conventional technique in which two penetrating vias using IVH are arranged adjacent to each other will be described. FIG. 8 is a cross-sectional view of the multilayer substrate 2 according to the prior art in which a through via containing IVH is formed. The internal configuration of the multilayer board 2 shown in FIG. 8 is different from the high-density multilayer board 1 of the present invention described above in that the wiring layer L3 and the wiring layer L4 are conducted by IVH.

More specifically, in the multilayer substrate 2 according to the prior art, one through via is formed through the first non-penetrating via hole IVH1 formed in the insulating layer R3, and the second non-penetrating via is formed in the insulating layer R3. The other penetrating via is configured through the via hole IVH2. Here, in each IVH, a hole is formed by a drill in the insulating layer R3 in which the wiring layer L3 and the wiring layer L4 are formed on both sides, copper plating is applied to the inner wall of the hole, and the internal space is filled with resin. It is formed by doing. Further, as shown in FIG. 8, the IVH can directly connect the conductive via through the lid plating by forming the lid plating that seals the resin inside the hole.

However, the multilayer substrate 2 according to the prior art has a hole diameter of about 100 μm due to mechanical fangs being drilled in the formation of the first non-penetrating via hole IVH1 and the second non-penetrating via hole IVH2. As a result, the land diameter W2 at both ends of the IVH becomes about 300 μm.

Further, in the multilayer substrate 2 according to the prior art, migration is likely to occur due to damage to the insulating layer R3 due to the formation of IVH, and when the insulating layer R3 is formed of a general material, the first non-penetrating via hole In order to prevent a short circuit between the IVH1 and the second non-penetrating via hole IVH2, it is necessary to set the distance W4 between the two to 0.4 mm or more. Even when the insulating layer R3 is formed of a highly reliable material to improve the insulating property, it is necessary to set the distance W4 between the two to 0.25 mm or more.

Therefore, in the multilayer board 2 according to the prior art, even if the land spacing W3 at both ends of the IVH is suppressed to 50 μm, the pitch P2 of the penetrating vias of each other is set to about 350 μm in order to ensure reliability against a short circuit. It must be set, and other electronic components and the like cannot be arranged in the vicinity of the first non-penetrating via hole IVH1 and the second non-penetrating via hole IVH2, which hinders the pitching of the gorge.

As described above, in the high-density multilayer board 1 according to the present invention, the chip component 20 is embedded in the insulating layer R3 of the multilayer wiring board 10, and each electrode terminal of the chip component 20 and the stack via 30 connected to the electrode terminal are provided. By forming the penetrating vias through the layers, the outer layer wiring layers formed on both sides of the multilayer wiring board 10 are made conductive with each other. Therefore, in the high-density multilayer board 1, the pitch of two stack vias 30 arranged apart from each other in the direction perpendicular to the stacking direction of the multilayer wiring boards 10 can be set according to the dimensions of the chip component 20. .. At this time, since the above-mentioned through via is formed in the high-density multilayer substrate 1 without using IVH formed by mechanical means, damage to the insulating layer R3 in which the chip component 20 is embedded is prevented. be able to.

As a result, in the high-density multilayer board 1, even if other electronic components or the like are arranged around the chip component 20 constituting the penetrating via, the possibility of migration occurring between them can be suppressed, and the gorge pitch can be increased. The risk of being hindered can be reduced. Therefore, according to the present invention, it is possible to provide a high-density multilayer substrate 1 capable of forming a gorge pitch while suppressing the occurrence of migration, instead of the multilayer substrate 2 on which the through vias containing IVH are formed.

<Second Embodiment>
Next, the second embodiment of the present invention will be described. In the high-density multilayer board 3 according to the second embodiment, the chip component 40 incorporated in the high-density multilayer board 1 of the first embodiment described above is a resistor, and the second stack via 30b and the third stack via 30b and the third. The area of the wiring layers L1 to L6 is expanded instead of not providing the stack via 30c. Hereinafter, the parts different from those of the first embodiment will be described, and the components common to the first embodiment are designated by the same reference numerals and detailed description thereof will be omitted. Since each step in the manufacturing method of the high-density multilayer substrate 3 is almost the same as that of the high-density multilayer substrate 1 of the first embodiment described above, detailed description of the manufacturing method will be omitted.

FIG. 9 is a cross-sectional view of the high-density multilayer substrate 3 according to the second embodiment of the present invention. The chip component 40 in the high-density multilayer substrate 3 of the second embodiment is a square chip component for embedding a substrate, like the chip component 20 according to the first embodiment described above, and has the same component shape as the chip component 20. doing. On the other hand, since the chip component 40 in the second embodiment is a resistor, energization between the first electrode terminal 22 and the second electrode terminal 23 is permitted.

Therefore, in the high-density multilayer board 3 according to the second embodiment, the first land 31 formed on the wiring layer L1 and the fourth land 34 formed on the wiring layer L6 have a first stack via 30a and a chip component 40. , And a through via that conducts through the fourth stack via 30d. That is, the high-density multilayer board 3 is formed with through vias that are used to conduct conduction between the first land 31 and the fourth land 34 that are not aligned in a straight line in the substrate stacking direction.

Here, it is preferable that the resistance value of the chip component 40 is set as low as possible as a conduction path corresponding to a part of the through via, and in the present embodiment, a zero ohm resistor is adopted. There is.

Further, the size of the chip component 40 is selected from the standard products also in this embodiment. Therefore, in the high-density multilayer board 3 according to the second embodiment, the distance between the first stack via 30a and the fourth stack via 30d can be set according to the dimensions of the chip component 40. As a result, the high-density multilayer board 3 according to the second embodiment has the same as the first embodiment described above, for example, when the standard of the chip component 40 is "0402", the first stack via 30a and the fourth stack via 30a. The pitch P3 with the stack via 30d can be suppressed to about 250 μm. For example, when the standard of the chip component 40 is “03015”, the pitch P3 can be suppressed to about 200 μm.

Further, in the high-density multilayer substrate 3 according to the second embodiment, the penetrating via is formed without using IVH formed by mechanical means, as in the first embodiment described above. Damage to the insulating layer R3 in the manufacturing process can be prevented. Therefore, in the high-density multilayer board 3, even if other electronic components or the like are arranged around the chip component 40, the possibility of migration occurring between them can be suppressed, and the pitch can be increased.

Further, in the high-density multilayer board 3 according to the second embodiment, since one of the upper surface or the lower surface of each electrode terminal of the chip component 40 is not connected by the laser via, the wiring layer L3 and the wiring layer are located at positions facing the portions. It is also possible to extend L4 and use it effectively.

Next, as a comparative example with respect to the high-density multilayer substrate 3 according to the present invention, there is a case where the connection positions of the through via formed via the IVH and the wiring layer L1 and the wiring layer L6 do not face each other on both sides of the multilayer wiring board 10. The prior art will be described. FIG. 10 is a cross-sectional view of the multilayer substrate 4 according to the prior art in which a through via containing IVH is formed. The internal configuration of the multilayer board 4 shown in FIG. 10 is different from the high-density multilayer board 3 of the present invention described above in that the wiring layer L3 and the wiring layer L4 are conducted by IVH.

More specifically, in the multilayer board 4 according to the prior art, the wiring layer L3 and the wiring layer L4 are conducted through the third non-penetrating via hole IVH3 formed in the insulating layer R3, and are insulated from the insulating layer R1. The stack vias formed on the layer R2, the third non-penetrating via hole IVH3, and the stack vias formed on the insulating layer R4 and the insulating layer R5 are all arranged in a straight line with respect to the stacking direction of the multilayer wiring board 10. There is no arrangement.

Here, in the third non-penetrating via hole IVH3, a hole is formed by a drill in the insulating layer R3 in which the wiring layer L3 and the wiring layer L4 are formed on both sides, and the inner wall of the hole is plated with copper and the internal space is formed. It is formed by filling with resin without performing lid plating. That is, since the third non-penetrating via hole IVH3 has a configuration in which the conductive via is not directly connected, the manufacturing cost is suppressed by not forming the lid plating.

However, the multilayer substrate 4 according to the prior art is formed in the insulating layer R1 and the insulating layer R2 because the vicinity of both ends of the third non-penetrating via hole IVH3 is a wiring prohibited region as shown by two broken line ellipses in FIG. It becomes necessary to separate the stack via and the third non-penetrating via hole IVH3, and the distance between the stack via formed on the insulating layer R4 and the insulating layer R5 and the third non-penetrating via hole IVH3, and the pitch P2 of both is set. It will have to be set to about 450 μm.

Further, in the multilayer board 4 according to the prior art, migration is likely to occur due to damage to the insulating layer R3 due to the formation of IVH, so that other electronic components or the like are arranged in the vicinity of the third non-penetrating via hole IVH3. It cannot be done and the pitching of the gorge is hindered. Further, in the multilayer board 4 according to the prior art, the areas of the wiring layer L3 and the wiring layer L4 are limited by the wiring prohibition region described above.

As described above, in the high-density multilayer board 3 according to the present invention, the chip component 40 is embedded in the insulating layer R3 of the multilayer wiring board 10, and each electrode terminal of the chip component 40 and the stack via 30 connected to the electrode terminal are provided. By forming the penetrating vias through the layers, the outer layer wiring layers formed on both sides of the multilayer wiring board 10 are made conductive with each other. Therefore, in the high-density multilayer board 3, the pitch of two stack vias 30 arranged apart from each other in the direction perpendicular to the stacking direction of the multilayer wiring boards 10 can be set according to the dimensions of the chip component 40. .. At this time, since the above-mentioned through via is formed in the high-density multilayer substrate 3 without using IVH formed by mechanical means, damage to the insulating layer R3 in which the chip component 40 is embedded is prevented. be able to.

As a result, in the high-density multilayer board 3, even if other electronic components or the like are arranged around the chip component 40 constituting the through via, the possibility of migration occurring between them can be suppressed, and the gorge pitch can be increased. The risk of being hindered can be reduced. Therefore, according to the present invention, it is possible to provide a high-density multilayer substrate 3 capable of forming a gorge pitch while suppressing the occurrence of migration, instead of the multilayer substrate 4 on which a through via containing IVH is formed.

Although the description of the embodiment is completed above, the present invention is not limited to each of the above-described embodiments. For example, in each of the above embodiments, the case where a capacitor or a resistor is adopted as the "chip component" is illustrated, but in the case of a square chip component for burying a substrate having electrode terminals at both ends, the through vias are multi-layer wiring. Various electronic components can be adopted as long as the circuit configuration of the plate 10 is not impaired. Further, in each of the above embodiments, the embodiment in which one or two penetrating vias are formed through one chip component is illustrated, but more penetrating vias are formed through a plurality of chip components, which is more complicated. A circuit configuration may be constructed.

<Embodiment of the present invention>
A first aspect of the present invention is a high-density multilayer substrate that replaces a multilayer substrate on which a through via containing IVH is formed, and comprises a multilayer wiring board in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated. A pair of electrode terminals are provided at both ends, and the pair of electrode terminals are embedded in the insulating layer in a direction perpendicular to the stacking direction of the multilayer wiring board, and on both sides of the multilayer wiring board. It is a high-density multilayer substrate including each of the formed outer layer wiring layers and a stack via which conducts at least one of the pair of electrode terminals and is formed by stacking a plurality of laser vias.

In the high-density multilayer substrate according to the first aspect of the present invention, a chip component is embedded in an insulating layer in a multilayer wiring board, and a through via is formed through an electrode terminal of the chip component and a stack via connected thereto. As a result, the outer layer wiring layers formed on both sides of the multilayer wiring board are made conductive with each other. Therefore, in the high-density multilayer board, the pitch of two stack vias arranged apart from each other in the direction perpendicular to the stacking direction of the multilayer wiring boards can be set according to the dimensions of the chip component. At this time, since the above-mentioned through via is formed in the high-density multilayer substrate without using IVH formed by mechanical means, it is possible to prevent damage to the insulating layer in which the chip component is embedded. .. As a result, according to the high-density multilayer board according to the first aspect of the present invention, even if other electronic components or the like are arranged around the chip components constituting the penetrating vias, migration occurs between them. The risk can be suppressed, and the risk of hindering the pitching of the gorge can be reduced.

The second aspect of the present invention is, in the first aspect of the present invention described above, the chip component is a high-density multilayer substrate whose dimensions are selected from standard products.

According to the second aspect of the present invention, for example, by adopting an existing chip component conforming to an industrial standard, a cost advantage can be obtained because it is a mass-produced product, and in mounting the chip component and conducting with a laser via. By patterning the manufacturing process, it is possible to provide a high-density multilayer substrate in which the manufacturing cost is reduced and the yield is also improved.

A third aspect of the present invention is that in the first or second aspect of the present invention described above, the chip component is a capacitor, and each of the pair of electrode terminals is connected to both outer layer wiring layers. It is a high-density multilayer board.

According to the third aspect of the present invention, two electrically independent penetrating vias connecting the outer layer wiring layers formed on both sides of the multilayer wiring board are arranged at a gorge pitch without short-circuiting. Can be done.

A fourth aspect of the present invention is, in the third aspect of the present invention described above, the capacitor is set so that the rated voltage is larger than the maximum potential difference assumed for the pair of electrode terminals. It is a multilayer board.

According to the fourth aspect of the present invention, even when the potentials of the two penetrating vias change independently, a capacitor having a rated voltage larger than the maximum potential difference assumed between the two is selected. By maintaining the potential difference between the two according to the charge amount of the capacitor, the independence of the two conductive paths can be reliably ensured.

In a fifth aspect of the present invention, in the first or second aspect of the present invention described above, the chip component is a resistor, and each of the outer layer wiring layers is connected to one of the pair of electrode terminals. It is a high-density multilayer substrate.

According to the fifth aspect of the present invention, even when the connection position of the through via formed on the multilayer wiring board with the outer layer wiring layer is different from each other on both sides of the multilayer wiring board, it depends on the dimensions of the chip component. The route of the penetrating via can be set, and the interval between the connection positions can be set to the gorge pitch.

In the sixth aspect of the present invention, in the fifth aspect of the present invention described above, the resistor is a high-density multilayer substrate which is a zero-ohm resistor.

According to the sixth aspect of the present invention, it is possible to prevent a voltage drop due to a chip component in a penetrating via that conducts the outer layer wiring layers on both sides of the multilayer wiring board.

A seventh aspect of the present invention is a method for manufacturing a high-density multilayer substrate that replaces a multilayer substrate on which a through via containing IVH is formed, and is a pair of insulating layers formed by being laminated on a first wiring layer. Chip components provided with electrode terminals at both ends are embedded in a direction in which the pair of electrode terminals are separated in a direction perpendicular to the stacking direction, and a second wiring layer is provided on the surface of the insulating layer to form a double-sided plate. Each of the outer layer wiring layers formed on both sides of the multilayer wiring board is said to include a plate forming step and a multilayering step of forming the multilayer wiring board by multilayering the double-sided plates. This is a method for manufacturing a high-density multilayer substrate in which a stack via is formed by stacking a plurality of laser vias so as to be conductive with at least one of a pair of electrode terminals.

According to the method for manufacturing a high-density multilayer substrate according to a seventh aspect of the present invention, a chip component is embedded in an insulating layer in a multilayer wiring board, via an electrode terminal of the chip component and a stack via connected to the chip component. By forming the through vias, the outer layer wiring layers formed on both sides of the multilayer wiring board are made conductive with each other. Therefore, in the high-density multilayer board, the pitch of two stack vias arranged apart from each other in the direction perpendicular to the stacking direction of the multilayer wiring boards can be set according to the dimensions of the chip component. At this time, since the above-mentioned through via is formed in the high-density multilayer substrate without using IVH formed by mechanical means, it is possible to prevent damage to the insulating layer in which the chip component is embedded. .. As a result, according to the method for manufacturing a high-density multilayer substrate according to the seventh aspect of the present invention, even if other electronic components or the like are arranged around the chip components constituting the penetrating vias, migration is performed between them. Can be suppressed, and the risk of hindering the pitching of the gorge can be reduced.

The eighth aspect of the present invention is the method for manufacturing a high-density multilayer substrate in which the dimensions of the chip component are selected from standard products in the seventh aspect of the present invention described above.

According to the eighth aspect of the present invention, for example, by adopting an existing chip component conforming to an industrial standard, a cost advantage can be obtained because it is a mass-produced product, and in mounting the chip component and conducting with a laser via. By patterning the manufacturing process, it is possible to provide a method for manufacturing a high-density multilayer substrate in which the manufacturing cost is reduced and the yield is also improved.

A ninth aspect of the present invention is that in the seventh or eighth aspect of the present invention described above, the chip component is a capacitor, and each of the pair of electrode terminals is connected to both outer layer wiring layers. This is a method for manufacturing a high-density multilayer substrate.

According to the ninth aspect of the present invention, two electrically independent penetrating vias connecting the outer layer wiring layers formed on both sides of the multilayer wiring board are arranged at a gorge pitch without short-circuiting. Can be done.

A tenth aspect of the present invention is a high density in which the rated voltage of the capacitor is set to be larger than the maximum potential difference assumed for the pair of electrode terminals in the ninth aspect of the present invention described above. This is a method for manufacturing a multilayer substrate.

According to the tenth aspect of the present invention, even when the potentials of the two penetrating vias change independently, a capacitor having a rated voltage larger than the maximum potential difference assumed between the two is selected. By maintaining the potential difference between the two according to the charge amount of the capacitor, the independence of the two conductive paths can be ensured.

In the eleventh aspect of the present invention, in the seventh or eighth aspect of the present invention described above, the chip component is a resistor, and each of the outer layer wiring layers is connected to one of the pair of electrode terminals. This is a method for manufacturing a high-density multilayer substrate.

According to the eleventh aspect of the present invention, even when the connection position of the through via formed on the multilayer wiring board with the outer layer wiring layer is different from each other on both sides of the multilayer wiring board, it depends on the dimensions of the chip component. The route of the penetrating via can be set, and the interval between the connection positions can be set to the gorge pitch.

The twelfth aspect of the present invention is the method for manufacturing a high-density multilayer substrate in which the resistor is a zero-ohm resistor in the eleventh aspect of the present invention described above.

According to the twelfth aspect of the present invention, it is possible to prevent a voltage drop due to a chip component in a penetrating via that conducts the outer layer wiring layers on both sides of the multilayer wiring board.

1 High-density multilayer board 10 Multilayer wiring board 20 Chip parts 22 1st electrode terminal 23 2nd electrode terminal 30 Stack vias R1 to R5 Insulation layer L1 to L6 Wiring layer

Claims

A high-density multilayer substrate that replaces a multilayer substrate on which a through via containing IVH is formed.
A multi-layer wiring board in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated,
A chip component in which a pair of electrode terminals are provided at both ends and the pair of electrode terminals are embedded in the insulating layer in a direction perpendicular to the stacking direction of the multilayer wiring board.
A high-density multilayer substrate comprising each of the outer layer wiring layers formed on both sides of the multilayer wiring board and a stack via that conducts at least one of the pair of electrode terminals and is formed by stacking a plurality of laser vias.
The high-density multilayer substrate according to claim 1, wherein the chip component has dimensions selected from standard products.
The high-density multilayer substrate according to claim 1 or 2, wherein the chip component is a capacitor, and each of the pair of electrode terminals is connected to both outer layer wiring layers, respectively.
The high-density multilayer substrate according to claim 3, wherein the capacitor is set so that the rated voltage is set to be larger than the maximum potential difference assumed for the pair of electrode terminals.
The high-density multilayer substrate according to claim 1 or 2, wherein the chip component is a resistor, and each of the outer layer wiring layers is connected to either one of the pair of electrode terminals.
The high-density multilayer substrate according to claim 5, wherein the resistor is a zero-ohm resistor.
A method for manufacturing a high-density multilayer substrate that replaces a multilayer substrate on which a through via containing IVH is formed.
A chip component having a pair of electrode terminals provided at both ends is embedded in an insulating layer formed by being laminated on the first wiring layer in a direction in which the pair of electrode terminals are separated from each other in a direction perpendicular to the stacking direction. A double-sided plate forming step of providing a second wiring layer on the surface of the layer to form a double-sided plate,
Including a multi-layering step of forming a multi-layer wiring board by multi-layering the double-sided plate.
In the multi-layering step, a stack via is formed by stacking a plurality of laser vias so that each of the outer layer wiring layers formed on both sides of the multilayer wiring board conducts with at least one of the pair of electrode terminals. A method for manufacturing a high-density multilayer substrate.
The method for manufacturing a high-density multilayer substrate according to claim 7, wherein the chip component has dimensions selected from standard products.
The method for manufacturing a high-density multilayer substrate according to claim 7 or 8, wherein the chip component is a capacitor, and each of the pair of electrode terminals is connected to both outer layer wiring layers, respectively.
The method for manufacturing a high-density multilayer substrate according to claim 9, wherein the capacitor is set so that the rated voltage is set to be larger than the maximum potential difference assumed for the pair of electrode terminals.
The method for manufacturing a high-density multilayer substrate according to claim 7 or 8, wherein the chip component is a resistor, and each of the outer layer wiring layers is connected to one of the pair of electrode terminals.
The method for manufacturing a high-density multilayer substrate according to claim 11, wherein the resistor is a zero-ohm resistor.