TW202110293A - High-density multilayer substrate and method for manufacturing same - Google Patents

Abstract

A high-density multilayer substrate 1, which replaces a multilayer substrate 2 having through-vias including an interstitial via hole (IVH), is provided with: a multilayer wiring board 10 in which a plurality of insulating layers R1 to R5 and a plurality of wiring layers L1 to L6 are stacked alternately; a chip component 20 which has a first electrode terminal 22 and a second electrode terminal 23 on both ends and is embedded in an insulating layer R3 in an orientation such that the electrode terminals are spaced apart from each other in a direction perpendicular to a stacking direction of the multilayer wiring board 10; and a stack via 30 which provides electrical continuity between each of the wiring layers L1 and L6 formed on both sides of the multilayer wiring board 10 and at least one of the first electrode terminal 22 and the second electrode terminal 23, and which is formed of a plurality of laser vias stacked upon one another.

Description

High-density multilayer substrate and manufacturing method of high-density multilayer substrate

The present invention relates to a high-density multilayer substrate and a method for manufacturing the high-density multilayer substrate.

Circuit boards used in electrical and electronic equipment have tended to be multi-functional and miniaturized in recent years: they are stacked by multiple wiring layers, and the multiple wiring layers are connected to each other and connected to each other. A continuity via and a plurality of through holes provided through the substrate are formed with a narrow pitch. Here, the diameter of the through hole penetrating the multilayer substrate is increased in accordance with the length of the penetrating hole (penetrating hole) formed in the multilayer substrate, thereby compressing the mounting area. Therefore, in multi-layer substrates that require narrower pitches, the outer wiring layers on both sides are often connected to each other through a plurality of via holes that connect the wiring layers between layers, thereby replacing the through holes to form a saver. Spatialized through vias.

Although the above-mentioned high-density multilayer substrates can be connected by laser vias (laser vias) when the spacing between the wiring layers is relatively small, there is a problem due to the aspect ratio when the spacing is relatively large. The situation where the laser through hole cannot be formed due to limitation. Therefore, in a multilayer substrate with a relatively thick insulating layer, through holes are formed in the insulating layer by mechanical means such as drilling with a drill, and the wiring layers on both sides of the insulating layer are provided to communicate with each other. Interstitial Via Hole (IVH for short), which can form a conductive path on the outer wiring layer on both sides.

More specifically, for example, as disclosed in Patent Document 1, IVH (non-through through hole) is formed by drilling a hole in a double-sided board by drilling and performing plating processing on the inner wall of the hole. Conduction with the double-sided wiring layer and fill the inside of the hole with resin. In addition, in the IVH system, the through-holes provided in the adjacent insulating layer can be arranged in the stacking direction by forming a cover plating that seals the resin inside the hole.

Furthermore, as disclosed in Patent Document 1, the IVH system offsets the vias connected via the insulating layer of the double-sided sided laminate, thereby eliminating the need to form a cap plating and suppressing the manufacturing cost. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] JP 2014-208751 A.

[The problem to be solved by the invention]

However, when the IVH is formed by mechanically perforating holes as described above, since a load is placed on the insulating layer, there are minute cracks along the glass cloth included in the insulating layer. In addition, there is a suspicion that adjacent parts such as internal parts or vias arranged in the vicinity of the IVH may cause migration (migration) short-circuiting the IVH. Therefore, a high-density multilayer substrate on which IVH is formed must be placed away from adjacent parts in order to suppress short circuits, and there is a concern that it hinders the narrowing of the pitch. In particular, when two IVHs are arranged adjacent to each other, the suspicion of migration between the two becomes even higher.

The present invention was developed in view of the above situation. The purpose of the present invention is to provide a high-density multilayer substrate and a method for manufacturing a high-density multilayer substrate, which can replace the multilayer substrate formed with through holes containing IVH and can suppress the occurrence of migration And can narrow the pitch. [Means to solve the problem]

The high-density multi-layer substrate of the present invention is used to replace the multi-layer substrate formed with through holes including IVH. The high-density multi-layer substrate includes: a multi-layer wiring board, which is alternately laminated with a plurality of insulating layers and a plurality of wiring layers; a wafer; The component is provided with a pair of electrode terminals at both ends, and when the wafer component is embedded in the insulating layer, the following orientation is used: the pair of electrode terminals are moved away in a direction perpendicular to the stacking direction of the multilayer wiring board; and Stack vias are formed by stacking a plurality of laser vias to connect each of the double-sided outer wiring layers formed on the multilayer wiring board with at least one of the pair of electrode terminals.

In addition, in the method for manufacturing a high-density multilayer substrate of the present invention, the high-density multilayer substrate is used to replace a multilayer substrate formed with through holes containing IVH, and the method for manufacturing the high-density multilayer substrate includes: A chip component with a pair of electrode terminals provided at both ends such that the pair of electric terminals are buried in the insulating layer laminated on the first wiring layer in the direction perpendicular to the direction of the lamination, and arranged on the surface of the insulating layer The second wiring layer thus forms a double-sided board; and the multi-layering step is to multi-layer the aforementioned double-sided board to form a multi-layer wiring board; in the aforementioned multi-layering step, so that the double-sided outer wiring layer formed on the multi-layer wiring board A plurality of laser through holes are overlapped so that at least one of the pair of electrode terminals is electrically connected to each other to form an overlapped through hole. [Efficacy of invention]

According to the present invention, it is possible to provide a high-density multilayer substrate and a method for manufacturing a high-density multilayer substrate, which can replace the multilayer substrate formed with through holes containing IVH, can suppress the occurrence of migration, and can narrow the pitch.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the present invention is not limited by the content described below, and can be arbitrarily changed and implemented within the scope not changing the gist of the present invention. In addition, the drawings used in the description of the embodiment are only schematically showing the constituent members, so they are partially emphasized, enlarged, reduced, or omitted in order to deepen the understanding, and the structure may be incorrectly displayed. The scale and shape of the component.

In addition, the IVH system in the present application means a via hole formed by a mechanical means such as an opening with a drill bit, and can be described as an interlayer connection that does not include a laser via hole or the like.

[First Embodiment] Fig. 1 is a cross-sectional view of a high-density multilayer substrate 1 according to a first embodiment of the present invention. The high-density multilayer substrate 1 includes a multilayer wiring board 10, a chip component 20, and a stacked through hole 30. The high-density multilayer substrate 1 is equipped with various electronic components not shown in the drawings, and is appropriately formed with wiring circuits and solder resist, so that it can be used as, for example, an automotive printed wiring board with excellent mechanical strength.

In this embodiment, although the multilayer wiring board 10 is formed by alternately laminating a plurality of insulating layers R1 to R5 and a plurality of wiring layers L1 to L6, the number of layers is not limited to this and can be variously changed. In addition, the multilayer wiring board 10 in this embodiment is formed such that the central insulating layer R3 among the plurality of insulating layers R1 to R5 is thicker than the other insulating layers R1, R2, R4, and R5.

The chip component 20 is a square type chip component used for substrate embedding in which the insulating layer R3 of the multilayer wiring board 10 is embedded. For example, in this embodiment, it is a multilayer ceramic capacitor (MLCC). Then, the size of the chip component 20 is selected from standard products. For example, the so-called "0402" having a size of 0.4 mm×0.2 mm or the so-called “03015” having a size of 0.3 mm×0.15 mm can be used in a plan view.

The overlapped via 30 is formed by overlapping a plurality of laser vias on a straight line, thereby performing interlayer connection in the multilayer wiring board 10. The stacked through hole 30 in this embodiment includes a first stacked through hole 30a, a second stacked through hole 30b, a third stacked through hole 30c, and a fourth stacked through hole 30d, and connects one of the chip components 20 to the electrode terminal and The outer wiring layers formed on both sides of the multilayer wiring board 10 are conductive.

More specifically, the first stacked through hole 30a connects the electrode terminal of one side of the wafer component 20 and the first land 31 to each other, and the first land 31 is provided in the wiring layer L1. The opposite position of the electrode terminals. The second stacked through hole 30b connects the electrode terminal of one side of the wafer component 20 and the second island portion 32 to each other, and the second island portion 32 is provided at a position facing the one electrode terminal in the wiring layer L6. That is, the high-density multilayer substrate 1 electrically connects the wiring layer L1 and the wiring layer L6 as the outer wiring layer to each other through the first stacked through hole 30a, one electrode terminal, and the second stacked through hole 30b.

In addition, the third stacked through hole 30c connects the other electrode terminal of the wafer component 20 and the third island portion 33 to each other, and the third island portion 33 is provided in the wiring layer L1 facing the other electrode terminal. s position. The fourth stacked through hole 30d connects the other electrode terminal of the wafer component 20 and the fourth island portion 34 to each other, and the fourth island portion 34 is provided at a position facing the other electrode terminal in the wiring layer L6 . That is, the high-density multilayer substrate 1 connects the wiring layer L1 and the wiring layer L6 as the outer wiring layer to each other through the third stacked through hole 30c, the other electrode terminal, and the fourth stacked through hole 30d.

That is, the high-density multilayer substrate 1 must be adjacent to each other to form through holes that linearly connect the first island portion 31 and the second island portion 32 and linearly connect the third island portion 33 and the fourth island portion 34 In the case of through-holes, by forming the structure of FIG. 1 composed of the chip parts 20 and the stacked through-holes 30 on the multilayer wiring board 10, conductive paths equivalent to two through-holes are formed at a narrow pitch. The details of the reason why the narrow pitch becomes possible will be described later.

Next, an example of the manufacturing method of the above-mentioned high-density multilayer substrate 1 will be described with reference to FIGS. 2 and 6. In the production of the high-density multilayer substrate 1, first, a component mounting step is performed, and the component mounting step is a subsequent step to mount the chip component 20 on the copper foil 11 that becomes the wiring layer L4. FIG. 2 is a cross-sectional view showing the steps of mounting parts of the high-density multilayer substrate 1 of the first embodiment.

As shown in FIG. 2, the wafer component 20 is mounted on the copper foil 11 via the adhesive 12 printed on the surface of the copper foil 11 as the "first wiring layer". Here, the adhesive 12 is made of an insulating material such as resin, and is provided with a predetermined thickness on the surface of the copper foil 11 where the wafer component 20 is to be arranged.

In more detail, the chip component 20 is composed of a component body 21 and a first electrode terminal 22 and a second electrode terminal 23 that are formed by copper plating on both ends of the component body 21, respectively, as a "pair of electrode terminals". constitute. Then, the wafer component 20 is mounted in such an orientation that both the first electrode terminal 22 and the second electrode terminal 23 are in contact with the adhesive 12.

Next, by laminating a resin layer and a metal layer on the copper foil 11 on which the chip components 20 are mounted, a double-sided board containing the chip components 20 is formed. FIG. 3 is a cross-sectional view showing the steps of forming a double-sided board of the high-density multilayer substrate 1 of the first embodiment.

In the double-sided board formation step, the chip component 20 mounted on the copper foil 11 is buried in the insulating layer R3, and the copper foil 13 as the "second wiring layer" is placed on the surface of the insulating layer R3, thereby forming a double-sided board, a double-sided board The both sides of the insulating layer R3 are each provided with a copper foil 11 and a copper foil 13.

Here, although the insulating layer R3 is, for example, glass epoxy resin formed by impregnating glass cloth with epoxy resin, a prepreg that does not contain glass cloth may also be used. In addition, the insulating layer R3 may be embedded with electronic components not shown in the figure other than the wafer component 20.

Next, a hole-opening step is performed. The hole-opening step is to ensure a conductive path in the chip component 20 contained in the double-sided board. FIG. 4 is a cross-sectional view showing the hole-opening step of the high-density multilayer substrate 1 of the first embodiment.

As shown in FIG. 4, the first electrode terminal 22 and the second electrode terminal 23 of the chip component 20 are formed from each of the copper foil 11 and the copper foil 13 _{by, for example, a CO 2 laser in the opening step}通孔14。 Connecting hole 14. Thereby, the metal surface that becomes the first electrode terminal 22 and the metal surface of the second electrode terminal 23 are exposed. In addition, in the formation of the communicating hole 14, it is preferable to appropriately perform desmear treatment to remove the insulating resin remaining in the hole. In addition, it is preferable to further perform a soft etching process on each electrode terminal exposed by the formation of the via hole 14 to remove oxides and organic substances on the exposed surface. As a result, the surface of the metal on which the coating is not formed is exposed, and the adhesion with the metal deposited in the subsequent plating process is improved, and as a result, the reliability of the electrical connection can be improved.

Next, a plating process is performed to connect the copper foil 11 and the copper foil 13 to the first electrode terminal 22 and the second electrode terminal 23 and to make the copper foil 11 and the copper foil 13 each become the wiring layer L3 and the wiring layer L4. FIG. 5 is a cross-sectional view showing a plating process step of the high-density multilayer substrate 1 of the first embodiment.

In the plating process step, copper plating is performed on the copper foil 11 and the copper foil 13 of the double-sided board and the via hole 14, thereby forming a filled via 15 in which the via hole 14 is filled with copper plating, and The thickness of the copper foil 11 and the copper foil 13 that are connected to the filling hole 15 is increased.

Then, a patterning process for forming a circuit on the copper foil 11 and the copper foil 13 having the increased thickness so as to become the wiring layer L3 and the wiring layer L4 is performed. FIG. 6 is a cross-sectional view showing the patterning step of the high-density multilayer substrate 1 of the first embodiment.

As shown in FIG. 6, in the patterning step, the conductor layer composed of copper foil 11 and copper foil 13 is processed into a desired circuit pattern by, for example, conventional photolithography (photolithography), thereby forming a wiring layer L3 and wiring layer L4.

At this time, in order to form the stacked via 30 in a subsequent step, an island portion 16 is formed in the portion of the wiring layer L3 and the wiring layer L4 that is connected to the filled via 15.

Then, as shown in FIG. 6, a conventional build-up method in which a plurality of resin layers and a plurality of metal layers are laminated is applied to the double-sided wiring board, thereby forming a multilayer wiring board as shown in FIG. 10. That is, the multilayer wiring board 10 can be formed on both sides of the double-sided wiring board as shown in FIG. 6 by a multilayering step. The multilayering step is repeated by the buildup of resin layers, the buildup of copper foil, and the laser through hole. A series of steps of formation, copper plating, and patterning are the addition of wiring layers. In addition, since the conventional technology can be used for multilayering of the substrate, the detailed description is omitted here.

However, in the high-density multilayer substrate 1 of the present invention, in the above-mentioned multilayering step, the above-mentioned stacked through holes 30 are formed at positions corresponding to the first electrode terminal 22 and the second electrode terminal 23 of the wafer component 20. More specifically, the high-density multilayer substrate 1 shown in FIG. 1 connects the first electrode terminal 22 and the second electrode terminal 23 of the wafer component 20 in a straight line each time a layer is added by build-up. The filling through holes 15 are overlapped and formed, thereby forming four stacked through holes 30. Thereby, the high-density multilayer substrate 1 forms two mutually independent conductive paths which respectively conduct the wiring layer L1 and the wiring layer L6 via the first electrode terminal 22 and the second electrode terminal 23.

Next, the effect of the present invention will be explained. FIG. 7 is a cross-sectional view illustrating the function and effect of the high-density multilayer substrate 1 of the first embodiment. FIG. 7 shows the structure of the high-density multilayer substrate 1 similar to that of FIG. 1.

As described above, the high-density multilayer substrate 1 of the first embodiment of the present invention is one of the wafer components 20 and each of the electrode terminals is connected to both outer layer wiring layers. That is, the high-density multilayer substrate 1 is formed by the first stacked through hole 30a, the first electrode terminal 22, and the second stacked through hole 30b to form one through hole, and the third stacked through hole 30c, the second electrode The terminal 23 and the fourth stacked through hole 30d constitute the other through hole.

Here, each of the stacked through holes 30 is formed by a conventional laser through hole forming means, for example, the diameter W1 of the laser through hole can be formed to 75 μm, and the diameter W2 of the island portion 16 is formed to 150 μm. The interval W3 between the islands is formed to be 100 μm.

Then, the high-density multilayer substrate 1 has two through-holes formed by the first electrode terminal 22 and the second electrode terminal 23 of the wafer component 20 arranged at a distance corresponding to the size of the wafer component 20. At this time, the through-holes on both sides are electrically interrupted by the characteristics of the chip component 20 as a capacitor, so that an independent conductive path can be formed that does not cause a short circuit even when the applied potentials are different from each other. . In addition, the capacitor as the chip component 20 is set to have a rated voltage larger than the maximum potential difference assumed between the through-holes of both sides, thereby preventing short circuits more reliably.

With this, for example, when the specification of the wafer component 20 is "0402", the high-density multilayer substrate 1 can suppress the pitch P1 between the through-holes to about 250 μm. In addition, for example, in the case where the specification of the wafer component 20 is "03015", the high-density multilayer substrate 1 can suppress the pitch P1 between the through-holes to about 200 μm.

In addition, since the high-density multilayer substrate 1 does not use a mechanically formed IVH to form the above-mentioned through-holes, it is possible to prevent damage to the insulating layer R3 during the manufacturing process. Therefore, even if the high-density multilayer substrate 1 is arranged around the wafer component 20 with other electronic components, it is possible to suppress the suspicion of migration between these components, and to reduce the suspicion of hindering the narrowing of the pitch.

Next, as a comparative example to the high-density multilayer substrate 1 of the present invention, a prior art using IVH and arranging two through-holes adjacent to each other will be described. FIG. 8 is a cross-sectional view of a prior art multilayer substrate 2 in which through holes including IVH are formed. The internal structure of the multilayer substrate 2 shown in FIG. 8 is different from the above-mentioned high-density multilayer substrate 1 of the present invention at the point that the wiring layer L3 and the wiring layer L4 are electrically connected by IVH.

More specifically, the multi-layer substrate 2 of the prior art is constituted by the first non-through via IVH1 formed in the insulating layer R3 to form one through hole, and is constituted by the second non-through via IVH2 formed in the insulating layer R3 The through hole on the other side. Here, the respective IVH is formed by the following method: the insulating layer R3 with the wiring layer L3 and the wiring layer L4 formed on both sides of the hole is formed with a drill, and copper plating is performed on the inner wall of the hole and inside Space filling resin. In addition, as shown in FIG. 8, the IVH system can directly connect the via hole through the cap plating by forming a cap plating that seals the resin inside the hole.

However, in the prior art multilayer substrate 2 in the formation of the first non-through via IVH1 and the second non-through via IVH2, a mechanical tapping drill is performed by a drill to make the hole diameter reach The diameter W2 of the islands at both ends of the IVH becomes about 300 μm.

In addition, the multilayer substrate 2 of the prior art is prone to migration due to damage to the insulating layer R3 accompanying the formation of IVH. In the case of forming the insulating layer R3 with a general material, in order to prevent the first non-through via IVH1 and the second non-through hole IVH1 and the second non-through The short-circuit between the communication holes IVH2 requires the interval W4 between the two to be set to 0.4 mm or more. In addition, even in the case where the insulating layer R3 is formed of a highly reliable material to improve the insulation, it is still necessary to set the distance W4 between the two to 0.25 mm or more.

Therefore, even if the prior art multilayer substrate 2 suppresses the distance W3 between the islands at both ends of the IVH to 50 μm, it is necessary to set the pitch P2 between the through-holes in order to ensure reliability against short circuits. It is about 350 μm, and other electronic components cannot be placed in the vicinity of the first non-through via IVH1 and the second non-through via IVH2, which hinders the narrowing of the pitch.

As described above, the high-density multilayer substrate 1 of the present invention is embedded in the insulating layer R3 of the multilayer wiring board 10 with the chip component 20 and formed with through-holes. The through-holes pass through the electrode terminals and connections of the chip component 20. The overlapped through holes 30 in these electrode terminals allow the outer wiring layers formed on both sides of the multilayer wiring board 10 to be connected to each other. Therefore, the high-density multilayer substrate 1 can be set at the pitch of the two stacked through holes 30 arranged away from each other in a direction perpendicular to the stacking direction of the multilayer wiring board 10 in accordance with the size of the chip component 20. At this time, since the high-density multilayer substrate 1 does not use the IVH formed by mechanical means to form the above-mentioned through holes, it is possible to prevent damage to the insulating layer R3 in which the wafer component 20 is embedded.

Thereby, even if the high-density multilayer substrate 1 is arranged with other electronic parts around the chip parts 20 constituting the through-holes, the doubts about migration between these parts can be suppressed, and the doubts that hinder the narrowing of the pitch can be reduced. . Therefore, according to the present invention, a high-density multilayer substrate 1 can be provided, which can replace the multilayer substrate 2 formed with through holes containing IVH, can suppress the occurrence of migration and can narrow the pitch.

[Second Embodiment] Next, the second embodiment of the present invention will be explained. Compared with the high-density multilayer substrate 1 of the first embodiment described above, the high-density multilayer substrate 3 of the second embodiment contains the chip components 40 that are resistors and does not have the second stacked through holes 30b and the third stacked through holes. The hole 30c, but instead expands the area of the wiring layers L1 to L6. Hereinafter, the differences from the first embodiment will be described, and the same reference numerals will be given to the components common to the first embodiment, and detailed descriptions will be omitted. In addition, since each step in the manufacturing method of the high-density multilayer substrate 3 is almost the same as that of the high-density multilayer substrate 1 of the first embodiment described above, a detailed description of the manufacturing method is omitted.

FIG. 9 is a cross-sectional view of the high-density multilayer substrate 3 according to the second embodiment of the present invention. The wafer component 40 in the high-density multilayer substrate 3 of the second embodiment is a square wafer component for substrate embedding similarly to the wafer component 20 of the first embodiment described above, and the component shape is the same as that of the wafer component 20. On the other hand, since the wafer component 40 in the second embodiment is a resistor, energization between the first electrode terminal 22 and the second electrode terminal 23 is allowed.

Therefore, the high-density multilayer substrate 3 of the second embodiment is provided with the first island portion 31 formed on the wiring layer L1 and the fourth island portion 34 formed on the wiring layer L6 via the first stack through hole 30a and the wafer component 40 And a through-hole through which the fourth stacked through-hole 30d is conducted. That is, the high-density multilayer substrate 3 is formed with through-holes that are used in the case of seeking conduction between the first island portion 31 and the fourth island portion 34 that are not aligned on a straight line in the substrate stacking direction.

Here, it is preferable that the chip component 40 set the resistance value of the section corresponding to a part of the through hole as the conduction path as low as possible, and in this embodiment, a zero-ohm resistor is used.

In addition, in this embodiment, the size of the wafer component 40 is still selected from standard products. Therefore, in the high-density multilayer substrate 3 of the second embodiment, the interval between the first stacked through hole 30a and the fourth stacked through hole 30d can be set according to the size of the chip component 40. Thereby, the high-density multilayer substrate 3 of the second embodiment is the same as the above-mentioned first embodiment. For example, when the specification of the chip component 40 is "0402", the first stack through hole 30a and the fourth stack through hole can be combined. The pitch P3 between 30d is suppressed to about 250 μm. For example, in the case where the specification of the wafer component 40 is "03015", the pitch P3 can be suppressed to about 200 μm.

In addition, since the high-density multilayer substrate 3 of the second embodiment is similar to the above-mentioned first embodiment, the through-holes are formed without using the IVH formed by mechanical means. Therefore, it is possible to prevent the insulation layer R3 from deteriorating during the manufacturing process. damage. Therefore, in the high-density multilayer substrate 3, even if other electronic components and the like are arranged around the wafer component 40, the fear of migration between these components can be suppressed and the pitch can be narrowed.

Furthermore, in the high-density multilayer substrate 3 of the second embodiment, since one of the upper surface or the lower surface of each electrode terminal of the wafer component 40 is not connected by the laser through hole, it is in a position opposite to this part. The wiring layer L3 and the wiring layer L4 can also be expanded and used effectively.

Next, as a comparative example of the high-density multilayer substrate 3 of the present invention, a description will be given of the previous case where the connection positions of the through-holes formed via IVH and the wiring layer L1 and the wiring layer L6 are not opposed to both sides of the multilayer wiring board 10 technology. FIG. 10 is a cross-sectional view of a prior art multilayer substrate 4 in which through holes including IVH are formed. The internal structure of the multilayer substrate 4 shown in FIG. 10 is different from the above-mentioned high-density multilayer substrate 3 of the present invention at the point that the wiring layer L3 and the wiring layer L4 are electrically connected by IVH.

More specifically, the multilayer substrate 4 of the prior art connects the wiring layer L3 and the wiring layer L4 through the third non-through via IVH3 formed in the insulating layer R3, and is a laminated through hole formed in the insulating layer R1 and the insulating layer R2. , The third non-through via IVH3 and the stacked via holes formed in the insulating layer R4 and the insulating layer R5 are all arranged not on a straight line with respect to the stacking direction of the multilayer wiring board 10.

Here, the third non-through via IVH3 is formed without plating by the following method: the insulating layer R3, in which the wiring layer L3 and the wiring layer L4 have been formed on both sides, is formed with a drill and a hole is formed in the hole The inner wall is copper-plated and the inner space is filled with resin. That is, since the third non-through via IVH3 is a structure that does not directly connect the via via, it is possible to suppress the manufacturing cost by not forming the cap plating.

However, the multi-layer substrate 4 of the prior art is shown by the two dashed ellipses in FIG. 10, and since the vicinity of both ends of the third non-through via IVH3 becomes a wiring prohibition area, it is necessary to form the insulating layer R1 and the insulating layer R2. The distance between the stacked through hole and the third non-through via IVH3, and the distance between the stacked through hole formed in the insulating layer R4 and the insulating layer R5 and the third non-through via IVH3, must be set at P4 It is about 450 μm.

In addition, since the multilayer substrate 4 of the prior art is likely to cause migration due to damage to the insulating layer R3 due to the formation of IVH, it is impossible to arrange other electronic components near the third non-through via IVH3, resulting in a narrower pitch. Hinder. Furthermore, the area of the wiring layer L3 and the wiring layer L4 is also limited due to the above-mentioned wiring prohibition area in the multilayer substrate 4 of the prior art.

As described above, the high-density multilayer substrate 3 of the present invention is embedded in the insulating layer R3 of the multilayer wiring board 10 with the chip component 40 and formed with through-holes. The through-holes pass through the electrode terminals and connections of the chip component 40. The overlapped through holes 30 in these electrode terminals allow the outer wiring layers formed on both sides of the multilayer wiring board 10 to be connected to each other. Therefore, the high-density multilayer substrate 3 can be set at the pitch of the two stacked through holes 30 arranged away from each other in a direction perpendicular to the stacking direction of the multilayer wiring board 10 in accordance with the size of the chip component 40. At this time, since the high-density multilayer substrate 3 does not use the IVH formed by mechanical means to form the through-holes, it is possible to prevent damage to the insulating layer R3 in which the wafer component 40 is embedded.

Thereby, even if the high-density multilayer substrate 3 is provided with other electronic components around the chip components 40 constituting the through-holes, the suspicion of migration between these components can be suppressed, and the suspicion of hindering the narrowing of the pitch can be reduced. . Thus, according to the present invention, it is possible to provide a high-density multilayer substrate 3 that replaces the multilayer substrate 4 formed with through holes containing IVH, suppresses the occurrence of migration, and can narrow the pitch.

Although the description of the embodiments is completed above, the present invention is not limited to the above-mentioned embodiments. For example, in each of the above embodiments, although capacitors or resistors are used as examples of "chip parts", as long as it is a rectangular chip part for embedding in a substrate with electrode terminals at both ends, there is no through hole. Various electronic components can be used to hinder the circuit configuration of the multilayer wiring board 10. In addition, in each of the above-mentioned embodiments, although the form in which one through-hole or two through-holes are formed through one wafer component is illustrated, it is also possible to form more through-holes through a plurality of wafer components to construct a more complicated structure. Circuit composition.

[Practice of the present invention] The first aspect of the present invention is a high-density multilayer substrate to replace the multilayer substrate formed with through-holes containing IVH. The high-density multilayer substrate includes: a multilayer wiring board, which is alternately laminated with a plurality of insulating layers And a plurality of wiring layers; wafer parts are provided with a pair of electrode terminals at both ends, and when the wafer parts are buried in the insulating layer, the orientation is in the following manner: the pair of electrode terminals are laminated with the multilayer wiring board The direction perpendicular to the direction away; and the overlapped through holes are formed by overlapping a plurality of laser through holes to make each of the double-sided outer wiring layers formed on the multilayer wiring board and at least one of the pair of electrode terminals Conduction.

The high-density multilayer substrate of the first aspect of the present invention is a multilayer wiring board in which a chip component is buried in the insulating layer and a through hole is formed. The through hole passes through the electrode terminals of the chip component and is connected to these electrode terminals The stacked through holes, thereby allowing the outer wiring layers formed on both sides of the multilayer wiring board to be connected to each other. Therefore, the high-density multilayer substrate can be set at the pitch of the two stacked through holes arranged away from each other in a direction perpendicular to the stacking direction of the multilayer wiring board in accordance with the size of the chip component. At this time, since the high-density multilayer substrate does not use the IVH formed by mechanical means to form the above-mentioned through-holes, it is possible to prevent damage to the insulating layer in which the wafer parts are embedded. Thereby, according to the high-density multilayer substrate of the first aspect of the present invention, even if other electronic components are arranged around the chip components constituting the through-holes, the fear of migration between these components can be suppressed, thereby reducing the risk of migration between these components. Concerns that hinder the narrowing of the pitch.

The high-density multilayer substrate of the second aspect of the present invention is in the above-mentioned first aspect of the present invention, and the size of the aforementioned chip component is selected from standard products.

According to the second aspect of the present invention, a high-density multi-layer substrate can be provided. By using, for example, existing chip parts based on industrial specifications, in addition to obtaining the cost advantage due to the fact that the chip parts are mass products, It is also possible to reduce the manufacturing cost and improve the yield rate by patterning the process in the process of mounting the chip components and the conduction with the laser through hole.

The high-density multilayer substrate of the third aspect of the present invention is in the above-mentioned first aspect or second aspect of the present invention, the chip component is a capacitor, and each of the pair of electrode terminals is connected to both of the foregoing Outer wiring layer.

According to the third aspect of the present invention, two through-holes that are electrically independent from each other can be arranged at a narrow pitch without short-circuiting, and the two through-holes will be formed on the respective outer layers of both sides of the multilayer wiring board. Wiring layer connection.

The high-density multilayer substrate of the fourth aspect of the present invention is in the third aspect of the present invention described above, and the capacitor is set to have a rated voltage larger than the maximum potential difference contemplated at the pair of electrode terminals.

According to the fourth aspect of the present invention, even in the case where the potentials of the two through-holes are independently changed, since a capacitor with a rated voltage larger than the maximum potential difference contemplated between the two through-holes is selected, The independence of the two conductive paths can be assured by maintaining the potential difference between the two through-holes in accordance with the amount of charge of the capacitor.

The high-density multilayer substrate of the fifth aspect of the present invention is in the above-mentioned first aspect or second aspect of the present invention, the chip component is a resistor, and the outer wiring layer is connected to the pair of electrode terminals, respectively Either party.

According to the fifth aspect of the present invention, even in the case where the connection positions of the through-holes formed in the multilayer wiring board with the outer wiring layer are different from each other on both sides of the multilayer wiring board, it can still be adapted to the chip components. The size is used to set the path of the through hole, and the interval between the connection positions can be set to a narrow pitch.

The high-density multilayer substrate of the sixth aspect of the present invention is the above-mentioned fifth aspect of the present invention, and the aforementioned resistor is a zero-ohm resistor.

According to the sixth aspect of the present invention, it is possible to prevent the voltage drop due to chip components in the through-holes that conduct the double-sided outer wiring layers of the multilayer wiring board.

The seventh aspect of the present invention is a method for manufacturing a high-density multi-layer substrate. The high-density multi-layer substrate is used to replace a multi-layer substrate formed with through holes containing IVH. The method for manufacturing the high-density multi-layer substrate includes: The panel formation step is to embed a wafer component with a pair of electrode terminals on both ends so that the aforementioned pair of electrical terminals are away from the direction perpendicular to the stacking direction and buried in the insulating layer laminated on the first wiring layer, and A second wiring layer is provided on the surface of the insulating layer to form a double-sided board; and a multilayering step is to multilayer the double-sided board to form a multilayer wiring board; in the multilayering step, it is formed on the multilayer wiring board A plurality of laser through holes are overlapped so that each of the double-sided outer wiring layers and at least one of the pair of electrode terminals are electrically connected to form an overlapped through hole.

According to the manufacturing method of the high-density multilayer substrate of the seventh aspect of the present invention, since the insulating layer in the multilayer wiring board is embedded with chip parts and formed with through-holes, the through-holes pass through the electrode terminals and connections of the chip parts. The overlapped through holes in these electrode terminals allow the outer wiring layers formed on both sides of the multilayer wiring board to be connected to each other. Therefore, the high-density multilayer substrate can be set at the pitch of the two stacked through holes arranged away from each other in a direction perpendicular to the stacking direction of the multilayer wiring board in accordance with the size of the chip component. At this time, since the high-density multilayer substrate does not use the IVH formed by mechanical means to form the above-mentioned through-holes, it is possible to prevent damage to the insulating layer in which the wafer parts are embedded. Thereby, according to the manufacturing method of the high-density multilayer substrate of the seventh aspect of the present invention, even if other electronic components are arranged around the chip components constituting the through-holes, the suspicion of migration between these components can be suppressed. Thereby, the doubt that hinders the narrowing of the pitch can be reduced.

The manufacturing method of the high-density multilayer substrate of the eighth aspect of the present invention is in the seventh aspect of the present invention described above, and the size of the aforementioned wafer component is selected from standard products.

According to the eighth aspect of the present invention, a method for manufacturing a high-density multilayer substrate can be provided. By using, for example, existing chip parts based on industrial specifications, in addition to obtaining the cost advantage that the chip parts are mass products In addition, it is possible to reduce the manufacturing cost and improve the yield rate by patterning the process in the process of mounting the chip components and the conduction with the laser through hole.

The manufacturing method of the high-density multilayer substrate of the ninth aspect of the present invention is based on the seventh aspect or the eighth aspect of the present invention. The chip component is a capacitor, and each of the pair of electrode terminals is connected to each Both of the aforementioned outer wiring layers.

According to the ninth aspect of the present invention, two through-holes that are electrically independent from each other can be arranged at a narrow pitch without short-circuiting, and the aforementioned two through-holes will be formed on each of the two sides of the multilayer wiring board. Outer wiring layer connection.

The manufacturing method of the high-density multilayer substrate of the tenth aspect of the present invention is based on the above-mentioned ninth aspect of the present invention, and the capacitor is set to a rated voltage larger than the maximum potential difference contemplated at the pair of electrode terminals .

According to the tenth aspect of the present invention, even in the case where the potentials of the two through-holes vary independently, since a capacitor with a rated voltage greater than the maximum potential difference contemplated between the two through-holes is selected, The independence of the two conductive paths can be assured by maintaining the potential difference between the two through-holes in accordance with the amount of charge of the capacitor.

The manufacturing method of the high-density multilayer substrate of the eleventh aspect of the present invention is based on the seventh or eighth aspect of the present invention. The chip component is a resistor, and the outer wiring layer is connected to the aforementioned Either one of a pair of electrode terminals.

According to the eleventh aspect of the present invention, even when the connection positions of the through holes formed in the multilayer wiring board with the outer wiring layer are different from each other on both sides of the multilayer wiring board, it can still be adapted to the chip parts The size of the through hole sets the path of the through hole, and the interval between the connection positions can be set to a narrow pitch.

The manufacturing method of the high-density multilayer substrate of the twelfth aspect of the present invention is the above-mentioned eleventh aspect of the present invention, and the aforementioned resistor is a zero-ohm resistor.

According to the twelfth aspect of the present invention, it is possible to prevent the voltage drop due to the chip components in the through-holes that conduct the double-sided outer wiring layers of the multilayer wiring board.

1, 3: High-density multilayer substrate 2,4: Multilayer substrate 10: Multilayer wiring board 11, 13: Copper foil 12: Adhesive 14: Connecting hole 15: Fill through holes 16: Island 20, 40: chip parts 21: Component body 22: First electrode terminal 23: second electrode terminal 30: stacked through holes 30a: First stack of through holes 30b: Second stack of through holes 30c: The third stack of through holes 30d: The fourth stack of through holes 31: First Island 32: Second Island 33: Third Island 34: Fourth Island IVH1: The first non-through hole IVH2: The second non-through hole IVH3: The third non-through hole L1~L6: Wiring layer P1, P2, P3, P4: pitch R1~R5: insulating layer W1, W2: diameter W3, W4: interval

Fig. 1 is a cross-sectional view of a high-density multilayer substrate according to a first embodiment of the present invention. [Fig. 2] is a cross-sectional view showing the parts mounting process of the high-density multilayer substrate of the first embodiment. Fig. 3 is a cross-sectional view showing a step of forming a double-sided board of a high-density multilayer substrate according to the first embodiment. [Fig. 4] is a cross-sectional view showing a step of opening a hole in the high-density multilayer substrate of the first embodiment. Fig. 5 is a cross-sectional view showing a plating process step of the high-density multilayer substrate of the first embodiment. Fig. 6 is a cross-sectional view showing the patterning step of the high-density multilayer substrate of the first embodiment. [Fig. 7] is a cross-sectional view illustrating the function and effect of the high-density multilayer substrate of the first embodiment. Fig. 8 is a cross-sectional view of a prior art multilayer substrate in which through-holes including IVH are formed. Fig. 9 is a cross-sectional view of a high-density multilayer substrate according to a second embodiment of the present invention. Fig. 10 is a cross-sectional view of a prior art multilayer substrate in which through holes including IVH are formed.

1: High-density multilayer substrate

10: Multilayer wiring board

20: Chip parts

30: stacked through holes

30a: First stack of through holes

30b: Second stack of through holes

30c: The third stack of through holes

30d: The fourth stack of through holes

31: First Island

32: Second Island

33: Third Island

34: Fourth Island

L1~L6: Wiring layer

R1~R5: insulating layer

Claims (12)

A high-density multi-layer substrate is used to replace a multi-layer substrate formed with through holes including non-through vias. The high-density multi-layer substrate is provided with: Multi-layer wiring boards are alternately laminated with multiple insulating layers and multiple wiring layers; A wafer component is provided with a pair of electrode terminals at both ends, and when the wafer component is embedded in the insulating layer, the orientation is used in the following manner: the pair of electrode terminals are moved away in a direction perpendicular to the stacking direction of the multilayer wiring board; as well as The stacked vias are formed by stacking a plurality of laser vias to connect each of the double-sided outer wiring layers formed on the multilayer wiring board to at least one of the pair of electrode terminals. The high-density multilayer substrate described in claim 1, wherein the size of the aforementioned chip component is selected from standard products. The high-density multilayer substrate according to claim 1 or 2, wherein the chip component is a capacitor, and each of the pair of electrode terminals is connected to both of the outer layer wiring layers. The high-density multilayer substrate described in claim 3, wherein the capacitor is set to have a rated voltage greater than the maximum potential difference contemplated at the pair of electrode terminals. The high-density multilayer substrate according to claim 1 or 2, wherein the chip component is a resistor, and the outer wiring layer is connected to either one of the pair of electrode terminals, respectively. The high-density multilayer substrate according to claim 5, wherein the aforementioned resistor is a zero-ohm resistor. A method for manufacturing a high-density multi-layer substrate. The high-density multi-layer substrate is used to replace a multi-layer substrate formed with through holes including non-through vias. The method for manufacturing the high-density multi-layer substrate includes: The double-sided board formation step is to embed a wafer component with a pair of electrode terminals on both ends so that the aforementioned pair of electric terminals are away from the direction perpendicular to the stacking direction and buried in the insulating layer laminated on the first wiring layer, And disposing a second wiring layer on the surface of the aforementioned insulating layer to form a double-sided board; and The multi-layering step is to multi-layer the aforementioned double-sided board to form a multi-layer wiring board; In the multi-layering step, a plurality of laser through holes are overlapped so that each of the double-sided outer wiring layers formed on the multi-layer wiring board and at least one of the pair of electrode terminals are connected to each other to form overlapped through holes. The method for manufacturing a high-density multilayer substrate as described in claim 7, wherein the size of the aforementioned chip component is selected from standard products. The method for manufacturing a high-density multilayer substrate according to claim 7 or 8, wherein the chip component is a capacitor, and each of the pair of electrode terminals is connected to both of the outer wiring layers. The method for manufacturing a high-density multilayer substrate as recited in claim 9, wherein the capacitor is set to have a rated voltage greater than the maximum potential difference contemplated at the pair of electrode terminals. The method for manufacturing a high-density multilayer substrate according to claim 7 or 8, wherein the chip component is a resistor, and the outer wiring layer is connected to either one of the pair of electrode terminals, respectively. The method for manufacturing a high-density multilayer substrate described in claim 11, wherein the aforementioned resistor is a zero-ohm resistor.

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