JPH0225088A - Multilayer thick film hybrid integrated circuit device - Google Patents
Multilayer thick film hybrid integrated circuit deviceInfo
- Publication number
- JPH0225088A JPH0225088A JP63174543A JP17454388A JPH0225088A JP H0225088 A JPH0225088 A JP H0225088A JP 63174543 A JP63174543 A JP 63174543A JP 17454388 A JP17454388 A JP 17454388A JP H0225088 A JPH0225088 A JP H0225088A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- pattern
- hole
- insulator
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 abstract description 10
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、各種電子・電気機器に使用される多層厚膜混
成集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multilayer thick film hybrid integrated circuit device used in various electronic and electrical equipment.
従来の技術
近年、各種電子電気機器の小型化・低価格化が進む中で
部品の小型化が要求されている。2. Description of the Related Art In recent years, as various electronic and electrical devices have become smaller and lower in price, there has been a demand for smaller parts.
しかし、これには限界があシ、そのため一方では基板の
高密度実装が重要視されてきた。However, there are limits to this, and as a result, high-density mounting on the board has become important.
以下、図面を参照しながら、上述した様な従来の多層厚
膜集積回路について説明を行う。Hereinafter, a conventional multilayer thick film integrated circuit as described above will be explained with reference to the drawings.
第４図は従来例の多層厚膜混成集積回路を示すものであ
り、１はセラミック基板、２は導体（パターン）、３は
絶縁体、４は導体（パターン）である。第４図の上層の
パターン２と下層パターン４を連通さすべく、ホール５
を使って、上層パターン２と下層パターン４をチップ型
抵抗１０で接続させているのが第５図である。FIG. 4 shows a conventional multilayer thick film hybrid integrated circuit, in which 1 is a ceramic substrate, 2 is a conductor (pattern), 3 is an insulator, and 4 is a conductor (pattern). In order to connect the upper layer pattern 2 and the lower layer pattern 4 in FIG.
FIG. 5 shows how the upper layer pattern 2 and the lower layer pattern 4 are connected by a chip type resistor 10 using the above.
発明が解決しようとする課題
しかしながら、前記の様な手段では、高密度実装化とい
う面では不十分であり、基板上でチップ型抵抗１ｏの占
める面積が大きいという問題を有していた。Problems to be Solved by the Invention However, the above-mentioned means are insufficient in terms of high-density packaging, and have the problem that the chip-type resistor 1o occupies a large area on the substrate.
本発明は上記問題点に鑑み、現状の同一面積でよυ高い
高密度実装を実施することのできる多層厚膜混成集積回
路装置を提供するものである。In view of the above-mentioned problems, the present invention provides a multilayer thick film hybrid integrated circuit device that can be mounted at a higher density than the current one in the same area.
課題を解決するだめの手段
そこで、上記問題点を解決するために、本発明の多層厚
膜混成集積回路は、絶縁体３の厚みとホール断面積を利
用し、その間にぺ一°スト状の抵抗体を挿入し、抵抗を
形成することによって、上層パターンと下層パターンを
電気的に結合させるという構成を備えたものである。Means for Solving the Problems Therefore, in order to solve the above problems, the multilayer thick film hybrid integrated circuit of the present invention utilizes the thickness of the insulator 3 and the cross-sectional area of the hole, and inserts a paste-like layer between them. The structure is such that the upper layer pattern and the lower layer pattern are electrically coupled by inserting a resistor and forming a resistor.
作 用
本発明は、上記した構成によって、チップ型抵抗の占め
る面積が減り、その余ったスペースに他の部品を実装す
ることで、現況以上のより高密度な実装が可能となる。Effects According to the present invention, the area occupied by the chip resistor is reduced by the above-described configuration, and by mounting other components in the remaining space, higher density packaging than the current situation is possible.
実施例
以下、本発明の一実施例の多層厚膜混成集積回路につい
て第１図〜第３図を参照しながら説明する。EXAMPLE Hereinafter, a multilayer thick film hybrid integrated circuit according to an example of the present invention will be described with reference to FIGS. 1 to 3.
第１図は、本発明の一実施例における多層厚膜混成集積
回路の完成時の構成を示すものである。FIG. 1 shows the completed configuration of a multilayer thick film hybrid integrated circuit according to an embodiment of the present invention.
第２図に示すように、基板１上に導体（パターン）４、
絶縁体３を順次積層形成し、絶縁体３には導体４に連通
するホール６を設ける。ホール断面積８、厚ｄの前記ホ
ール６が、第３図に示すように任意の体積固有抵抗率を
もった導体成分とガラス成分とビフィクル成分によって
形成されたペースト状の抵抗体６によって埋められ、下
層パターン４に接する。一方、その抵抗体６に接するべ
く上層パターン２を絶縁体３上に形成することによシ、
上層パターン２と下層パターン４が抵抗体６によシ接続
される。抵抗体６の抵抗値は絶縁体厚ｄ、ホール断面積
Ｓ１抵抗体６のシート抵抗値によって決定する。As shown in FIG. 2, a conductor (pattern) 4,
Insulators 3 are sequentially laminated, and holes 6 communicating with conductors 4 are provided in the insulators 3. The hole 6 having a hole cross-sectional area of 8 and a thickness of d is filled with a paste-like resistor 6 formed of a conductor component, a glass component, and a bificle component having an arbitrary specific volume resistivity, as shown in FIG. , is in contact with the lower layer pattern 4. On the other hand, by forming the upper layer pattern 2 on the insulator 3 in contact with the resistor 6,
The upper layer pattern 2 and the lower layer pattern 4 are connected by a resistor 6. The resistance value of the resistor 6 is determined by the insulator thickness d, the hole cross-sectional area S1, and the sheet resistance value of the resistor 6.
以上の様に構成された結果、チップ型抵抗１０が占める
割合が軽減される。As a result of the above configuration, the proportion occupied by the chip type resistor 10 is reduced.
発明の効果
本発明により、従来のチップ型抵抗の占める割合が節約
された面積外だけ、他の部品を実装することができ、高
密度実装化が可能になる。Effects of the Invention According to the present invention, other components can be mounted only outside the area where the proportion occupied by the conventional chip-type resistor is saved, and high-density packaging becomes possible.
なお、本実施例では片面２層を取り上げ説明したが両面
２層以上の多層厚膜集積回路としてでも良い。Although this embodiment has been described with two layers on one side, it may be a multilayer thick film integrated circuit with two or more layers on both sides.
その場合、孔は上層パターンと下層パターンを結ぶ孔（
ホー）ｖ ）とスルーホールを加えた孔の構成とするも
のである。In that case, the hole is a hole connecting the upper layer pattern and the lower layer pattern (
The hole configuration is the addition of a through hole and a through hole.
第１図は本発明の一実施例における多層厚膜混成集積回
路装置の断面図、第２図、第３図はその製造過程を説明
するための断面図、第４図は多層基板の断面図、第５図
は従来例の多層厚膜混成集積回路の断面図である。
１・・・・・・基板、２・・・・・・導体（パターン）
、３・・・・・・絶縁体、４・・・・・・導体（パター
ン）、５・・・・・・ボール、θ・・・・・・抵抗体。
代理人の氏名 弁理士 粟 野 重 孝 ほか１名派
派
ｉが
法
派
Ｕ）
稼FIG. 1 is a sectional view of a multilayer thick film hybrid integrated circuit device according to an embodiment of the present invention, FIGS. 2 and 3 are sectional views for explaining the manufacturing process, and FIG. 4 is a sectional view of a multilayer board. , FIG. 5 is a sectional view of a conventional multilayer thick film hybrid integrated circuit. 1...Substrate, 2...Conductor (pattern)
, 3... Insulator, 4... Conductor (pattern), 5... Ball, θ... Resistor. Name of agent: Patent attorney Shigetaka Awano and 1 other person
Claims (1)
により多層に配線回路を印刷形成し、前記配線パターン
の任意の第１パターンと前記第１パターンに隣接する上
・下層パターン間の絶縁層に各々の層のパターンを連通
すべくホールを設け、前記ホールに抵抗体を埋め込み、
各層の配線パターンを抵抗体で電気的に結合するように
したことを特徴とする多層厚膜混成集積回路装置。A multilayer wiring circuit is printed by stacking wiring patterns and insulators alternately on a substrate, and each insulating layer is formed between an arbitrary first pattern of the wiring pattern and upper and lower layer patterns adjacent to the first pattern. A hole is provided to connect the layer patterns, a resistor is embedded in the hole,
A multilayer thick film hybrid integrated circuit device characterized in that the wiring patterns of each layer are electrically connected by resistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174543A JPH0225088A (en) | 1988-07-13 | 1988-07-13 | Multilayer thick film hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174543A JPH0225088A (en) | 1988-07-13 | 1988-07-13 | Multilayer thick film hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0225088A true JPH0225088A (en) | 1990-01-26 |
Family
ID=15980385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63174543A Pending JPH0225088A (en) | 1988-07-13 | 1988-07-13 | Multilayer thick film hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0225088A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002185565A (en) * | 2000-12-12 | 2002-06-28 | Dainippon Printing Co Ltd | Multilayer print |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119593A (en) * | 1986-11-07 | 1988-05-24 | 松下電器産業株式会社 | Printed board |
| JPS63168074A (en) * | 1986-12-27 | 1988-07-12 | 株式会社富士通ゼネラル | Method of forming resistor on electronic circuit substrate |
-
1988
- 1988-07-13 JP JP63174543A patent/JPH0225088A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119593A (en) * | 1986-11-07 | 1988-05-24 | 松下電器産業株式会社 | Printed board |
| JPS63168074A (en) * | 1986-12-27 | 1988-07-12 | 株式会社富士通ゼネラル | Method of forming resistor on electronic circuit substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002185565A (en) * | 2000-12-12 | 2002-06-28 | Dainippon Printing Co Ltd | Multilayer print |
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