JPH1065342A - Multilayer circuit board and manufacture thereof - Google Patents

Multilayer circuit board and manufacture thereof

Info

Publication number
JPH1065342A
JPH1065342A JP9193475A JP19347597A JPH1065342A JP H1065342 A JPH1065342 A JP H1065342A JP 9193475 A JP9193475 A JP 9193475A JP 19347597 A JP19347597 A JP 19347597A JP H1065342 A JPH1065342 A JP H1065342A
Authority
JP
Japan
Prior art keywords
circuit board
resistor
multilayer circuit
resistors
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9193475A
Other languages
Japanese (ja)
Inventor
Yuji Otani
祐司 大谷
Takashi Nagasaka
長坂  崇
Yutaka Fukuda
豊 福田
Hideki Nakagawara
英樹 中川原
Hideki Tanigawa
秀樹 谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP9193475A priority Critical patent/JPH1065342A/en
Publication of JPH1065342A publication Critical patent/JPH1065342A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize a miniaturized board by reducing the occupied areas of passive elements, such as resistors and the like in a multilayer circuit board. SOLUTION: In a thick-film multilayer circuit board on which alumina substrate 25, wiring conductors 26 and insulators 28, 31 are alternately formed by printing, resistors are formed as follows. In the insulator 28, via holes 27 for wiring connection between circuit substrates are provided. Then in this via hole, a resistor 30 is built. Thereby, by reducing the occupied areas of passive elements such as a resistor and the like on the layer 31, miniaturizing the overall size of a board is enabled.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は多層回路基板およ
びその製造方法に関するものである。
The present invention relates to a multilayer circuit board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来の多層回路基板(多層ハイブリッド
IC)においては、図4に示すように受動素子である厚
膜抵抗体1は多層よりなる基板2の表面においてターミ
ナルとなる導体3、4間に形成される。
2. Description of the Related Art In a conventional multi-layer circuit board (multi-layer hybrid IC), as shown in FIG. 4, a thick film resistor 1 as a passive element is connected between conductors 3 and 4 serving as terminals on the surface of a multi-layer board 2. Formed.

【0003】[0003]

【発明が解決しようとする課題】ところが、この厚膜抵
抗体1の占有面積は導体3、4を含めて少なくとも1.
6mm□程度必要となっている。従って、このような厚
膜抵抗体1を使用する場合において抵抗体の数が多いと
きには基板サイズの小型化(高密度化)に対応できない
という問題があった。
However, the area occupied by the thick film resistor 1 including the conductors 3 and 4 is at least 1.
About 6 mm square is required. Therefore, when such a thick film resistor 1 is used, when the number of resistors is large, there is a problem that it is not possible to cope with a reduction in the size of the substrate (higher density).

【0004】この発明の目的は上記課題に鑑み抵抗体等
の受動素子の占有面積を少なくし基板の小型化を図るこ
とができる多層回路基板およびその製造方法を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer circuit board capable of reducing the area occupied by passive elements such as resistors and reducing the size of the board, and a method of manufacturing the same.

【0005】[0005]

【課題を解決するための手段】本発明は、上記目的に鑑
みてなされたものであり、請求項1によれば、層間の配
線接続を行うためのホール部に抵抗体若しくは誘電体が
組込まれ、層の表面においてはその抵抗体等の占有面積
は”0”となる。よって、層上の抵抗体等の受動素子の
占有面積を少なくし基板の小型化を図ることができる優
れた効果を発揮する。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned object, and according to the first aspect, a resistor or a dielectric is incorporated in a hole portion for connecting a wiring between layers. On the surface of the layer, the area occupied by the resistor and the like is "0". Therefore, an excellent effect of reducing the area occupied by passive elements such as resistors on the layer and reducing the size of the substrate is exhibited.

【0006】また、請求項2によれば、請求項1の効果
に加え、ホール部に充填した抵抗体若しくは誘電体を積
層後のグリーンシートと一括して焼成することができる
という優れた効果を発揮する。
According to the second aspect, in addition to the effect of the first aspect, there is an excellent effect that the resistor or the dielectric filled in the hole can be fired together with the laminated green sheet. Demonstrate.

【0007】[0007]

【発明の実施の形態】以下、この発明を具体化した一実
施の形態を図面に従って説明する。図2(a)〜(d)
はその製造工程を示す基板の断面図であり、この実施の
形態では3層構造とし最も上層に抵抗体を配置する場合
について以下述べる。まず、図2(a)に示すように、
3枚のアルミナのグリーンシート11、12、13を用
意し、最も上層に位置させるグリーンシート11の所定
の位置にビアホール(穴)14、15、16を形成す
る。そして、図2(b)に示すようにスクリーン印刷に
てビアホール15に周知の手法により導体ペースト17
を充填する。次いで、ビアホール14、16に抵抗体ペ
ースト18、19をスクリーン印刷法にて充填する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIGS. 2A to 2D
Is a cross-sectional view of a substrate showing a manufacturing process thereof. In this embodiment, a case where a three-layer structure is adopted and a resistor is arranged in the uppermost layer will be described below. First, as shown in FIG.
Three alumina green sheets 11, 12, and 13 are prepared, and via holes (holes) 14, 15, and 16 are formed at predetermined positions of the uppermost green sheet 11. Then, as shown in FIG. 2B, the conductive paste 17 is formed in the via hole 15 by screen printing using a known method.
Fill. Next, the via holes 14 and 16 are filled with resistor pastes 18 and 19 by a screen printing method.

【0008】次に、図2(c)に示すように、同じくス
クリーン印刷にて各グリーンシート11、12、13の
表面に所定の導体ペースト20、21のパターンを印刷
する。そして、図2(d)に示すように、各グリーンシ
ート11、12、13を重ねた状態で加圧し圧着する。
その後、圧着した各グリーンシート11、12、13を
焼成する。
Next, as shown in FIG. 2C, a predetermined pattern of conductive pastes 20, 21 is printed on the surfaces of the green sheets 11, 12, 13 by screen printing. Then, as shown in FIG. 2D, the green sheets 11, 12, and 13 are pressed and pressed in a state of being stacked.
Thereafter, the pressed green sheets 11, 12 and 13 are fired.

【0009】その結果、図1に示すような多層よりなる
アルミナ基板22、23、24の層間に配線接続を施す
ためのビアホール部(14、16)に抵抗体(18、1
9)を組込んだ多層回路基板が形成される。この多層回
路基板においては、通常の層間配線接続を行うビアホー
ル部(14、16)に抵抗体(18、19)が組込ま
れ、基板22の表面においてはその抵抗体の占有面積
は”0”となり、抵抗体の数が多くてもの占有面積を少
なくし基板の小型化を図ることができることとなる。
As a result, the resistors (18, 1) are formed in the via holes (14, 16) for making wiring connections between the multilayer alumina substrates 22, 23, 24 as shown in FIG.
A multilayer circuit board incorporating 9) is formed. In this multilayer circuit board, resistors (18, 19) are incorporated in via holes (14, 16) for performing normal interlayer wiring connection, and the area occupied by the resistors on the surface of the substrate 22 is "0". In addition, even if the number of resistors is large, the occupied area can be reduced and the size of the substrate can be reduced.

【0010】即ち、従来では厚膜抵抗体1の占有面積は
導体3、4を含めて少なくとも1.6mm□程度必要と
なっていたが、その抵抗体の占有領域をなくすことがで
きることとなる。又、ビアホール部の抵抗体形成プロセ
スは従来のビアホール部への導体充填工程を抵抗体充填
工程に置換えるだけでよいので、従来の工程に特別の工
程を付加することなく容易に行うことができる。
That is, conventionally, the area occupied by the thick film resistor 1 needs to be at least about 1.6 mm □ including the conductors 3 and 4, but the area occupied by the resistor can be eliminated. In addition, the process of forming the resistor in the via hole portion can be easily performed without adding a special process to the conventional process, since it is only necessary to replace the conventional process of filling the via hole portion with the conductor. .

【0011】尚、この発明は上記実施の形態に限定され
るものでなく、上記実施の形態ではビアホール部に受動
素子として抵抗体を組込んだが誘電体をスクリーン印刷
法で組込んでもよい。又、上記実施の形態では各グリー
ンシート11、12、13を重ねることにより多層化し
たが、図3に示すように、導体ペーストと絶縁ペースト
を交互に印刷する方法により多層化しそのビアホール部
に抵抗体等を組込んでもよい。
The present invention is not limited to the above embodiment. In the above embodiment, a resistor is incorporated as a passive element in the via hole, but a dielectric may be incorporated by screen printing. In the above-described embodiment, the green sheets 11, 12, and 13 are stacked to form a multilayer. However, as shown in FIG. 3, the conductive paste and the insulating paste are alternately printed to form a multilayer, and the via holes have resistance. A body or the like may be incorporated.

【0012】即ち、1枚の焼成したアルミナ基板25上
に導体ペースト26のパターンを形成し、次に、そのア
ルミナ基板25上に導体ペースト26に連通するビアホ
ール27を有する絶縁ペースト(ガラスペーストあるい
はガラスセラミックペースト)28を印刷する。その
後、ビアホール27に導体ペースト29や抵抗体ペース
ト30をスクリーン印刷法により充填する。
That is, a pattern of a conductive paste 26 is formed on one baked alumina substrate 25, and then an insulating paste (glass paste or glass paste) having via holes 27 communicating with the conductive paste 26 is formed on the alumina substrate 25. (Ceramic paste) 28 is printed. After that, the via holes 27 are filled with the conductor paste 29 and the resistor paste 30 by a screen printing method.

【0013】さらに、同様に絶縁ペースト31により多
層化し、その後焼成することにより製造するようにして
もよい。さらに、基板材料もアルミナに限定されるもの
ではなく、例えばガラスセラミックや、あるいはガラス
エポキシ等の樹脂材料であってもよい。又、この発明の
構造は両面スルーホール基板におけるスルーホール部に
も適用できる。
Further, similarly, it may be manufactured by multi-layering with the insulating paste 31 and then firing. Further, the substrate material is not limited to alumina, but may be a resin material such as glass ceramic or glass epoxy. Further, the structure of the present invention can be applied to a through-hole portion in a double-sided through-hole substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を具体化した多層回路基板の断面図。FIG. 1 is a sectional view of a multilayer circuit board embodying the present invention.

【図2】(a)は多層回路基板の製造工程を説明するた
めの断面図。(b)は多層回路基板の製造工程を説明す
るための断面図。(c)は多層回路基板の製造工程を説
明するための断面図。(d)は多層回路基板の製造工程
を説明するための断面図。
FIG. 2A is a cross-sectional view for explaining a manufacturing process of a multilayer circuit board. (B) is sectional drawing for demonstrating the manufacturing process of a multilayer circuit board. (C) is sectional drawing for demonstrating the manufacturing process of a multilayer circuit board. (D) is sectional drawing for demonstrating the manufacturing process of a multilayer circuit board.

【図3】別例の多層回路基板の断面図。FIG. 3 is a cross-sectional view of another example of a multilayer circuit board.

【図4】従来の多層回路基板の断面図。FIG. 4 is a cross-sectional view of a conventional multilayer circuit board.

【符号の説明】[Explanation of symbols]

14、16、30 ビアホール 18、19 抵抗体(抵抗体ペースト) 22、23、24 アルミナ基板 27 ビアホール 28、31 絶縁ペースト 14, 16, 30 Via hole 18, 19 Resistor (resistor paste) 22, 23, 24 Alumina substrate 27 Via hole 28, 31 Insulating paste

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中川原 英樹 愛知県刈谷市昭和町1丁目1番地 株式会 社デンソー内 (72)発明者 谷川 秀樹 愛知県刈谷市昭和町1丁目1番地 株式会 社デンソー内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideki Nakagawara 1-1-1, Showa-cho, Kariya-shi, Aichi Pref. Inside

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に配線導体と絶縁体を交互に印刷
形成してなる多層回路基板において、 前記絶縁体には回路基板の層間の配線接続を施すための
ホール部が設けられており、該ホール部に抵抗体若しく
は誘電体を組込んだことを特徴とする多層回路基板。
1. A multi-layer circuit board in which wiring conductors and insulators are alternately printed on a substrate, wherein the insulators are provided with holes for making wiring connections between layers of the circuit board. A multilayer circuit board, wherein a resistor or a dielectric is incorporated in the hole.
【請求項2】 配線導体が施された複数のグリーンシー
トを積層後焼成してなる多層回路基板の製造方法におい
て、 前記グリーンシートの所定位置に回路基板の層間の配線
接続を施すためのホール部を形成し、該ホール部に抵抗
体若しくは誘電体を充填し、該抵抗体若しくは誘電体を
前記積層後のグリーンシートと一括して焼成することを
特徴とする多層回路基板の製造方法。
2. A method for manufacturing a multilayer circuit board, comprising laminating and firing a plurality of green sheets to which wiring conductors have been applied, wherein a hole portion for making a wiring connection between layers of the circuit board at a predetermined position of the green sheet. Forming a hole, filling the hole portion with a resistor or a dielectric, and firing the resistor or the dielectric together with the laminated green sheet at a time.
JP9193475A 1997-07-18 1997-07-18 Multilayer circuit board and manufacture thereof Pending JPH1065342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9193475A JPH1065342A (en) 1997-07-18 1997-07-18 Multilayer circuit board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9193475A JPH1065342A (en) 1997-07-18 1997-07-18 Multilayer circuit board and manufacture thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP63129372A Division JP2712295B2 (en) 1988-05-26 1988-05-26 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH1065342A true JPH1065342A (en) 1998-03-06

Family

ID=16308645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9193475A Pending JPH1065342A (en) 1997-07-18 1997-07-18 Multilayer circuit board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH1065342A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320846C (en) * 2002-12-06 2007-06-06 松下电器产业株式会社 Circuit board and its manufacturing method
CN117641718A (en) * 2024-01-26 2024-03-01 苏州敏芯微电子技术股份有限公司 Circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320846C (en) * 2002-12-06 2007-06-06 松下电器产业株式会社 Circuit board and its manufacturing method
CN117641718A (en) * 2024-01-26 2024-03-01 苏州敏芯微电子技术股份有限公司 Circuit board
CN117641718B (en) * 2024-01-26 2024-04-12 苏州敏芯微电子技术股份有限公司 Circuit board

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