JPH03136337A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH03136337A JPH03136337A JP1275293A JP27529389A JPH03136337A JP H03136337 A JPH03136337 A JP H03136337A JP 1275293 A JP1275293 A JP 1275293A JP 27529389 A JP27529389 A JP 27529389A JP H03136337 A JPH03136337 A JP H03136337A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- land
- hybrid integrated
- circuit device
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 239000012212 insulator Substances 0.000 claims abstract description 4
- 230000010354 integration Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、混成集積回路装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a hybrid integrated circuit device.
従来の技術
従来の混成集積回路装置において、ベアチップ搭載・組
立・特にワイヤーボンディングランドは第３図及び、第
４図のようにして行われていた０第３図において、９は
基板、１ｏは導体パターン、１１はワイヤー接続のため
のワイヤランド、１２はペアチップ搭載のためのベアチ
ップ用ダイランドである。また、第４図はその断面図で
ある。2. Prior Art In conventional hybrid integrated circuit devices, bare chip mounting, assembly, and especially wire bonding land are carried out as shown in FIGS. 3 and 4. In FIG. 3, 9 is a substrate, and 1o is a conductor. The pattern, 11 is a wire land for wire connection, and 12 is a bare chip die land for mounting a pair of chips. Further, FIG. 4 is a sectional view thereof.
発明が解決しようとする課題
従来のワイヤーボンディングのランド形成方法では、第
３図、第４図に示す通り、導体パターン１０、ワイヤラ
ンド１１、ベアチップ用ダイランド１２が同一の導体で
形成されるため、ベアチップ用ダイランド１２０部分に
は別の導体パターンが形成できず、基板面積を有効に利
用することが出来ず、小型化が困難であるという問題を
有してい氏。Problems to be Solved by the Invention In the conventional wire bonding land forming method, as shown in FIGS. 3 and 4, the conductor pattern 10, the wire land 11, and the bare chip die land 12 are formed of the same conductor. Another problem is that a separate conductor pattern cannot be formed in the die land 120 portion for bare chips, and the board area cannot be used effectively, making miniaturization difficult.
本発明は、混成集積回路装置の集積度を高めることを目
的とするものである。An object of the present invention is to increase the degree of integration of a hybrid integrated circuit device.
課題を解決するための手段
この問題点を解決するために本発明は、混成集積回路装
置のワイヤボンディングランドを形成する際にベアチッ
プダイランドを絶縁体とすることにより、その下層に、
導体パターンを形成したものである。Means for Solving the Problems In order to solve this problem, the present invention makes the bare chip die land an insulator when forming the wire bonding land of the hybrid integrated circuit device, so that the underlying layer is
A conductor pattern is formed.
作用
この形成方法により、混成集積回路装置におけるペアチ
ップダイランドの下層を有効に利用することが出来、混
成集積回路装置の集積度を高めることができる。Effect: This formation method makes it possible to effectively utilize the lower layer of the paired chip die land in the hybrid integrated circuit device, thereby increasing the degree of integration of the hybrid integrated circuit device.
実施例
以下、本発明による混成集積回路装置の一実施例を図面
とともに説明する。Embodiment Hereinafter, one embodiment of a hybrid integrated circuit device according to the present invention will be described with reference to the drawings.
第１図において、１はアルミナ材等から成る基板、２は
ベアチップ２１を搭載するためのペアチップ用ダイラン
ド、３は銀パラジウムあるいは銀・鋼材で成る導体パタ
ーン、４はベアチップ２１を電気的に接続するためのワ
イヤランドである。そして具体的な製造方法の例として
は、基板１の片面あるいは両面に導体材料を印刷・焼成
にて導体パターン３やワイヤランド４を形成した後、ペ
アチップ２１の必要とする面積で、ガラス材等の絶縁材
料を印刷・焼成して、ベアチップ用ダイランド２を一部
の導体パターン３の上に形成する。しかる後、ダイラン
ド２上に所定のペアテップ２１を搭載し、金あるいはア
ルミ材のワイヤにより、ベアチップ２１とワイヤランド
４を接続（図示せず）して、所定の電子回路を構成し、
混成集積回路とするのである。In FIG. 1, 1 is a substrate made of alumina material, etc., 2 is a pair chip die land for mounting the bare chip 21, 3 is a conductor pattern made of silver-palladium or silver/steel, and 4 is a part that electrically connects the bare chip 21. It is a wire land for. As an example of a specific manufacturing method, after forming the conductive pattern 3 and wire lands 4 by printing and baking a conductive material on one or both sides of the substrate 1, the area required for the pair chip 21 is formed using a glass material, etc. A bare chip die land 2 is formed on a part of the conductor pattern 3 by printing and firing an insulating material. After that, a predetermined pair tip 21 is mounted on the die land 2, and the bare chip 21 and the wire land 4 are connected with gold or aluminum wire (not shown) to form a predetermined electronic circuit.
It is a hybrid integrated circuit.
なお、第２図は、その断面図を示している。Note that FIG. 2 shows a sectional view thereof.
発明の効果
以上のように、本発明によれば、混成集積回路装置にお
いて、ワイヤボンディングランドを形成する場合、ベア
チップ用ダイランドを絶縁体とすることにより導体パタ
ーン上に重ねて設けられるから、決められた基板面積を
最大限に活用でき、そして導体パターンによりシールド
することも出来るなど、混成集積回路装置の集積度を高
め、かつ性能の安定化を図ることができる。Effects of the Invention As described above, according to the present invention, when forming a wire bonding land in a hybrid integrated circuit device, the die land for bare chip is formed as an insulator so that it is provided over the conductor pattern. This makes it possible to make maximum use of the board area and to shield it with a conductor pattern, thereby increasing the degree of integration of the hybrid integrated circuit device and stabilizing its performance.
第１図は本発明の一実施例における混成集積回路装置の
要部を示す平面図、第２図は同断面図、第３図は従来の
混成集積回路の要部を示す平面図、第４図は同断面図で
ある。
１・・・・・・基板、２・・・・・・ベアチップ用ダイ
ランド、３・・・・・・導体パターン、４・・・・・・
ワイヤランド、２１・・・・・・ベアチップ。
−−−
２−°−
３−・−
４”°−
蟇 叢
ペアチップＦＩ５クイ５ンド
４停パターン
フイＴ’ ５ ｙド
第２図
第
３
図
第
図FIG. 1 is a plan view showing the main parts of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the same, FIG. 3 is a plan view showing the main parts of a conventional hybrid integrated circuit, and FIG. The figure is a sectional view of the same. 1... Board, 2... Die land for bare chip, 3... Conductor pattern, 4...
Wireland, 21...Bear Chip. --- 2-°- 3-・- 4"°- Toad Pair Chip FI5 Quiet 5nd 4 Stop Pattern FiT' 5yD Fig. 2 Fig. 3 Fig. Fig.
Claims (1)
縁体により形成するとともに、そのダイランド上にベア
チップを搭載し、かつ前記導体パターンの一部のワイヤ
ランドにベアチップをボンデングにより接続した混成集
積回路装置。A hybrid integrated circuit device in which a die land for a bare chip is formed of an insulator on a part of the conductor pattern, a bare chip is mounted on the die land, and the bare chip is connected to a part of the wire land of the conductor pattern by bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1275293A JP2743524B2 (en) | 1989-10-23 | 1989-10-23 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1275293A JP2743524B2 (en) | 1989-10-23 | 1989-10-23 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03136337A true JPH03136337A (en) | 1991-06-11 |
| JP2743524B2 JP2743524B2 (en) | 1998-04-22 |
Family
ID=17553414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1275293A Expired - Fee Related JP2743524B2 (en) | 1989-10-23 | 1989-10-23 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2743524B2 (en) |
-
1989
- 1989-10-23 JP JP1275293A patent/JP2743524B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2743524B2 (en) | 1998-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |