JPH03110768A - Chip for connecting wiring pattern - Google Patents
Chip for connecting wiring patternInfo
- Publication number
- JPH03110768A JPH03110768A JP24964589A JP24964589A JPH03110768A JP H03110768 A JPH03110768 A JP H03110768A JP 24964589 A JP24964589 A JP 24964589A JP 24964589 A JP24964589 A JP 24964589A JP H03110768 A JPH03110768 A JP H03110768A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- strip conductor
- wiring pattern
- electrode
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims description 27
- 230000000694 effects Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000013011 mating Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
回路基板の一面で交叉する配線パターンの一方の分断さ
れた配線パターンを他方の分断されない配線パターンを
跨いで接続する配線パターン接続用チップの構造に関し
、
交叉する信号間の漏話と減衰をできるだけ軽減すること
を目的とし、
上下に重ね圧着される誘電体基板間の全面にシールド接
地導体を介挿し、下側誘電体基板の実装面に接地用電極
と信号用電極を設け、上側誘電体基板の表面中央にスト
リップ導体を設けるとともに該ストリップ導体の両側に
接地導体を設け、該接地導体とシールド接地導体とを前
記接地用電極に、ストリップ導体を前記信号用電極にそ
れぞれ前記両誘電体基板の側面を経て接続するように構
成する。[Detailed Description of the Invention] [Summary] This invention relates to the structure of a wiring pattern connecting chip that connects one divided wiring pattern of wiring patterns that intersect on one surface of a circuit board by straddling the other undivided wiring pattern. In order to reduce crosstalk and attenuation between signals as much as possible, a shield grounding conductor is inserted between the dielectric substrates that are stacked and crimped on top of each other, and a grounding electrode and signal conductor are inserted on the mounting surface of the lower dielectric substrate. A strip conductor is provided at the center of the surface of the upper dielectric substrate, and ground conductors are provided on both sides of the strip conductor, and the ground conductor and the shield ground conductor serve as the ground electrode, and the strip conductor serves as the signal electrode. The dielectric substrates are connected to each other through the side surfaces of both dielectric substrates.
本発明は回路基板の一面で交叉する配線パターンの一方
の分断された配線パターンを他方の分断されない配線パ
ターンを跨いで接続する配線パターン接続用チップに関
する。The present invention relates to a wiring pattern connecting chip that connects one divided wiring pattern of wiring patterns that intersect on one surface of a circuit board by straddling the other undivided wiring pattern.
高周波回路においては、交叉する信号線が多い複雑な回
路の場合、信号線間の漏話をできるだけ防止するため、
信号線（配線パターン）を電気的に独立させる多層構造
とする場合が多いが、単に一部の信号配線パターンが交
叉するような場合、低製造コストの観点から多層構造と
はせず、単層構造としている。即ち、回路基板の表面上
で信号配線パターンを交叉させ一方の分断された信号線
をワイヤボンディングなどにより接続している。In high-frequency circuits, in the case of complex circuits with many intersecting signal lines, in order to prevent crosstalk between signal lines as much as possible,
In many cases, a multilayer structure is used to make signal lines (wiring patterns) electrically independent, but in cases where some signal wiring patterns simply intersect, a single layer structure is used instead of a multilayer structure to reduce manufacturing costs. It has a structure. That is, the signal wiring patterns are crossed on the surface of the circuit board, and one of the separated signal lines is connected by wire bonding or the like.
ところが、高周波回路ではこのワイヤが長いため信号間
の漏話や信号の減衰が生じる問題があるこのような状況
から交叉する高周波信号線の交叉部分の漏話と減衰をで
きるだけ軽減することのできる接続構造が要望されてい
る。However, in high-frequency circuits, the long wires cause problems such as crosstalk between signals and signal attenuation.In response to this situation, a connection structure that can reduce crosstalk and attenuation as much as possible at the intersection of high-frequency signal lines has been developed. It is requested.
従来、高周波回路基板２０は、第９図の要部斜視図に示
すように信号配線パターン２１の周囲に短絡防止の隙間
を開けて残る全面に接地配線パターン・２２を設は電気
的に独立させ、信号配線パターン２１の一部交叉する信
号配線パターン２１−１．２１−２の一方の分断された
信号配線パターン２１−１間を他方の分断されない信号
配線パターン２１−２を跨いでワイヤ２３でボンディン
グ接続している。Conventionally, the high-frequency circuit board 20 has a ground wiring pattern 22 that is electrically independent by leaving a gap around the signal wiring pattern 21 to prevent short circuits, as shown in the perspective view of the main part of FIG. , a wire 23 is connected between one of the signal wiring patterns 21-1 and 21-2 which partially intersects the signal wiring pattern 21, straddling the other undivided signal wiring pattern 21-1. It is connected by bonding.
しかしながら、このような上記接続構造によれば、接続
するワイヤが空間に長く伸びてアンテナの役目を果たし
信号間の漏話と信号の減衰が生じるといった問題があっ
た。However, such a connection structure has a problem in that the connecting wire extends long into the space and functions as an antenna, causing crosstalk between signals and signal attenuation.
上記問題点に鑑み、本発明は回路基板の一面で交叉する
信号間の漏話と減衰をできるだけ軽減することのできる
配線パターン接続用チップを提供することを目的とする
。In view of the above problems, it is an object of the present invention to provide a wiring pattern connection chip that can reduce as much as possible the crosstalk and attenuation between signals that intersect on one surface of a circuit board.
上記目的を達成するために、本発明の配線パターン接続
用チップにおいては、上下に重ね圧着される誘電体基板
間の全面にシールド接地導体を介挿し、下側誘電体基板
の実装面に接地用電極と信号用電極を設け、上側誘電体
基板の表面中央にストリップ導体を設けるとともに該ス
トリップ導体の両側に接地導体を設け、該接地導体とシ
ールド接地導体とを前記接地用電極に、ストリップ導体
を前記信号用電極にそれぞれ前記両誘電体基板の側面を
経て接続するように構成する。In order to achieve the above object, in the wiring pattern connection chip of the present invention, a shield grounding conductor is inserted between the dielectric substrates stacked one above the other and pressure-bonded, and a grounding conductor is inserted on the mounting surface of the lower dielectric substrate. An electrode and a signal electrode are provided, a strip conductor is provided at the center of the surface of the upper dielectric substrate, and ground conductors are provided on both sides of the strip conductor, and the ground conductor and the shield ground conductor are connected to the ground electrode, and the strip conductor is provided at the center of the surface of the upper dielectric substrate. The signal electrodes are configured to be connected to the respective signal electrodes through the side surfaces of both the dielectric substrates.
ストリップ導体はストリップ線路を構成することにより
、回路基板上の交叉する信号配線パターンの接続に用い
て一方の分断された信号配線パターンをインピーダンス
の整合をとって信号の減衰を軽減するように接続するこ
とができる。また、シールド接地導体は他方の分断され
ない信号配線パターンとストリップ導体との間に位置す
ることにより、電磁的にシールドし信号間の漏話を軽減
することができる。By configuring a strip line, strip conductors are used to connect intersecting signal wiring patterns on a circuit board, and connect one separated signal wiring pattern to match impedance and reduce signal attenuation. be able to. Moreover, by positioning the shield ground conductor between the other undivided signal wiring pattern and the strip conductor, it is possible to electromagnetically shield and reduce crosstalk between signals.
以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.
配線パターン接続用チップ１は、第１図の外観斜視図及
び第２図のを解斜視図に示すように上下に重ね合わせ積
層される２枚の誘電体基板１−１．１−２の下側誘電体
基板１−２の上面（合わせ面）全面にシールド接地導体
１ａを設け、下面（実装面）に接地用電極１ｂと信号用
電極ＩＣとを設け、上側誘電体基板１−１の表面中央に
ストリップ導体１ｄを設けるとともに、このストリップ
導体１ｄの両側に接地導体１ｅを設け、接地導体１ｅと
シールド接地導体１ａとを接地用電極１ｂに、ストリッ
プ導体１ｄを信号用電極１ｃにそれぞれ両誘電体基板１
−１．１−２の側面を経て接続し構成する。The wiring pattern connection chip 1 is placed under two dielectric substrates 1-1 and 1-2 that are stacked one above the other as shown in the external perspective view of FIG. 1 and the exploded perspective view of FIG. A shield grounding conductor 1a is provided on the entire upper surface (mating surface) of the side dielectric substrate 1-2, a grounding electrode 1b and a signal electrode IC are provided on the lower surface (mounting surface), and the surface of the upper dielectric substrate 1-1 is provided with a grounding electrode 1b and a signal electrode IC. A strip conductor 1d is provided in the center, and grounding conductors 1e are provided on both sides of the strip conductor 1d, and the grounding conductor 1e and shield grounding conductor 1a are used as the grounding electrode 1b, and the strip conductor 1d is used as the signal electrode 1c, respectively. body substrate 1
-1. Connect and configure via the side of 1-2.
この配線パターン接続用チップの製作方法を以下に述べ
る。なお、本実施例は誘電体基板をセラミック基板とし
ている。A method of manufacturing this wiring pattern connection chip will be described below. Note that in this embodiment, the dielectric substrate is a ceramic substrate.
■ 先ず、第３図の斜視図に示すように多面取りする（
図は９個取りを示す）大きさのアルミナなどからなるグ
リーンシート１０を製作し、配線パターン接続用チップ
の大きさ（斜線部は１個片の大きさを示す）に分割切断
する縦、横切断線Ａ、 Ｂの縦切断線Ａ上に１個片の
間隔に３傭ずつの貫通する孔１０ａ（例えば直径約２１
１）をパンチング加工する。このグリーンシート１０に
シールド接地導体またはストリップ導体及び接地導体を
形成するため厚膜法により風体ペースト、例えば銅導体
ペーストをそれぞれの孔１０ａを含めて印刷塗布するが
、グリーンシート１０を上側、下側誘電体基板を形成す
る素材、即ち第１、第２のグリーンシート１０−１゜１
０−２に分ける。■ First, as shown in the perspective view of Fig. 3, multiple sides are cut (
A green sheet 10 made of alumina, etc., is produced with a size of 9 pieces (the figure shows 9 pieces), and is cut vertically and horizontally into the size of the chip for wiring pattern connection (the shaded area indicates the size of one piece). On the vertical cutting line A of the cutting lines A and B, there are holes 10a (for example, about 21 mm in diameter) that pass through each piece at intervals of 3 mm.
1) is punched. In order to form a shield ground conductor, a strip conductor, and a ground conductor on this green sheet 10, air paste, such as copper conductor paste, is printed and applied by a thick film method including the holes 10a. Materials forming the dielectric substrate, i.e., first and second green sheets 10-1゜1
Divide 0-2.
■ 下側誘電体基板１−２となる第２のグリーンシート
１Ｏ−２の上面（合わせ而）は、第４図の合わせ面倒一
部拡大斜視図に示すように各個片の中央孔１０ａ−１を
除き（孔１０ａ−１の周囲に隙間を開は短絡を防ぐ）、
シールド接地導体１ａとなる導体ペースト１ａ’ を両
側孔１０ａ−２を含めて全面印刷塗布する。■ The upper surface (joint) of the second green sheet 1O-2, which becomes the lower dielectric substrate 1-2, has a central hole 10a-1 of each individual piece, as shown in the partially enlarged perspective view of the joint in FIG. (opening a gap around hole 10a-1 prevents short circuit),
A conductor paste 1a' which will become the shield ground conductor 1a is applied by printing to the entire surface including the holes 10a-2 on both sides.
そして、下面（回路基板との実装面）には、第５図の実
装面側一部拡大斜視図に示すように各孔１０ａ−１，１
０ａ−２の周囲に孔１０ａ−１，１０ａ−２を含めて接
地用電極１ｂ及び信号用電極１ｃとなる導体ペースト１
ｂＺ１ｃ’を印刷塗布する。As shown in the partially enlarged perspective view of the mounting surface side in FIG.
A conductive paste 1 including holes 10a-1 and 10a-2 around 0a-2 and serving as a grounding electrode 1b and a signal electrode 1c.
bZ1c' is applied by printing.
■ 上側誘電体基板１−１となる第２のグリーンシート
１０−２の片面（合わせ面の反対面で配線パターン接続
用チップ完成後は表面となる）は、第６図の表面側一部
拡大斜視図に示すように各個片の中央孔１０ａ−１列間
を接続するようにストリップ導体１ｄとなる導体ペース
）１ｄ”を孔１０ａ−１を含めて１本の線に印刷塗布し
、この導体ペース１−１ｄ’（ストリップ導体１ｄ）に
短絡しないように隙間を開は接地導体１ｅとなる導体ペ
ースト１ｅ’を孔１０ａ−２を含めて残る全面に印刷塗
布する。■ One side of the second green sheet 10-2 that will become the upper dielectric substrate 1-1 (the opposite side to the mating surface, which will become the front surface after the wiring pattern connection chip is completed) is shown in the enlarged part of the front side in Figure 6. As shown in the perspective view, a conductor paste (1d), which will become the strip conductor 1d, is printed and coated on one line including the holes 10a-1 so as to connect between the central holes 10a-1 row of each individual piece, and this conductor is A gap is opened so as not to cause a short circuit to the paste 1-1d' (strip conductor 1d), and conductor paste 1e', which will become the ground conductor 1e, is printed and coated on the remaining entire surface including the hole 10a-2.
■ 第１、第２のグリーンシート１０−１．１０−２に
塗布したそれぞれの導体ペース）ｌａ’ 〜１ｅ１を乾
燥した後、第２図のように第２のグリーンシート１０２
を下側に上下に重ね合わせ圧着・積層する。■ After drying the respective conductor pastes la' to 1e1 applied to the first and second green sheets 10-1 and 10-2, the second green sheets 102 are coated as shown in FIG.
Stack and crimp/laminate the top and bottom on the bottom side.
そして、縦、横切断線Ａ、Ｂ上で個片に分割切断した後
（導体ペーストを塗布した孔は２分割される）、それぞ
れを加熱・焼成し、第１図に示した配線パターン接続用
チップ１を完成する。Then, after cutting into individual pieces on vertical and horizontal cutting lines A and B (the hole coated with conductive paste is divided into two), each piece is heated and fired to connect the wiring pattern shown in Figure 1. Complete chip 1.
なお、配線パターン接続用チップの信号用電極、接地用
電極には半田めっきを施し、表面のストリップ導体及び
接地導体を保護するため、ガラスエポキシ樹脂接着剤な
どの絶縁体を被着しておくのが望ましい。Note that the signal electrodes and ground electrodes of the wiring pattern connection chip are solder plated, and an insulator such as glass epoxy resin adhesive is applied to protect the strip conductor and ground conductor on the surface. is desirable.
つぎに、本発明の配線パターン接続用チップ１を第７図
の要部斜視図に示す高周波回路基板１１の交叉する信号
配線パターン１２の接続に用いる場合について説明する
。Next, a case will be described in which the wiring pattern connecting chip 1 of the present invention is used for connecting the intersecting signal wiring patterns 12 of the high frequency circuit board 11 shown in the perspective view of the main part in FIG.
高周波回路基板１１は図示するように、信号配線パター
ン１２の周囲に短絡しない程度の隙間を開けて残る全面
に接地レベルの接地配線パターン１３を備え、信号配線
パターン１２の一部が互いに交叉する信号配線パターン
１２−１．１２−２を備えている。配線パターン接続用
チップ１を第８図の要部斜視図に示すように信号配線パ
ターン１２−１．１２−２の交叉部に載せ、信号用電極
１ｃを一方の分断された信号配線パターン１２−１に、
接地用電極１ｂを接地配線パターン１２−２にそれぞれ
合わせた後、半田１４付げにより実装接続する。As shown in the figure, the high-frequency circuit board 11 is provided with a ground wiring pattern 13 at the ground level on the entire surface of the signal wiring pattern 12 with a gap large enough to prevent short circuits, and a part of the signal wiring patterns 12 is used for signals that intersect with each other. It is provided with wiring patterns 12-1 and 12-2. The wiring pattern connection chip 1 is placed on the intersection of the signal wiring patterns 12-1 and 12-2 as shown in the main part perspective view of FIG. 8, and the signal electrode 1c is connected to one of the divided signal wiring patterns 12- 1,
After the grounding electrodes 1b are aligned with the grounding wiring patterns 12-2, they are mounted and connected by soldering 14.
このように接続した配線パターン接続用チップは、スト
リップ導体と接地導体とでストリップ線路を構成してい
ることにより、ストリップ導体は一方の分断された信号
配線パターンを従来のワイヤに比べて極端に短く接続で
きるとともに、インピーダンスの整合をとって信号の減
衰を軽減することができる。また、シールド接地導体は
回路基板の分断されない信号配線パターンとストリップ
導体との間に設けられていることにより、両者を電磁的
にシールドし信号間の漏話を軽減することができる。The wiring pattern connection chip connected in this way has a strip line made up of a strip conductor and a ground conductor, so the strip conductor can connect one separated signal wiring pattern to an extremely short length compared to conventional wires. In addition to being able to connect, impedance matching can be achieved to reduce signal attenuation. Further, by providing the shield ground conductor between the undivided signal wiring pattern of the circuit board and the strip conductor, it is possible to electromagnetically shield both and reduce crosstalk between signals.
配線パターン接続用チップは、上記説明のように誘電体
基板をセラミック基板とし、そのグリーンシートの多面
取りによって製作することができるため、生産性に優れ
安価に提供することができるが、セラミック基板に限ら
ず他の誘電体基板、例えばガラスエポキシ樹脂を重ね合
わせ積層し同様の構成としてもよい。As explained above, chips for connecting wiring patterns can be manufactured by using a ceramic substrate as a dielectric substrate and cutting out multiple green sheets. However, other dielectric substrates such as glass epoxy resin may be laminated to form a similar structure.
以上、詳述したように本発明によれば、シールド接地導
体とストリップ線路を有する配線パターン接続用チップ
を交叉する信号配線パターンの接続に用いることにより
、信号間の漏話及び信号の減衰を軽減することができ、
特性のよい高周波回路基板を提供することができるとい
った産業上極めて有用な効果を発揮する。As detailed above, according to the present invention, crosstalk between signals and signal attenuation are reduced by using a wiring pattern connection chip having a shield ground conductor and a strip line to connect intersecting signal wiring patterns. It is possible,
This exhibits extremely useful effects in industry, such as being able to provide a high-frequency circuit board with good characteristics.
第１図は本発明による一実施例の外観斜視図、第２図は
第１図の分解斜視図、
第３図は本発明に用いるグリーンシートの斜視図、
第４図は第２のグリーンシートの合わせ面倒−部拡大斜
視図、
第５図は第２のグリーンシートの実装面側一部拡大斜視
図、
第６図は第１のグリーンシートの表面側一部拡大斜視図
、
第７図は高周波回路基板の要部斜視図、第８図は第１図
を第７図に接続した状態を示す要部斜視図、
第９図は従来技術による接続状態を示す要部斜視図であ
る。
図において、
ｌは配線パターン接続用チップ、
１−１は上側誘電体基板、
１−２は下側誘電体基板、
ｌａはシールド接地導体、
１ｂは接地用電極、
１ｃは信号用電極、
１ｄはストリップ導体、
１ｅは接地導体を示す。
配線パターン接続用チップ上
第
ｄ
凶Fig. 1 is an external perspective view of an embodiment according to the present invention, Fig. 2 is an exploded perspective view of Fig. 1, Fig. 3 is a perspective view of a green sheet used in the present invention, and Fig. 4 is a second green sheet. Fig. 5 is a partially enlarged perspective view of the mounting surface side of the second green sheet, Fig. 6 is a partially enlarged perspective view of the front side of the first green sheet, and Fig. 7 is an enlarged perspective view of the mounting surface side of the first green sheet. FIG. 8 is a perspective view of the main parts of the high frequency circuit board, FIG. 8 is a perspective view of the main parts showing the state in which FIG. 1 is connected to FIG. 7, and FIG. 9 is a perspective view of the main parts showing the state of connection according to the prior art. In the figure, l is a wiring pattern connection chip, 1-1 is an upper dielectric substrate, 1-2 is a lower dielectric substrate, la is a shield grounding conductor, 1b is a grounding electrode, 1c is a signal electrode, and 1d is a Strip conductor, 1e indicates ground conductor. No. d on the chip for wiring pattern connection
Claims (1)
の全面にシールド接地導体（１ａ）を介挿し、下側誘電
体基板（１−２）の実装面に接地用電極（１ｂ）と信号
用電極（１ｃ）を設け、上側誘電体基板（１−１）の表
面中央にストリップ導体（１ｄ）を設けるとともに該ス
トリップ導体（１ｄ）の両側に接地導体（１ｅ）を設け
、該接地導体（１ｅ）とシールド接地導体（１ａ）とを
前記接地用電極（１ｂ）に、ストリップ導体（１ｄ）を
前記信号用電極（１ｃ）にそれぞれ前記両誘電体基板（
１−１，１−２）の側面を経て接続してなることを特徴
とする配線パターン接続用チップ。A shield grounding conductor (1a) is inserted between the dielectric substrates (1-1, 1-2) which are stacked and crimped one above the other, and a grounding electrode (1a) is inserted on the mounting surface of the lower dielectric substrate (1-2). 1b) and a signal electrode (1c), a strip conductor (1d) is provided at the center of the surface of the upper dielectric substrate (1-1), and ground conductors (1e) are provided on both sides of the strip conductor (1d), The ground conductor (1e) and the shield ground conductor (1a) are connected to the ground electrode (1b), and the strip conductor (1d) is connected to the signal electrode (1c), respectively.
1-1, 1-2) A chip for connecting a wiring pattern, characterized in that the chip is connected through the side surfaces of 1-1 and 1-2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24964589A JPH03110768A (en) | 1989-09-25 | 1989-09-25 | Chip for connecting wiring pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24964589A JPH03110768A (en) | 1989-09-25 | 1989-09-25 | Chip for connecting wiring pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03110768A true JPH03110768A (en) | 1991-05-10 |
Family
ID=17196103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24964589A Pending JPH03110768A (en) | 1989-09-25 | 1989-09-25 | Chip for connecting wiring pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03110768A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5768109A (en) * | 1991-06-26 | 1998-06-16 | Hughes Electronics | Multi-layer circuit board and semiconductor flip chip connection |
| EP1047291A1 (en) * | 1999-04-24 | 2000-10-25 | Diehl AKO Stiftung & Co. KG | Solder bridge |
| EP1324646A2 (en) * | 2001-12-27 | 2003-07-02 | Alps Electric Co., Ltd. | Jumper chip component and mounting structure therefor |
-
1989
- 1989-09-25 JP JP24964589A patent/JPH03110768A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5768109A (en) * | 1991-06-26 | 1998-06-16 | Hughes Electronics | Multi-layer circuit board and semiconductor flip chip connection |
| EP1047291A1 (en) * | 1999-04-24 | 2000-10-25 | Diehl AKO Stiftung & Co. KG | Solder bridge |
| EP1324646A2 (en) * | 2001-12-27 | 2003-07-02 | Alps Electric Co., Ltd. | Jumper chip component and mounting structure therefor |
| EP1324646A3 (en) * | 2001-12-27 | 2004-11-03 | Alps Electric Co., Ltd. | Jumper chip component and mounting structure therefor |
| US6949819B2 (en) | 2001-12-27 | 2005-09-27 | Alps Electric Co., Ltd. | Jumper chip component and mounting structure therefor |
| US7098531B2 (en) | 2001-12-27 | 2006-08-29 | Alps Electric Co., Ltd. | Jumper chip component and mounting structure therefor |
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