JPH03122572U - - Google Patents
Info
- Publication number
- JPH03122572U JPH03122572U JP3206790U JP3206790U JPH03122572U JP H03122572 U JPH03122572 U JP H03122572U JP 3206790 U JP3206790 U JP 3206790U JP 3206790 U JP3206790 U JP 3206790U JP H03122572 U JPH03122572 U JP H03122572U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- conductive layer
- multilayer printed
- printed circuit
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000011889 copper foil Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図ａ，ｂ，ｃ，ｄはこの考案の一実施例に
よる多層プリント回路基板を示す構成図、第２図
〜第６図は従来の多層プリント回路基板を示し、
第２図〜第５図はハンダ上りの状態図、第６図ａ
，ｂ，ｃ，ｄは多層プリント回路基板の構成図で
ある。
図において、ａ１，ａ２，ａ３，ａ４……銅箔
、１１，１２……ハンダ接合性の良好な材料であ
る。なお、図中、同一符号は同一、又は相当部分
を示す。
FIGS. 1a, b, c, and d are block diagrams showing a multilayer printed circuit board according to an embodiment of this invention, and FIGS. 2 to 6 show conventional multilayer printed circuit boards,
Figures 2 to 5 are state diagrams of soldering, Figure 6a
, b, c, and d are configuration diagrams of a multilayer printed circuit board. In the figure, a1, a2, a3, a4 are copper foils, and 11, 12 are materials with good solderability. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
電層となし、該導電層を絶縁層の表面に積層し、
その導電層と絶縁層とを組み合せた多層プリント
回路基板において、制御素子等の電気部品と接続
するスルーホール部の内径側部にハンダ接合性の
良好な材料を押入したことを特徴とする多層プリ
ント回路基板。 Forming a predetermined circuit pattern with copper foil to form a conductive layer, laminating the conductive layer on the surface of the insulating layer,
In a multilayer printed circuit board that combines a conductive layer and an insulating layer, a multilayer printed circuit board is characterized in that a material with good solderability is injected into the inner diameter side of a through hole that connects to electrical components such as control elements. circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3206790U JPH03122572U (en) | 1990-03-28 | 1990-03-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3206790U JPH03122572U (en) | 1990-03-28 | 1990-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03122572U true JPH03122572U (en) | 1991-12-13 |
Family
ID=31534925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3206790U Pending JPH03122572U (en) | 1990-03-28 | 1990-03-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03122572U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009274864A (en) * | 2008-05-19 | 2009-11-26 | Casio Electronics Co Ltd | Packing bag sealing method of consumables unit and consumables unit having packing bag locking tool |
-
1990
- 1990-03-28 JP JP3206790U patent/JPH03122572U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009274864A (en) * | 2008-05-19 | 2009-11-26 | Casio Electronics Co Ltd | Packing bag sealing method of consumables unit and consumables unit having packing bag locking tool |