JPH03117923A - Error correcting decoder - Google Patents

Abstract

PURPOSE:To increase the error correction speed by comparing the number of errors of reception words with the number of correction errors and correcting errors of received words divided in parallel based on this comparison result. CONSTITUTION:A number 'e' of errors of received words is stored in a memory 4, and numbers of errors e'1, e'2...e'N calculated by a correction error number calculating circuit 6 are stored in a memory 7. A comparing circuit 8 compares contents 'e' of the memory 4 with contents e'i (i=1, 2,..., N) of the memory 7; and in the case of e'i=e-1 (1<=e<=t), the error of the received word of bits in positions corresponding to N-number of circuits arranged in parallel is corrected by a correcting circuit 10. Thereafter, the received word which is corrected and divided into N in parallel is converted to series connection by a parallel-serial converting circuit 12 and is outputted to an output terminal 14. The correction operation of received words in another N-bit unit block is continued till the number (e) of errors to be corrected are found. Thus, error correction and decoding are quickly performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoder for correcting errors in digital information, and in particular to a decoder for correcting errors in digital information, and in particular for binary BCH codes (Bose-Chaudh codes).
The present invention relates to an error correction decoder for uri-Hocquenghem code).

[Conventional technology]

FIG. 5 is a block diagram showing a conventional decoder shown in, for example, "A Study of Error/Erasure Correction Decoding for Optical Discs" (Proceedings of the 10th Information Theory and Its Applications Society PP, 6l-64). In the figure, 20 is a control circuit, 21 is a program ROM that stores instructions issued by the control circuit 20, and 22
23 is a syndrome/Cheng processing circuit that calculates a syndrome from a received word and also performs a Chien search from an error locator polynomial to find an error location. 23 is a Galois rest that calculates an error locator polynomial from the syndrome generated by the syndrome/Cheng processing circuit 22. an arithmetic circuit; 24 a buffer memory for storing received words; 25 a buffer memory 2;
4 is an interface circuit that interfaces the received word stored in the error correction device with the received word, 26 is an input terminal of the error correction decoder, and 27 is an output terminal of the error correction decoder.

Next, the operation will be explained.

First, the received word is stored in the buffer memory 24 from the input terminal 26. This received word is read out from the buffer memory 24 to the syndrome chain processing circuit 22 by a control signal sent from the control circuit 20 to the interface circuit 25. And syndrome Chen processing circuit 2
2, the syndrome corresponding to the received word is calculated. The syndrome is read out from the syndrome Chen processing circuit 22 to the Galois rest arithmetic circuit 23 in response to a signal from the control circuit 20, and the Galois rest arithmetic circuit 23 calculates an error locator polynomial. Here, regarding the process of calculating the error locator polynomial, for example, Figure 6 is a flowchart shown in "Theory of Information and Codes" (Iwanami Shoten, by Miyayo, Harashima, and Imai, p. 169). Ru.

Next, the error locator polynomial is read out from the Galois rest arithmetic circuit 23 to the syndrome-Cheng processing circuit 22 in response to a signal from the control signal 20.
2, a Chien search is performed and the error location is calculated. The error position is read out from the syndrome-chen processing circuit 22 by a signal from the control circuit 2o, and the received word stored in the buffer memory 24 is corrected through the interface circuit 25, and outputted to the output terminal 27 to correct the error. Finish the operation.

[Problem to be solved by the invention]

Since the conventional error correction decoder is configured as described above, the operation to obtain the error pattern must go through many steps, which increases the time spent on error correction decoding, and also requires the control circuit. There were problems such as complicated control.

This invention was made to solve the above-mentioned problems, and an object thereof is to obtain an error correction decoding device that can perform error correction at high speed.

[Means to solve the problem]

The error correction decoding device according to the present invention includes a syndrome generation circuit including a buffer memory for storing an n-bit received word, means for calculating a syndrome of the received word, and a register for storing the result, and An error number calculation circuit that calculates the number of errors from the above, a storage circuit that stores the number of errors, and N (1≦N≦n) registers arranged in parallel to store the syndromes generated by the syndrome generation circuit, and a memory circuit that stores the number of errors. a modified syndrome generation circuit comprising a means for calculating a syndrome for use in a modification, and a modification register for storing a modification syndrome;
a correction error number calculation circuit that calculates the number of errors for correction based on the correction syndrome; a correction storage circuit that stores the number of errors for correction; a comparison circuit that compares the calculated number of errors with the number of errors for correction; A serial-to-parallel converter divides the received word into blocks of N bits corresponding to the number N of modified syndrome generation circuits, and further divides the received word into N blocks in parallel, and the comparison circuit divides the received word into N parallel blocks. The present invention is equipped with a correction circuit that corrects errors according to the result of the correction circuit, and a parallel-to-serial conversion circuit that connects in series the received words that have been corrected by the correction circuit and divided into N pieces in parallel.

[Effect]

In the present invention, as configured as described above, it is possible to save the time and effort of the conventional Chien search operation, and also to simplify the operation for determining errors, so that error correction decoding can be performed at high speed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an error correction decoding device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the detailed configuration of some of the components of the error correction decoding device according to an embodiment of the present invention. It is a diagram.

In Figure 1, ■ is a buffer memory that stores an n-bit received word, 2 is a syndrome generation circuit that calculates the syndrome of the received word, and 3 is a syndrome generation circuit that calculates the number of errors in the received word from the syndrome calculated. 4 is a memory that stores the number of errors "e" calculated by the error number calculation circuit 3; 5 is a memory that stores a virtual 1-bit error for the n-bit received word stored in the buffer memory 1 This is a modified syndrome generation circuit that generates a modified syndrome of a received word in the case of pseudo addition, and as shown in FIG. 2, this circuit has a register 5a that stores the syndrome calculated by the syndrome generation circuit 2.
, a syndrome generation circuit 5b that calculates a correction syndrome from the syndrome, and a correction register 5C that stores the correction syndrome. In FIG. 1, 6 is a correction error number calculation circuit that calculates the number of correction errors from the correction syndrome calculated by the correction syndrome generation circuit 5, and 7 is a correction error number calculation circuit that calculates the number of correction errors calculated by the correction error number calculation circuit 6. It is a memory that stores information. A comparison circuit 8 compares the contents of the memory 4 and the contents of the memory 7.

These modified syndrome generation circuits5. Corrected error number calculation circuit 6. The memory 7 and the comparison circuit 8 are sequentially connected in series, and N (1≦N≦n) devices having this configuration are arranged in parallel. 9 is serial-parallel conversion for dividing the n-bit received word in the buffer memory 1 into N-bit blocks corresponding to the number of corrected syndrome generation circuits arranged in N parallel, and then dividing it into N blocks in parallel. 10 is a correction circuit that corrects the received word from the serial/parallel converter 9 in accordance with the output of the comparison circuit 8; 11 is a control circuit that controls the entire error correction circuit;
13 is an input terminal of an error correction decoder, and 14 is an output terminal of the error correction decoder.

Next, the operation will be explained.

The received word of n bits is transferred from the input terminal 13 to the buffer memory 1.
This received word is input to the syndrome generation circuit 2 and the syndrome r3.corresponding to the received word is stored. l S2
+..., 5zt (t is the maximum number of errors that can be corrected). The syndrome is read out from the syndrome generation circuit 2 to the error number calculation circuit 3 in response to a signal from the control circuit 9, and the number of errors "e" is calculated. Here, the process of calculating the number of errors [ej] is performed according to the flowchart of FIG. 3, and the number of errors "e" of the received word is stored in the memory 4.

Next, in response to a signal from the control circuit 9, the syndrome generation circuit 2 outputs the syndrome "S+, St, . . . ," to each of the N modified syndrome generation circuits 5 arranged in parallel.
5ztJ is read and stored in the syndrome storage register 5a. And the syndrome generation circuit 5b
As a result, a modified syndrome corresponding to the received word when a virtual error is generated in the i-th bit (1≦i≦N) of the received word is generated and stored in the corrected syndrome storage register 5c. Here, as shown in FIG. 3, the modified syndrome generation circuit 5 operates as α1. α1. ...α2t
1 (i=1. 2...., N) to the corresponding syndromes Sl, SZ+...+5Zt-, the modified syndromes s', =s, +αji (j=
1°2, . . . , 2t, α is the root of the primitive polynomial).

Next, for the N sets of modified syndromes generated by the modified syndrome generation circuit 5, the error calculation circuit 6 calculates the number of errors in the N sets 'e'l+e'2. . . , ej8'. The process of calculating this number of errors is shown in Figure 3 as follows: S (Z) = S, +Sz Z+...+Sz
tZ! Publish S (Z)=S', +3', 7. +
. . . 10 S゛, calculated according to the flowchart changed to t221-+.

Then, the number of errors "e"I+e'Z+ . . . +e'sJ calculated by the corrected error number calculation circuit 6 is stored in the memory 7.

Next, the n-bit received word from buffer memory 1 is read out to the serial/parallel conversion circuit, and as shown in FIG. 4, it is divided into blocks of N bits. The word is divided into N parts and processed in parallel so that each word has a 1-bit correspondence according to the N modified syndrome generation circuits arranged in parallel.

Furthermore, in the comparator circuit 8, the content 'e' of the memory 4 and the content 'e' of the memory 7 + (i=1.2°..., N
)”. And e't=e-1(1≦e≦t
), the correction circuit 10 performs error correction on the received word of the bit at the position corresponding to the N circuits arranged in parallel. Thereafter, the corrected and parallel-divided N words are converted into series connections by the parallel-to-serial conversion circuit 12 and output to the output terminal 14. Then, the correction operation is continued for the received word of another N-bit unit block until zero errors are found to be corrected.

In the above embodiment, the syndrome of the received word is first calculated, then the number of errors in the received word is calculated, and then the corrected syndrome for the first N-bit unit is calculated, but they may be performed simultaneously.

[Effects of the Invention] As described above, according to the present invention, it is possible to find errors without performing a Chien search that was performed in the conventional decoding operation, and the operation can also be processed in a short time, so that errors can be detected quickly. This has the effect of corrective decoding.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an error correction decoding device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a modified syndrome generation circuit, and FIG. 3 is a flow chart showing the operation procedure in the error number calculation circuit. Fig. 4 is a diagram explaining the processing of the serial-parallel conversion circuit for received words, Fig. 5 is a block diagram showing a conventional error correction decoding device, and Fig. 6 is a flowchart showing the conventional operation procedure for calculating an error locator polynomial. It is. 1 is a buffer memory, 2 is a syndrome generation circuit, 3 is a received word error number calculation circuit, 4 is a storage device, 5 is a modified syndrome generation circuit, 6 is an error number calculation circuit, 7 is a storage device, 8 is a comparison circuit, 9 is a serial/parallel converter,
10 is a correction circuit, 11 is a control circuit, 12 is a parallel/serial conversion circuit, 13 is an input terminal, 14 is an output terminal, 2
o is a control circuit in the conventional example, 21 is a program ROM
, 22 is a syndrome-chen processing circuit, 23 is a Galois rest arithmetic circuit, 24 is a buffer memory, 25 is an interface circuit, 26 is an input terminal, and 27 is an output terminal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In an error correction decoder for a binary BCH code, a syndrome generation circuit includes a buffer memory for storing an n-bit received word, a means for calculating a syndrome of the received word, and a register for storing the result. , an error number calculation circuit that calculates the number of errors in the received word from the syndrome calculated above, and a memory circuit that stores the number of errors, N (1≦N≦n) arranged in parallel, and according to the syndrome generation circuit described above. A correction syndrome generation circuit comprising a register for storing a syndrome, a means for calculating a correction syndrome from the syndrome, and a register for storing the correction syndrome, and a correction error number for calculating the correction error number from the correction syndrome. a calculation circuit; a correction storage circuit that stores the number of errors for correction; a comparison circuit that compares the calculated number of errors with the number of errors for correction; and a correction syndrome generation circuit that converts the n-bit received word of the buffer memory A serial method that divides into N-bit blocks corresponding to the number N, and then divides them into N blocks in parallel.
a parallel converter, a correction circuit for error-correcting the received word divided into N parallel parts according to the result of the comparison circuit, and a parallel/serial converter for serially connecting the received word corrected by the correction circuit and divided into N parallel parts. An error correction decoder comprising a conversion circuit.