JP2001086005A - Chain searching circuit and error correction encoding/ decoding device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chain searching circuit where error position calculation is speeded up with the circuit of a small scale. SOLUTION: Multipliers 1, 2, 3 and 4 input σ1 and σ2 and output multiplier outputs σ11, σ21, σ12 and σ22. A switch 13 changes over the multiplier outputs σ11, σ21, σ12 and σ22. Registers 9, 10, 11 and 12 temporarily store the multiplier outputs σ11, σ21, σ12 and σ22. Multipliers 5, 6, 7 and 8 feed back the register outputs to the register inputs. An adder 14 adds the outputs of the registers 9 and 10 and a constant value '1' and outputs an addition result 16. An adder 15 adds the outputs of the registers 11 and 12 and the constant value '1' and outputs an addition result 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Chien search circuit and an error correction code decoding apparatus using the same, and more particularly to an error correction code decoding apparatus in which error positions are calculated in parallel by operating a plurality of circuits simultaneously. The present invention relates to a Chien search circuit for speeding up an error correction and an error correction code decoding device using the same.

[0002]

2. Description of the Related Art In recent years, it has become important to secure transmission quality by error correction in a data transmission device such as a radio device, and at the same time, to cope with an increase in the speed of a signal processing circuit accompanying an increase in the amount of transmitted information. I have.

Against this background, an error correction circuit is incorporated in a device, and the size of the device is increased. Therefore, it is required to reduce the size of the error correction circuit by LSI and to significantly speed up the processing.

FIG. 8 is a block diagram showing an example of a conventional Chien search circuit.

A Reed-Solomon code on a Galois field GF (2 ⁸ ), a primitive polynomial (1), a generator polynomial (2), a code length of 64 bytes, and a parity code length of RS (64, 4 bytes)
60) Implemented for code.

[0006] A conventional Chien search circuit comprises a multiplier 14
1, 142, a switch 147 for switching between the multiplier outputs σ ₁₁ and σ ₂₁ , registers 145 and 146, and a multiplier 14 for feeding back these register outputs to the register inputs.
3, 144, the outputs of the registers 145, 146 and the constant value “1”, and outputs an addition result 151.
0.

Next, the operation will be described. σ ₁ is a multiplier 141
And σ ₂ is input to the multiplier 142. Multiplier 141,
The result of multiplication of σ ₁ and σ ₂ by 142 is output to switch 147 as σ ₁₁ and σ ₂₁ . Here, the result converted to σ ₁₁ = σ ₁ α ¹⁹¹ σ ₂₁ = σ ₂ α ¹²⁷ is output to the switch 147.

In the switch 147, the first register 1
Σ ₁₁ and σ ₂₁ are selected by the initial value selection signal 148 as the initial values of 45 and 146, and the respective initial values are stored in the register 1
45 and 146. Further, the switch 147 outputs σ ₁₁ ,
After taking σ ₂₁ as an initial value, the multipliers 143 and 14
A switching operation is performed so as to select the output of No. 4 to the input side of the registers 145 and 146.

Registers 145 and 146 have clock input 1
An output from the switch 147 is taken in by 49 and output at the next clock of the clock input 149. Register 14
The outputs of 5, 146 are input to multipliers 143, 144, respectively, and the outputs of multipliers 143, 144 are input again to registers 145, 146 via switch 147. This feedback operation is repeated. Registers 145, 14
6 is output to the adder 150.

In the adder 150, registers 145 and 146
And outputs an addition result 151 obtained by further adding "1" to the output. Here, the addition result 15 which is the output of the adder 150
Determining whether 1 is “0” is the operation of solving the error locator polynomial, and the number of times of repeating the feedback corresponds to the power of the error locator polynomial.

The addition result 151 which is the output of the adder 150
The error position can be obtained by counting the number of times the feedback is repeated until becomes “0”.

The present circuit has a configuration in which σ ₁₁ and σ ₂₁ are multiplied and output, and other multiplied outputs σ ₁₂ and σ ₂₂ are not required, and the circuit is small in scale. 64 times twice).

An example of such a technique is disclosed in Japanese Unexamined Patent Publication No.
An "error position and error value calculation circuit" described in Japanese Patent No. 27217 is known.

This publication describes a technique for obtaining polynomials for calculating an error position in the Euclidean algorithm using several types of polynomial calculation circuits and a Galois field arithmetic circuit using outputs of these polynomial calculation circuits.

[0015]

In the above-described conventional Chien search circuit, an error position can be obtained by counting the number of times feedback is repeated. However, since the number of times feedback is repeated is required, a large number of times are required. There is a disadvantage that the processing time increases.

An object of the present invention is to provide a Chien search circuit which can speed up the processing by performing error position calculation in parallel.

[0017]

SUMMARY OF THE INVENTION A Chien search circuit of the present invention is a Chien search circuit for calculating an error position in error correction. The Chien search circuit uses a plurality of circuits to perform parallel processing, and sets an initial value of the order of the error position calculation. It is characterized in that a multiplier for giving a different initial value to each of the parallel circuits is provided.

In a Chien search circuit for performing error position calculation in error correction, a plurality of circuits are used to perform parallel processing, and the initial value of the order of error position calculation is sequentially applied to the parallel circuit. And a multiplier for allocating.

In a Chien search circuit for performing error position calculation in error correction, a first multiplier and a third multiplier for generating first and third multiplier outputs from first input data; A second multiplier and a fourth multiplier for generating second and fourth multiplier outputs from the input data of the first, second, third, and fourth multipliers; A switch for simultaneously switching and outputting according to an initial value selection signal;
The outputs of the first, second, third, and fourth multipliers output by the switch are input, temporarily stored by clock input, and output as first, second, third, and fourth register outputs. First, second, third, and fourth registers; multiplying these first, second, third, and fourth register outputs, and multiplying the multiplied outputs by the first, second, third, and fourth registers A fifth, sixth, seventh, and eighth multiplier that outputs to the switch to feed back to the input of the register itself; and adds the first and second register outputs to a constant value “1”. A first adder that outputs a first addition result; a second adder that adds the third and fourth register outputs to a constant value “1” and outputs a second addition result.
And an adder 15 of.

The first, second, third, and fourth multipliers are:
It is characterized in that the initial value of the order of the error position calculation is set to a different initial value.

The first, second, third, and fourth multipliers are:
It is characterized in that settings are made so that the order of error position calculation is assigned in order.

The present invention is characterized in that the first to eighth multipliers, the switch, the first to fourth registers, and the first and second adders are integrated by a gate array.

A syndrome calculation circuit for calculating a syndrome from a received code input and outputting a syndrome; an error locator polynomial calculation circuit for deriving an error locator polynomial by the syndrome; and an error locator using the error locator polynomial. A chain search circuit for calculating and outputting
An error value calculation circuit that calculates and outputs an error value from the error position and the syndrome; and outputs a delay code in which the received code input is delayed by the same amount of delay amount due to processing from syndrome calculation to derivation of the error value. Delay circuit;
An error correction circuit that receives the delay code, corrects an erroneous code from the error value and the information on the error position, and outputs a corrected code output. .

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

First, as an example of an error correction code applied to the present invention, a primitive polynomial of a Reed-Solomon code on a Galois field GF (2 ⁸ ) is shown in equation (1), and a generator polynomial is shown in equation (2).

[0026]

(Equation 1)

[0027]

(Equation 2)

Here, an example is shown in which an RS (64, 60) code having a Reed-Solomon code (RS code) having a code word length of 64 bytes and a parity code length of 4 bytes is applied.

The calculation of the error location is performed by using α in the error location polynomial.
^-i (i = n−1, n−2,..., 1, 0) are sequentially substituted to obtain i for which the result is “0” (n is the codeword length). The general expression of the error locator polynomial is given by Expression (3), and -i corresponds to the position of the error.

[0030]

(Equation 3)

The error locator polynomial for the RS (64, 60) code is given by equation (4).

[0032]

(Equation 4)

FIG. 1 is a block diagram showing one embodiment of the Chien search circuit of the present invention.

Here, the Chien search circuit is a circuit to which a Chien search algorithm is applied. The Chien search algorithm means that σ (z) is the power α ⁱ of algorithm α
(I = 0, 1,..., N-1) are sequentially substituted, and σ (α ⁱ )
Is a method for checking whether or not is 0. A root search by this method is called a Chien Search.

The present embodiment shown in FIG.
2, 3, 4, and the multiplier outputs σ ₁₁ , σ ₂₁ , σ ₁₂ , σ
_A switching unit 13 for switching ₂₂ and registers 9, 10, 1
1, 12; multipliers 5, 6, 7, and 8 for feeding back the register outputs to the register inputs; and an adder 14 for adding the outputs of the registers 9 and 10 and a constant value "1" and outputting an addition result 16. And the outputs of the registers 11 and 12 and the constant value "1"
And an adder 15 for adding the result and outputting an addition result 17.

The operation will be described with reference to FIG. 1. Σ ₁ and σ ₂ of the error locator polynomial (4) derived in the error correction decoding process are first determined by any of the multipliers ₁ , ₂ , 3, and 4. Is entered.

Σ ₁ is input to a multiplier 1 that splits into two and multiplies by α ¹⁹² and a multiplier 3 that multiplies by α ²²⁴ , while σ ₂ also splits into two and multiplies by α ^{129 and} multiplies by α ¹⁹³ Input to the device 4. Σ ₁ by multipliers 1, 2, 3, and 4
And σ ₂ are output to the switch 13 as σ ₁₁ , σ ₂₁ , σ ₁₂ , and σ ₂₂ . Here, the result converted to σ ₁₁ = σ ₁ α ¹⁹² σ ₂₁ = σ ₂ α ¹²⁹ σ ₁₂ = σ ₁ α ²²⁴ σ ₂₂ = σ ₂ α ¹⁹³ is output to the switch 13.

In the switching unit 13, first, the register 9 in the subsequent stage,
The initial value selection signal 18 is used as the initial value of 10, 11, 12
More σ₁₁, Σ_{twenty one}, Σ₁₂, Σ_{twenty two}Select the respective initial
The value is output to registers 9, 10, 11, and 12. Also,
The switch 13 is σ₁₁, Σ_{twenty one}, Σ ₁₂, Σ_{twenty two}As the initial value.
After that, register the output of multipliers 5, 6, 7, 8
Switching operation to select the input side of 9, 10, 11, 12
I do.

The registers 9, 10, 11, and 12 take in the output from the switch 13 in response to the clock input 19 and output the clock with the clock following the clock input 19. Register 9 ~
The output of each of the 12 branches into two, one of which is input to the multipliers 5 to 8, and the output of which is input to the registers 9 to 12 again via the switch 13. By repeating this feedback operation, the order of -i increases.
On the other hand, the outputs of the registers 9 and 10 are output to an adder 14, and the outputs of the registers 11 and 12 are output to an adder 15.

The adder 14 outputs an addition result 16 obtained by further adding "1" to the outputs of the registers 9 and 10, and the adder 15 similarly adds the result of adding "1" to the outputs of the registers 11 and 12. 17 is output. Here, the addition result 16, which is the output of the adder 14 or the adder 15,
Determining whether 17 is "0" or not is the operation for solving the error locator polynomial in equation (4), and the number of times feedback is repeated corresponds to -i.

Addition result 1 output from adders 14 and 15
The error position is obtained by counting the number of times the feedback is repeated until "6" and "17" become "0". In FIG. 1, the code word length is 64 because two parallel processes are performed.
It suffices to perform half of the bytes, that is, 32 times. For this reason,
The output of the adder 15 is added to the number of repetitions of 32 times in advance and treated as a value of the error position.

Next, the circuit operation of FIG. 1 will be described in detail. First, the value of the multiplier is determined as follows.

First, equation (4) is transformed into equation (5).

[0044]

(Equation 5)

Furthermore, equation (4) of the error locator polynomial is rewritten as equation (6) by performing two parallel processes.

(Equation 6) Also, since the initial values σ ₁₁ and σ ₂₁ of the registers 9 and 10 are the case where j = 0 in the equation (6), σ ₁₁ = σ ₁ α ^-63 = σ ₁ α ^255-63 = σ ₁ α ¹⁹² σ ₂₁ = σ ₂ α− ^{2 × 63} = σ ₂ α ¹²⁹ .

Similarly, since the initial values σ ₁₂ and σ ₂₂ of the registers 11 and 12 are those of k = 0 in the equation (6), σ ₁₂ = σ ₁ α ^-63 α ³² = σ ₁ ^α224 σ ₂₂ = σ ₂ the ^{α -2 × 63 α 32 = σ} 2 α 193.

Therefore, equation (6) can be rewritten as equation (7).

[0048]

(Equation 7)

From equation (7), multiplier 1 is α ¹⁹² , multiplier 2
Is set to α ¹²⁹ , the multiplier 3 is set to α ²²⁴ , and the multiplier 4 is set to α ¹⁹³ .

FIG. 2 is a time chart showing the operation of FIG.

In the case of the operation of two parallel processes, the code word length of 6
This is an example in which the calculation is performed by dividing 4 bytes into 32 bytes each of the first half and the second half. Also, the speed of the received codeword input is 1
Two examples are shown, one for processing at a speed of 1/2 per circuit and the other for processing at the same magnification. FIG. 2 shows a case where there is an error in the first and 33rd byte positions of the received codeword input. After the delay due to the processing, the addition result 16 and the addition result 17 are output as error position detection results at the first position. Is done. Also, when the clock input 19 is the same-size clock as the reception clock input, it indicates that the processing is completed in half the code word length.

FIG. 3 is a block diagram showing a second embodiment of the Chien search circuit of the present invention.

The example shown in FIG. 1 is an example in which the data is divided at the center of the range where the order -i can be taken in order to make the two parallel.
i is divided so as to be selected in order according to the number of divisions.

The present embodiment shown in FIG.
22, 23, and 24 and the multiplier outputs σ ₁₁ , σ ₂₁ , and σ
₁₂ , a switch 33 for switching σ ₂₂ and registers 29 and 3
0, 31, 32, multipliers 25, 26, 27, 28 for feeding back these register outputs to the register inputs, and an addition for adding the outputs of the registers 29, 30 and a constant value "1" to output an addition result 36. And an adder 35 that adds the outputs of the registers 31 and 32 and the constant value “1” and outputs an addition result 37.

The operation will be described with reference to FIG. 3. Σ ₁ and σ ₂ of the error locator polynomial (4) derived in the error correction decoding process are first determined by any of the multipliers 21, 22, 23 and 24. Is entered.

Σ ₁ is input to a multiplier 21 that splits into two and multiplies by α ^{192 and a} multiplier that multiplies by α ¹⁹³ , while σ ₂ similarly splits into two and multiplies by α ^{129 and a} multiplier that multiplies by α ^131. Input to the device 24. Multipliers 21, 22, 23,
The result of multiplying σ ₁ and σ ₂ by 24 is σ ₁₁ , σ ₂₁ , σ
₁₂ and σ ₂₂ are input to the switch 33. Here, the result converted to σ ₁₁ = σ ₁ α ¹⁹² σ ₂₁ = σ ₂ α ¹²⁹ σ ₁₂ = σ ₁ α ¹⁹³ σ ₂₂ = σ ₂ α ¹³¹ is output to the switch 33.

In the switch 33, first, the register 2 in the latter stage is used.
The initial value selection signal 3 is used as the initial value of 9, 30, 31, and 32.
By 8₁₁, Σ_{twenty one}, Σ₁₂, Σ_{twenty two}Are selected, respectively
Is output to registers 29, 30, 31, and 32
You. Further, the switch 33₁₁, Σ _{twenty one}, Σ₁₂, Σ_{twenty two}The initial
After being fetched as values, multipliers 25, 26, 27, 28
Is selected as the input side of registers 29, 30, 31, and 32.
The switching operation is performed so as to select.

The registers 29, 30, 31, 32 take in the output from the switch 33 in response to the clock input 39 and output it with the clock following the clock input 39. Register 2
The outputs of 9 to 32 are each branched into two, one of which is a multiplier 25 to 2
8 and the outputs of the multipliers 25 to 28 are again input to the registers 29 to 32 via the switch 33. By repeating this feedback operation, the order of -i increases. On the other hand, the outputs of the registers 29 and 30 are output to an adder 34, and the outputs of the registers 31 and 32 are output to an adder 35.

An adder 34 outputs an addition result 36 obtained by adding "1" to the outputs of the registers 29 and 30, and an adder 35 similarly adds an addition result obtained by adding "1" to the outputs of the registers 31 and 32. 37 is output. Here, the addition result 36, which is the output of the adder 34 or the adder 35,
Determining whether 37 is "0" or not is the operation of solving the error locator polynomial in equation (4), and the number of times feedback is repeated corresponds to -i.

Addition result 3 output from adders 34 and 35
The error position can be obtained by counting the number of times the feedback is repeated until 6, 37 becomes "0". In FIG. 3, however, half of the code word length, that is, 32 times, because two parallel processes are performed, And the output of the adder 35 is 3
Two times are added to the number of repetitions in advance and treated as the value of the error position.

Similarly, a method of determining the value of the multiplier will be described with reference to FIG.

First, the error locator polynomial of equation (5) is expressed by equation (8).
Rewrite like an expression.

[0063]

(Equation 8)

As a result, the multiplier 21 becomes α ¹⁹² , the multiplier 2
2 is α ¹²⁹ , the multiplier 23 is α ¹⁹³ , and the multiplier 24 is α
¹³¹ , the multiplier 25 and the multiplier 27 set the value to α ² , and the multiplier 26 and the multiplier 28 set the value to α ⁴ .

FIG. 4 is a time chart showing the operation of FIG.

In the case of the operation of the two parallel processes, the code word length of 6
This is an example in which the calculation is performed by alternately dividing the 4-byte odd-numbered and even-numbered bytes. In addition, two examples are shown, in which processing is performed at half the speed of one circuit with respect to the speed of input of a received codeword, and processing is performed at the same magnification. FIG. 4 shows a case where there is an error in the positions of the first and second bytes of the received codeword input. After a delay due to the processing, the position addition result 36 and the addition result 37 of the first position are used as error position detection results. Is output. In addition, in the case of the same-size clock, it indicates that the processing is completed in half the code word length.

FIG. 5 is a block diagram of a generalized form of the circuit of FIG.

Here, the value of the multiplier can be generalized by rewriting the error locator polynomial from the equation (3) to the following equation (9) when the number of columns of the circuit to be processed in parallel is r.

[0069]

(Equation 9)

FIG. 5 shows an example of parallel processing of r columns. When parallel processing is not performed in error position detection, the detection is performed at n−1, n−.
1,..., 0 or 0, 1,..., N−2, n−1.

The detection order is as follows: First column: 0, 1,... N / r-1 Second column: n / r, n / r + 1,... 2n / r-1. (N / r), (r-1) (n / r) +1,... N-1.

Next, the operation of FIG. 5 will be described.

Error position derived in error correction decoding processing
Σ in equation (9), which is a polynomial₁ ,… Σ _m-1, Σ_mAre each
, and the multipliers 41,.
Entered each time. Multipliers 41,... Multipliers 48, multipliers 49
Is output to the switch 68. switching
The multiplier 68 has multipliers 41,.
After the selector 49 is selected, the power is multiplied by the initial value selection signal 78.
Switch to the selection of the multiplier 50,..., The multiplier 57 and the multiplier 58
And outputs the selected output to registers 59,.
The signals are input to a register 66 and a register 67, respectively. register
59,... Registers 66 and 67 take initial values
After that, the multiplier 5 is activated every clock of the clock input 79.
0, output to the multiplier 57 and the multiplier 58,
.., Multiplier 57, multiplier 5
The output of 8 is a register 59,.
7 is input. As a result, the repetition of the expression (9) is performed.
The calculation is performed.

On the other hand, the outputs of the registers 59,..., 66, 67 are input to the adders 69,..., The adder 71 to output the addition results 75,. When the addition result 75,..., 77 becomes 0, it is the root of the equation (9), and the registers 59,.
The number of times the register 67 repeatedly performs the operation is the solution.

Similarly, FIG. 6 is a block diagram of a generalized form of the circuit of FIG.

Here, the value of the multiplier can be generalized by rewriting the error locator polynomial from the equation (3) to the following equation (10) when the number of columns to be processed in parallel is r.

[0077]

(Equation 10)

FIG. 5 shows an example of parallel processing of r columns. When no parallel processing is performed in error position detection, the detection is performed at n−1, n−.
6,... 1, 0 or 0, 1,..., N−2, n−1 are sequentially performed, whereas FIG.

The detection order is as follows: 1st column: 0, r + 1,... Nr 2nd column: 1, r + 2,..., Nr + 1... Rth column: r-1, 2, r-1,. Become.

Next, the operation of FIG. 6 will be described.

Σ ₁ ,... Σ _{m -1} and σ _m of the error locator polynomial (10) derived in the error correction decoding process are respectively r-branched, and multipliers 81,. Are respectively input to the devices 89. Multiplier 81,... Multiplier 88, multiplier 8
The result of the multiplication by 9 is input to the switch 108.
The switch 108 has multipliers 81,.
8, after selecting the multiplier 89 side, the initial value selection signal 11
8, the operation is switched to the selection of the multiplier 90,..., The multiplier 97, and the multiplier 98, and the output of the selected side is input to the registers 99,. Register 99, Register 106, Register 10
7, after the initial value is fetched, the data is output to the multipliers 90,..., 97 and 98 for each clock of the clock input 119, and the multipliers 90,
.., The outputs of the multipliers 97 and 98 are input to the registers 99,. As a result, the repetitive operation of the expression (10) is performed.

On the other hand, registers 99,.
The output of the register 107 is an adder 109,.
, And outputs an addition result 115,..., An addition result 117. The addition result 115 there is...
Is the case of the root of the equation (10), and the register 9
9,... The number of times the repetitive operation is performed in the register 107 is the solution.

FIG. 7 is a block diagram showing an example in which the Chien search circuit of the present invention is applied to an error correction code decoder.

The syndrome calculation of the received code input 120 is first performed by the syndrome calculation circuit 121. The error locator polynomial 129 is derived by the error locator polynomial calculation circuit 122 using the syndrome 128 thus obtained, and is output to the Chien search circuit 123.

Error position 1 is detected by the chain search circuit 123.
30 and the error position 130 is calculated by the error value calculation circuit 1
24 and output to the error correction circuit 125. The error value calculation circuit 124 calculates an error value 131 from the calculation result of the syndrome 128 from the syndrome calculation circuit 121 and the error position 130 from the Chien search circuit 123 and outputs the error value 131 to the error correction circuit 125.

The error correction circuit 125 corrects an erroneous code from the information of the error value 131 and the error position 130, and
The corrected code output 127 is output. Further, since a delay occurs due to the processing from the calculation of the syndrome 128 to the derivation of the error value 131, the delay code 132 input to the error correction circuit 125 has the same amount as the delay due to the processing from the syndrome calculation to the derivation of the error value 131. Delay circuit 12
6, the timing is adjusted.

The multipliers 1 and 2 having the circuit configuration of FIG.
2, 3, 4, a switch 13, and registers 9, 10, 1
1, 12, multipliers 5, 6, 7, 8 and adders 14, 1
5 is integrated by a gate array,
Weight is reduced. Similarly, the circuits of FIGS. 3, 5, and 6 can be reduced in size and weight by being integrated.

[0088]

As described above, the Chien search circuit of the present invention can perform calculation processing in parallel with a small-scale circuit, and thus has the effect of reducing the calculation time.

Also, when real-time processing is required for the input of the received code of the error correction decoder, the calculation per circuit can be made longer than the conventional one-column processing by performing the calculation in parallel. Therefore, there is an effect that it becomes possible to cope with high-speed processing for high-speed reception code input.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a Chien search circuit of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a block diagram showing a second embodiment of the Chien search circuit of the present invention.

FIG. 4 is a time chart showing the operation of FIG. 3;

FIG. 5 is a block diagram of a generalized form of the circuit of FIG. 1;

FIG. 6 is a block diagram of a generalized form of the circuit of FIG. 3;

FIG. 7 is a block diagram showing an example in which the Chien search circuit of the present invention is applied to an error correction code decoding device.

FIG. 8 is a block diagram showing an example of a conventional Chien search circuit.

[Explanation of symbols]

 1,2,3,4 Multiplier 5,6,7,8 Multiplier 9,10,11,12 Register 13 Switcher 14,15 Adder 16,17 Addition result 18 Initial value selection signal 19 Clock input 21,22 , 23,24 Multipliers 25,26,27,28 Multipliers 29,30,31,32 Registers 33 Switchers 34,35 Adders 36,37 Addition results 38 Initial value selection signals 39 Clock inputs 41-49 Multipliers 50 -58 Multiplier 59-67 Register 68 Switcher 69-71 Adder 75-77 Addition result 78 Initial value selection signal 79 Clock input 81-89 Multiplier 90-98 Multiplier 99-107 Register 108 Switcher 109-111 Addition Units 115 to 117 Addition result 118 Initial value selection signal 119 Clock input 120 Received code input 121 Syndrome calculation Circuit 122 Error position polynomial calculation circuit 123 Chien search circuit 124 Error value calculation circuit 125 Error correction circuit 126 Delay circuit 127 Code output after correction 128 Syndrome 129 Error position polynomial 130 Error position 131 Error value 132 Delay code 141, 142 Multiplier 143, 144 Multiplier 145, 146 Register 147 Switch 148 Initial value selection signal 149 Clock input 150 Adder 151 Addition result

Claims (7)

[Claims] In a Chien search circuit for calculating an error position in error correction, a multiplier that processes in parallel using a plurality of circuits and gives a different initial value to each of the circuits in parallel with the initial value of the order of the error position calculation. A chain search circuit comprising: 2. A Chien search circuit for calculating an error position in an error correction, wherein a plurality of circuits are used for parallel processing, and an initial value of the order of the error position calculation is sequentially calculated for the circuits in parallel. 1. A Chien search circuit comprising a multiplier for assigning an order of. 3. A Chien search circuit for calculating an error position in error correction, comprising: a first multiplier and a third multiplier for generating first and third multiplier outputs from first input data; A second multiplier and a fourth multiplier for generating second and fourth multiplier outputs from second input data; and inputting the first, second, third and fourth multiplier outputs A switch for simultaneously switching and outputting the same according to the initial value selection signal; and inputting the first, second, third, and fourth multiplier outputs output from the switch, and temporarily storing the output by a clock input. First, second, third, and fourth registers that are output as first, second, third, and fourth register outputs; multiplying the first, second, third, and fourth register outputs; The multiplied output is the first, second, third,
Fifth, sixth, seventh, and eighth multipliers that output to the switch for feedback to the input of the fourth register itself; and output of the first and second registers and a constant value “1”. Add
A first adder for outputting a first addition result; adding the third and fourth register outputs to a constant value “1”;
And a second adder 15 for outputting a result of the addition. 4. The apparatus according to claim 3, wherein the first, second, third, and fourth multipliers have different initial values of the order of error position calculation. Chain search circuit. 5. The Chien search circuit according to claim 3, wherein the first, second, third, and fourth multipliers are set so as to sequentially assign the order of error position calculation. . 6. The first to eighth multipliers, the switch,
6. The Chien search circuit according to claim 3, wherein the first to fourth registers and the first and second adders are integrated by a gate array. 7. A syndrome calculation circuit that performs a syndrome calculation from a received code input and outputs a syndrome;
An error locator polynomial calculation circuit for deriving an error locator polynomial by the syndrome; a Chien search circuit for calculating and outputting an error location using the error locator polynomial; and calculating and outputting an error value from the error location and the syndrome. An error value calculating circuit to perform; a delay circuit that outputs a delay code obtained by delaying the input of the received code by the same amount of delay by processing from syndrome calculation to the derivation of the error value; An error correction circuit that corrects an erroneous code based on an error value and the information on the error position and outputs a corrected code output.
An error correction code decoding apparatus comprising the Chien search circuit according to 2, 3, 4, 5, or 6.