JPS6394720A - Decoding circuit for error correction code - Google Patents

Abstract

PURPOSE:To constitute simply a decoding circuit for a long code word by operating a chain search circuit section and an address generating circuit synchronously so as to constitute the decoding circuit using a conventional memory in place of a multi-stage shift register. CONSTITUTION:The chain search circuit 26 inputs an error location polynomial from a definite field arithmetic circuit 23, its chain search circuit section 18 starts chain search and returns an address corresponding to roots of the error location polynomial to the definite field arithmetic circuit 23. Its address output is outputted from an address genetating circuit 19 decremented synchronously with the chain search circuit 18 in the chain search circuit 28. Thus, the definite field arithmetic circuit 23 calculates the error from the result of chain search to correct the content represented at an error location address in a delay memory 24 received precedingly from the chain search circuit 26.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding circuit for error correction codes.

[Prior Art] In general, when a computer performs various processes, a system for correcting errors in a large number of bytes in a code word is required, and various systems have been proposed.

In such an error correction system, a method for decoding a plurality of byte errors is generally performed as follows. First, calculate the error syndrome, then determine the coefficients of the error location polynomial from this error syndrome, identify the error location from the error location polynomial using Chien search, and calculate the byte error value for each error location. It is decided.

By the way, FIG. 4 is a block diagram showing a chain search circuit similar to that shown in the conventional Japanese Patent Laid-Open No. 59-123945.
haudhuri-Hocquenghem-Code
This is a circuit used in applications such as s). In this Figure 4, 1 is an n-bit register, 2 is an adder circuit, 3 to 7 are constant multiplication circuits for the Galois field GF(271) (n is a natural number)-L code word, and 8 is an error locator polynomial. This is an output terminal that indicates that the sum of is zero.

Further, FIG. 3 is a circuit diagram showing an example of a conventional BCH code decoding circuit. In FIG. 3, 9 is a multi-stage shift register for delaying the received code word, 1O is an adder circuit, 11 is a syndrome calculation circuit, 12 is an error locator polynomial derivation circuit, 13 is a chain search circuit, 14 is a synchronization circuit,
15 is a sequence control circuit, 16 is an input terminal for a received code word, and 17 is an output terminal for corrected information.

Binary B in Figure 3 using the chain search circuit shown in Figure 4
The operation of the CH code decoding circuit will be explained.

First, when a received code word is input from the input terminal 16 and input to the synchronization circuit 14, the synchronization circuit 14 detects the beginning of the received code word. Then, the sequence control circuit 15 operates based on this detection result.

On the other hand, the received code word is simultaneously transmitted to the synchronization circuit 14 and the syndrome calculation circuit 11. It is also input to the multistage shift register 9.

Thereafter, the syndrome calculated by the syndrome calculation circuit 11 is input to the error locator polynomial deriving circuit 12, and an error locator polynomial is derived.

The error locator polynomial from the error locator polynomial deriving circuit 12 is input to a chain search circuit 13 to execute a chain search. Here, in the chain search circuit 13 shown in FIG. 4, the error polynomial is σ(X)=σ0+σ□8+σ2x2+
...+C1t-0xt~1, first the count of each term of this error locator polynomial is set in n-bit register 1, and then the clock is input to each register 1. . After that, when several clocks are input, the output of the output terminal 8 becomes zero, but if the number of clock inputs at this time is i, α2 becomes the root of σ(x). This process is called chain search. At the same time, the received code words are sequentially output to the output side of the multi-stage shift register 9 from the beginning. This output is synchronized with the execution of the chain search in the chain search circuit 13, and when the root of the error locator polynomial σ(x) is detected by the chain search, the output of the multistage shift register 9 is added to the adder circuit. 10.

[Problems to be Solved by the Invention] Conventional error correction code decoding circuits are configured as described above. There was a problem that the number of stages of the shift register was large.

This invention was made to solve the above-mentioned problems, and its purpose is to provide an error correction code decoding circuit that enables decoding without using the conventionally required multi-stage shift register. do.

[Means for Solving the Problems] The error correction code decoding circuit according to the present invention provides a delay memory for storing received code words in place of the multi-stage shift register so as to be able to calculate the speaking position. In addition, an address generation circuit operating in synchronization with the chain search circuit section is provided to enable calculation of an error position address in the delay memory.

[Function] In the error correction code decoding circuit of the present invention, the received code word is stored in the delay memory, and the address generation circuit operates in synchronization with the chain search circuit section, thereby decoding the data in the delay memory. Calculate the error location address.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Now, the Reed-Solomon code that corrects codeword errors in the Galois domain G F (27+) has multiple checkpoints corresponding to the roots of the generator polynomial. This is a decoding circuit for an error correction code having a chain search circuit for finding the root of an error locator polynomial in this Reed-Solomon code, similar to the one shown in FIG.

In FIG. 1, 23 is a finite field calculation circuit capable of performing finite field calculations such as deriving error locator polynomials and error value polynomials, and 24 is a delay unit that stores received code words in order to decode the code words. 25 is a syndrome calculation circuit, and 26 is a chain search circuit. This chain search circuit 26, as shown in FIG. Prepared. This address generation circuit 19 is configured for subtraction counting operation. In FIG. 2, 20 is a clock input terminal, 21 is an output terminal of the address generation circuit 19, and 2 is a clock input terminal.
2 is an output terminal indicating that the output of the output terminal 21 has detected the root of the error locator polynomial.

In addition, the finite field calculation circuit 23. The delay memory 24 and the chain search circuit 26 are connected by a data bus 27 and a control bus 28, respectively, as shown in FIG.

Furthermore, one port of the memory 24 is connected to an external data bus 2.
9, and inputs the received code word and outputs the corrected code word.

Next, the operation of this circuit will be explained. After the received code is inputted to the delay memory 24 from the external data bus 29.

Thereafter, the syndrome of the received code word input to the memory 24 is calculated by a syndrome calculation circuit 25. Furthermore, the finite field arithmetic circuit 23 derives an error locator polynomial and an error numeric polynomial from the syndrome. The chain search circuit 26 converts the error locator polynomial into the finite field arithmetic circuit 2.
3, the chain search circuit section starts the chain search at 8, and returns the address corresponding to the root of the error locator polynomial to the finite field arithmetic circuit 23. This address output is outputted from the address generation circuit 19 which performs a subtractive counting operation in synchronization with the chain search circuit section 18 in the chain search circuit 26. As a result, the finite field calculation circuit 23 calculates the error value from the result of the chain search, and first the chain search circuit 26 calculates the error value from the result of the chain search.
The contents indicated by the error position address in the delay memory 24 received from the CPU are corrected. At this time, data and control signals are exchanged through a data bus 27 and a control bus 28. Thereafter, the corrected output is sent to the external data bus 29 through the memory 24.

In this way, the address generation circuit 19 operating in synchronization with the chain search circuit section 18 calculates the error position address in the memory 24, and the finite field arithmetic circuit 23 and the delay memory 24 storing the received code word are used. Since the error correction code can be decoded and outputted through the encoder, a multi-stage shift register as in the conventional case is not required.

It should be noted that the above embodiment is applicable to non-binary cases that require calculation of error values.
This is the case of decoding an original code word, but it can also be applied to decoding a binary code word that does not require the calculation of error values. In this case, the address output of the chain search circuit 26 is used to Just reverse the contents.

[Effects of the Invention] As described above, according to the present invention, by operating the chain search circuit section and the address generation circuit in synchronization,
Instead of multi-stage shift registers, the decoding circuit can be configured using general-purpose memory, so decoding circuits for long-distance codewords, which was previously considered difficult, can be constructed by simply preparing memory for the code length, making it relatively easy. It has an effect that can be easily configured.

[Brief explanation of the drawing]

1 and 2 show a decoding circuit for an error correction code according to an embodiment of the present invention. FIG. 1 is a block diagram showing its overall configuration, and FIG. 2 is a block diagram showing its chain search circuit. FIG. 3.4 shows a conventional error correction code decoding circuit, FIG. 3 is a block diagram showing its overall configuration, and FIG. 4 is a block diagram showing its chain search circuit. In the figure, 18-Chien search circuit, 19-Address generation circuit, 20-Clock input terminal, 21-Address generation circuit output terminal, 22-Chien search circuit output terminal, 23-Finite field arithmetic circuit, 24-Delay memory, 25
- syndrome calculation circuit, 26 - chain search circuit, 27 - data bus, 28 - control bus, 29 -
External data bus. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In an error correction code decoding circuit equipped with a chain search circuit unit that finds the root of an error locator polynomial for a code word on a Galois domain GF (2^n), it operates in synchronization with the chain search circuit unit. What is claimed is: 1. A decoding circuit for an error correction code, comprising: an address generation circuit for generating a received code word; and a delay memory for storing a received code word. (2) The error correction code decoding circuit according to claim 1, wherein the address generation circuit is configured as a subtractive counting circuit.