JPS63274221A - Error correction decoding system - Google Patents

Abstract

PURPOSE:To attain high speed decoding for an error correction code by detecting error locations being a number less than a number (n) of correctable words by one and calculating the remaining error location based on the error location and a coefficient of an error location polynomial so as to decrease the expected value of the arithmetic operations into (n-1)/n. CONSTITUTION:A value corresponding to n-set of error locations is obtained in the decoding for an error correction code used to correct plural and lots of words such as a BCH code or a reed solomon code used for a recording and reproducing device such as an optical disk or a magnetic disk or the signal transmission. Moreover, an arithmetic section is provided, which adds (n-1)-set of values corresponding to (n-1) error locations obtained by an error location polynomial and coefficients being n-set of addends corresponding to n-set of locations being coefficients of the error location polynomial. Furthermore, (n-1)-set of coefficients corresponding to (n-1)-set of error locations are obtained from the error location polynomial, and coefficients being those of the error location polynomial and n-set of addends corresponding to the n-set of error locations and the (n-1)-set of values are added to calculate the n-th value corresponding to the n-th error location. Thus, the calculation time of the error locations is shortened and the decoding of the error correction code is quickened.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to error correction codes that correct multiple words, such as BCH codes and Reed-Solomon codes, which are used in recording and reproducing devices and signal transmission using optical disks, magnetic disks, etc. Concerning the decoding method.

[Prior art]

Conventionally, in decoding BCH codes and Reed-Solomon codes, error locator polynomials are obtained from syndromes and error locators are calculated using Cheno's algorithm.

Cheno's algorithm consists of sequentially substituting elements other than "0" of the Galois field used for error correction into the error locator polynomial, finding elements for which the operation result is 0 for the number of error words, and then The error position is calculated based on.

Therefore, in the error correction code of the 4-word correction of the extended Galois field GF (2'), for example, among the non-zero elements α0, α1, α2, ..., α2S4 of GF (28), α
If an error occurs at the positions corresponding to 0, α1, α2, and α254, 255 calculations must be performed for α0 to αzsa, resulting in a problem that decoding takes time.

〔the purpose〕

The present invention provides a method for calculating error positions in decoding error correction codes that correct multiple words, such as 13C)i codes and Reed-Solomon codes, which are used in recording/reproducing devices or signal transmission using optical disks, magnetic disks, etc. The purpose is to shorten the error correction code and speed up the decoding of error correction codes.

〔composition〕

The configuration of the present invention will be described based on an embodiment in which it is applied to a 4-word corrected Reed-Solomon code in Galois field GF(2B). That is, 28-1=255 received words r, , r, , H+H+** including parity.

r23. Four-word correction is performed on the received word string consisting of .

The Reed-Solomon code is decoded using the following 5 steps:
In other words, ``(11) Find the syndrome.

(2) Find the error locator polynomial from the syndrome.

(3) Find the error position from the error position polynomial.

(4) Find the error pattern from the error position.

(5) Correct the error based on the error position and error pattern.

However, according to the present invention, the calculation for determining the error position in step (3) is performed at high speed.

The above received word string is expressed as a polynomial, R(x) ” r6 X”' + r 1 K +・
"+ r z5a """+11, syndrome 80~S is So "R(12e')"re
+r, +・++j, S.

S,=R(cx')xroa"' + r,a"" +
-+ r,,.

S? -R(α')! f6 Cl””ff+rl
αtS”7+−+ rz54.

Now, in the case of correcting a 4-word error, if the elements α0 to α2S4 (hereinafter simply referred to as error positions) of GF (2'') indicating the error position are V, ~v4, then the error position polynomial σ. , σ.) = (X 10V1) (X +1h) (x
+V3) (X +VJ ・・・・・・(2)== x
4 +σ x3 +σ xt +σ, X+σ.・・・・・・・・・
(3), and the coefficient σ of each term shown in the above equation (3), ~σ
. There is the following relationship between , nibe, and /drome S0 to S7.

Then, the above error locator polynomial σ(. is the syndrome S
If even one of S7 to S7 is not O, the coefficient of each term of the old formula (3) is calculated by Peterson, Berlecumb-Mafsey, Euclid's algorithm, etc. based on the syndrome and the above formula (4). σ.

~σ. is calculated, and the corresponding old style (2) glue.

Vz, V2, and V4 are error positions, that is, values of any of the elements α0 to α2S4 other than O of the Galois field GF(2″).

For example, if an error occurs in ro j I pr2s4, V, etc. are a"', α"", txo
As mentioned above, by sequentially substituting the elements α0 to α2S4 other than O of the Galois field GF(2'') into the error locator polynomial σ(.), when αO, α1%!, α2S4 are substituted, Equation (2) is obtained. As can be seen from the above, σ axis)=0, and α0 and α2S3.αzsa are determined to be error positions.

Now, expanding the old formula (2), σ(3+) = (x +L)(x +Vz)(x
”V:1)(X +V4)x4 + (V, +V, +v, +v4)x3 + (VIV!+VIV3 +VIV4+V2V5 +
VzV4+V3V4) x”+(LVzVs + V
IVzV4+V1V3V1 + V2V3V4) X
+VIV2V*Vn・・'・”(51), and when comparing this formula (5) with the old formula (3), '3
=Vl+V2+V:l+V4 ””
”(6)6 z =V1V2+V1V3+VIV4+
VzV3+V2V4+VEILσ, =V, V2V1
+V+V2V4+V+V*L+VzVsLσ. =LVz
VsL, and from the above formula (6), Vl,=V+ tovt+v,+a 3
・・・−・+7) is obtained, so 4
When performing word correction, if three error positions are found, the fourth error position can be found from the above equation (7).

Therefore, once the third error position is found, there is no need to perform calculations by substitution of elements like Cheno's algorithm; for example, three error positions are detected at the beginning of the received word string. In some cases, the calculation speed can be significantly increased.

In addition, the error locator polynomial is expressed as a dual formula to the old formula (2), σ(X
) =< 1 + xL) (1+ xlh) (1+
XV3) (1+ XV4) = σ4'x4+σ3'x3 ten σ2'x! When +σ+'X+1, σI' =v, +v, +v, +%l.

That is, Va "Vl +v, + V3 + 61'
”=(8), and the above formula (
8) can be used.

FIG. 1 is a diagram showing a circuit for determining the error location of the embodiment, in which the error location polynomial σ(8) has an element α0. Three error positions are obtained by sequentially substituting α1, . . . , and the fourth error position is calculated based on the old formula (7).

As shown in the figure, there are four multipliers that individually calculate the first to fourth terms (fourth to first order terms) of the old formula (3).
, a selector 2, a register 3, and a multiplier 4 are connected in a loop.

For example, in the multiplier 3, when the coefficient σ of the error locator polynomial (σ axis) is input to the register 33 via the selector 23 and latched at the beginning of error locator detection for the - set of received word strings, From this register 38 is σ. , to α
When O is substituted, "σ," is output as the value of the second term. Further, this “σ3” is also output to the multiplier 4s and multiplied by α3, and the multiplied value “σ, α3” is applied to the register 33 via the selector 23 which is switched after the input of σ.

When the clock signal output from the arithmetic control unit 1 is applied to the register 33 as an operation corresponding to the sequential assignment of the elements α1, α2, . . . , the value “σ,” output from the multiplier 43, "α3" is latched in the register 33, and is output from the register 38 to the multiplier section 3 as a value obtained by substituting "α1" into the second term.

Similarly to 8 for this multiplication section, 4. for other multiplication sections. 2, 1 is the element α0 in the first, third and fourth terms of the old formula (3),
The values obtained by sequentially substituting α1, .

Then, 1 to 4 to each multiplier and the output value of register 5, that is, the value of each term of equation (3) output for each clock signal output by the arithmetic control unit 1, are sent to the adder by 1 to A4. The elements α0, α1, .
.

This output control unit 6 outputs a data valid signal (DV) when the value of the input error locator polynomial is 0'', and also outputs a select signal to the selector 7.
Furthermore, a strobe signal is output to the register 13 of the final error position generation circuit section 10, which will be described later.

On the other hand, the fifth multiplier Ks is configured in the same manner as the upper first to fourth multipliers 1 to 4. α0, α1, etc., which indicate the position of the received word in the received word string in synchronization with the assignment to the error locator polynomial σ(.) by the clock signal.
are generated sequentially. In other words, “αo=1” as the initial value
are latched and outputted to the register 35 via the selector 2s, and the multiplier 45 sequentially multiplies the values "α1, α2, . . ." by sequentially outputting the values "α1, α2, . . .".

The value indicating the position of the received word output from 5 to this fifth multiplier is applied to the selector 7, and
When a select signal is applied from the selector 7, a value indicating the position of the received word, that is, an error position V is outputted from the selector 7.

Further, the value indicating the position of the received word outputted by 5 to the fifth multiplier is outputted to the final error position generating circuit 10, and the final error position generating circuit 10 controls the adder 11 and the selector 12. The signal is applied to the register 13 via the register 13.

In this register 13, the coefficient "σ3" of the second term of the error locator polynomial inputted to l is latched as an initial value in the multiplication section, and this launched "σ," is applied to one side of the adder 11. is applied to the input terminal of

Then, when an error position is detected, the output control section 6
The register 13 performs a latch operation according to the strobe signal output by σ3 +%I every time an error position is detected.

σ3 +v, +v.

are sequentially latched, and when the third error position is detected, σ, + VI + Vz + Vs are latched and outputted via the selector 7 as the fourth error position.

In this way, an error pattern is determined based on the obtained error location, and the received word in which the error occurs is corrected.

In the above embodiment, the case where the code is applied to a 4-word correction Reed-Solomon code in the Galois field GF (2') has been described, but the present invention is not limited by the size of the Galois field or the number of error corrections. , also lead
Similar processing can be performed for error correction codes other than Solomon codes (for example, BCH codes) in which error positions are determined using Cheno's algorithm.

〔effect〕

According to the present invention, the number of error positions that are one less than the number of correctable words n is detected, and the remaining error position is calculated based on the error position and the coefficient of the error position polynomial. From the operation using Cheno's algorithm,
The expected value of the number of operations can be reduced to (n-1)/n, and the error correction code can be decoded at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an error position detection circuit in an embodiment of the present invention.

Claims (1)

[Scope of Claims] In an error correction decoding method in which values corresponding to n error positions are determined from an error position polynomial in decoding of an error correction code that corrects a plurality of errors, An arithmetic unit is provided that adds n-1 values corresponding to error positions and a coefficient of an error position polynomial that is the sum of n values corresponding to n error positions. Find the n-1 values corresponding to the error positions from the error position polynomial, and calculate the coefficients of the error position polynomial that are the sum of the n values corresponding to the n error positions, and the n-1 values above. and the value of nth
An error correction decoding method characterized in that an n-th value corresponding to an error position is calculated.