JPH05315974A - Decoding device for reed-solomon code - Google Patents

Abstract

PURPOSE:To provide a Reed Solomon code decoding device capable of rapidly and flexibly dealing with various decoding strategy and attaining excellent correction ability at the time of correcting an error generated at the time of recording/reproducing rapid compressed information in high density recording. CONSTITUTION:The decoding device is provided with an input part 10 for computing syndrome (b) in accordance with input data and forming the number of positions disappearing from a disappearing flag at the time of disappearance correction, a polynomial forming part 11 connected to the input part 10 to find out the coefficients of respective degrees of an error position polynomial (d) and an error evaluating polynomial (e) based upon a result outputted from the input part 10, and a polynomial evaluating part 12 connected to the forming part 11 to substitute a Galois body source to the error position polynomial (d) and the error evaluation polynomial (e) and find out an error position (f) and an error value (g).

Description

Detailed Description of the Invention

[0001]

This invention relates to digital video
The present invention relates to an apparatus for correcting an error generated in a digital data recording / reproducing apparatus such as a tape recorder, and more particularly to a Reed-Solomon code decoding apparatus.

[0002]

2. Description of the Related Art Generally, a digital video tape recorder (VTR) developed for broadcasting is capable of recording a high-quality image and also deteriorates the image quality no matter how many times it is dubbed. There is a particular advantage to digital recording that it does not. However, since the digital VTR for broadcasting suppresses the occurrence of errors during reproduction, the recording / reproduction is performed at a relatively low recording density, so that the tape consumption amount increases.

In order for the digital VTR to become popular for household use, it is necessary to develop a signal processing method capable of suppressing the tape consumption amount, and research on image compression technology and high density recording technology is active.

However, since the redundant information of the original image is lost by the image compression, it is difficult to compensate the correction omission, and the error at the time of reproduction increases due to the deterioration of the use environment and the high density recording. Therefore, the home digital VTR is required to have a high error correction capability.

Further, since the image is compressed to about ⅛ of the original image information, the correction processing speed may be about ⅛ of the broadcast digital VTR, but the digital audio is still used.・ Tepleco
Compared to digital audio equipment such as DA (DAT)
High-speed processing of 10 times or more is required.

FIG. 4 shows a configuration example of the conventional error correction circuit described above.

The error correction circuit of FIG. 4 has an input unit 51 and an input unit.
Calculation unit 52 connected to 51, output unit connected to the calculation unit 52
53, input section 51 and delay section connected to output section 53, respectively
It is composed of 54.

Next, the operation of the error correction circuit of FIG. 4 will be described.

The error correction circuit of FIG. 4 performs the correction processing of (1) detection of syndrome generation and erasure position, (2) error position, calculation of error value and check of correction result, and (3) output of correction result. It is divided into 3 stages and each is executed by one pipeline.

For example, (1) In the syndrome generation and the detection of the disappearance position, the input section 51 is
The syndrome and the number of erasure positions are generated while one code passes, and the syndrome and the number of erasure positions are passed to the next pipeline.

Next, (2) in the calculation of the error position and the error value and the check of the correction result, the arithmetic unit 52 calculates the error value from the syndrome and the number of erasure positions according to the correction program according to the decoding strategy, and The correction result is checked from the calculated error position and error value, and the check result of the error position and error value is passed to the next pipeline.

(3) In outputting the correction result, the output unit 53 ends the correction process by adding the error value to the data corresponding to the error position calculated in the previous stage.

As described above, in the method of calculating the error position and the error value from the syndrome and the number of erasure positions according to the correction program, it is possible to flexibly optimize the correction algorithm according to the information such as the error tendency and the number of erasure flags. Can be decrypted.

[0014]

However, in the above-described conventional error correction circuit, when the number of errors to be corrected is relatively small such as 3 error correction and 4 erasure correction,
(2) The calculation amount required to calculate the error position and error value and check the correction result is small, and (2) the processing for calculating the error position and error value can be completed before one code passes. Although high-speed processing was possible, if an attempt was made to increase the correction capability such as 4 error correction or 8 erasure correction, the amount of calculation increased dramatically and the correction processing was limited, so the correction speed could be increased. There was a problem that it was difficult.

In view of the above-mentioned problems in the conventional error correction circuit, the present invention provides a Reed-Solomon code decoding device which can realize error correction with high efficiency even when data processing is performed at high speed.

[0016]

SUMMARY OF THE INVENTION The present invention is a Reed-Solomon code decoding apparatus in which each process is constituted by a separate circuit, and a decoding process is performed in a flow-wise manner by a pipeline process. An input unit that calculates the syndrome and generates the number of erasure positions from the erasure flag at the time of erasure correction, and obtains each coefficient of a predetermined polynomial based on the result output from the input unit that is connected to the input unit Achieved by a Reed-Solomon code decoding device that includes a polynomial generator and a polynomial evaluator that is connected to the polynomial generator and that finds the error position and error value by substituting Galois field elements for a given polynomial. To be done.

[0017]

In the Reed-Solomon code decoding apparatus of the present invention,
The input unit calculates the syndrome according to the input data and generates the number of erasure positions from the erasure flag at the time of erasure correction, and the polynomial generator is connected to the input unit and predetermined based on the result output from the input unit. The polynomial evaluator is connected to the polynomial generator, and the polynomial evaluator is connected to the polynomial generator to substitute the elements of the Galois field into a predetermined polynomial to find the error position and the error value, It is composed of a circuit and performs a decoding process in a pipelined manner by a pipeline process.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a Reed-Solomon code decoding apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a Reed-Solomon code decoding circuit which is an embodiment of the Reed-Solomon code decoding apparatus of the present invention.

The decoding circuit for the Reed-Solomon code shown in FIG.
Input unit 10, polynomial generation unit 11, polynomial evaluation unit 12, output unit 1
3 and the delay unit 14.

Before explaining the operation of the Reed-Solomon code decoding apparatus of FIG. 1, the error, correction, and erasure correction processing in Reed-Solomon code decoding will be described.

First, the case of error correction will be described.

In error correction, from the syndrome, an error locator polynomial σ (z) and an error evaluation polynomial ω which are predetermined polynomials are used.
(z) is established, and then the Galois field elements are substituted into these polynomials to derive the error position and the error value.

From the received code containing an error, according to the following equation:
Generate (nk) syndromes S _i .

[0025]

[Equation 1]

Here, Y _j is each symbol of the received code, and α is a primitive element of the Galois field.

The error locator polynomial σ (z) is

[0028]

[Equation 2]

It is defined as Here, p is the number of errors contained in the received signal, and X _i is called the number of error positions and has a value that uniquely represents the position of the error in the code. For example, Y _j
If (j = 0 to n-1) is incorrect, the number of positions is α ^j
Can be expressed as

The following relational expression holds between the syndromes S _{0 to} S _2p-1 and the coefficients of the error locator polynomial.

[0031]

[Equation 3]

[0032]

[Equation 4]

Solving the equation (4),

[0034]

[Equation 5]

[0035]

[Equation 6]

[0036]

[Equation 7]

Here, M _p can be expressed by the following equation.

[0038]

[Equation 8]

When the number of errors is p-1 or less, the equation (8) becomes zero. Therefore, the number of errors can be judged as the largest p that the equation (8) does not become zero.

From the syndromes S _{0 to} S _2p-1 , the syndrome polynomial S (z) is

[0041]

[Equation 9]

The error evaluation polynomial ω (z) is defined as
It is obtained by multiplying the polynomials shown in the following equation.

[0043]

[Equation 10]

When obtaining the error position, the elements of the Galois field are sequentially substituted into the equation (2) to obtain the solution z (= X _i ^-1 ) that gives the error locator polynomial σ (z) = 0. A method called search is used.

If the number of errors exceeds the correction range, the order of the error locator polynomial may differ from the number of solutions obtained by the Chien search. Therefore, the number of errors obtained by the polynomial generator and the Chien search may be different. The erroneous correction can also be detected by comparing the number of solutions obtained in.

When obtaining the error value, the formal derivative σ ′ (z) of the error locator polynomial is used to

[0047]

[Equation 11]

It can be expressed as At this time, zσ ′
Since (z) is equal to the sum σ _odd (z) of odd-order terms of σ (z), it can be expressed as the following equation.

[0049]

[Equation 12]

Since the value of σ _odd (X _i ^-1 ) has already been obtained when the solution is found in the Chien search, if ω (z) is evaluated at the same time as the Chien search, the error value can be efficiently determined. Can be derived.

Further, when deriving the coefficient of the error locator polynomial, the same correction can be performed by using the following expressions instead of the expressions (5) to (8).

[0052]

[Equation 13]

[0053]

[Equation 14]

[0054]

[Equation 15]

[0055]

[Equation 16]

At this time, since it is not necessary to perform the division of the Galois field, the arithmetic processing can be reduced and the division can be omitted even in the Galois field arithmetic circuit, and the configuration can be simplified.

In erasure correction, the error position in the received code is known in advance, so X _{i in} equation (2) is known. Therefore, it is possible to derive the error position and the error value without setting the error locator polynomial. However, in the present invention, as shown in the embodiment described in detail below, the processing after the Chien search is performed with error correction and erasure. The correction is standardized and dedicated hardware is used to speed up the process.

Therefore, as the erasure correction processing, the syndrome is generated, X _i is substituted into the equation (2) to derive the error locator polynomial as defined, and then the error evaluation polynomial is derived according to the equation (10). To do. The number of errors is equal to the number of erasures. The subsequent procedure for erasure correction is exactly the same as for error correction.

Next, the operation of the Reed-Solomon code decoding apparatus shown in FIG. 1 will be described.

In the case of error correction, the received code a containing an error
Is input to the input unit 10.

The input unit 10 generates (nk) syndromes S _{0 to} S _nk-1 based on the equation (1). The syndrome b, which has been generated, is sent to the polynomial generation unit 11, and the input unit 10
Starts to generate the syndrome b of the next received code a.

The polynomial generator 11 performs arithmetic processing in accordance with the program, determines the number of errors c from the syndrome b based on the equations (5) to (8), and determines the coefficient (σ ₀ to σ _p ) and then the coefficients (ω _{0 to} ω _p-1 ) of the error evaluation polynomial e from the error locator polynomial d and the syndrome b based on the equation (10).

The error position polynomial d and the error evaluation polynomial e derived by the polynomial generation unit 11 are sent to the polynomial evaluation unit 12.

When the syndrome b of the next received code a is input to the polynomial generator 11, the polynomial generator 11 repeats the above process again.

Further, the coefficients of the error locator polynomial d (σ _{0 to} σ
When deriving _p ), instead of Eqs. (5) ~ (8), Eqs. (13) ~
The correction can be performed in the same manner by using the expression (16), and since the Galois field division is unnecessary, the configuration of the arithmetic circuit included in the polynomial generator 11 can be simplified.

In the polynomial evaluation section 12, the error locator polynomial d and the error evaluation polynomial e are respectively evaluated by a polynomial evaluation circuit (not shown).

In the polynomial evaluation circuit, the elements of the Galois field (α ⁰ , α ^-1 , α ^-2 , α ^-3 , ..., α- ^{(n- 1)} ) are sequentially substituted into the polynomial and the value of the equation is calculated. However, when the error locator polynomial d is evaluated, by separating the sum (σ _odd ) of only odd-order terms from the sum of all order terms in equation (2), It is possible to find the wrong value.

When the solution of the error locator polynomial d is found by the Chien search, the error locator polynomial σ (z) =
However, at this time, the value of the sum (σ _even ) of only the even-order terms becomes equal to the sum σ _odd of the odd-order terms only, so the sum σ _odd of only the odd-order terms in equation (12). The result does not change _{even if} the sum σ _even of even-order terms is used instead of.

The error position f output from the polynomial evaluation unit 12 is the error position polynomial σ in the Chien search.
A set of z for which (z) = 0 is output, and as the error value g, the evaluation result of the expression (12) at each error position is output.

One method of checking the correction process is to send the number of errors c obtained by the polynomial generator 11 to the polynomial evaluator 12, and determine the number of solutions of the error locator polynomial d obtained by the polynomial evaluator 12. Judgment is made based on whether or not the count matches.

Another method of checking the correction process is
In the polynomial generator 11, the error locator polynomial d and the error evaluation polynomial e
There is a method that can be used when there is a syndrome that is not used when deriving the, but it is used to decode the received code a from the polynomial generator 11 according to the code configuration and error situation at that time. Syndrome q (S
_chk ) is sent to the polynomial evaluation unit 12, and the error position f derived by the polynomial evaluation unit 12 is compared with the syndrome b ′ calculated from the error value g to determine whether or not they match.

In the output unit 13, the error value g is assigned to the symbol corresponding to the error position f obtained by the polynomial evaluation unit 12 in the received code m delayed by the time required for decoding input from the delay unit 14. Correction processing is performed by adding.

Further, the check result h in the polynomial evaluation unit 12
If an erroneous correction is detected by, the uncorrectable flag (not shown) is output and the correction is not performed.

In the case of erasure correction, the erasure flag i is input to the input unit 10 together with the received code a.

Like the error correction, the input unit 10 uses (nk) syndromes b (S _{0 to} S _nk-1 ) based on the equation ( ₁ ).
In addition to generating, the number of disappearance positions j is generated from the position of the disappearance flag i in the code and sent to the polynomial generator 11.

The polynomial generator 11 performs arithmetic processing in accordance with the erasure correction program, derives the coefficients (σ _{0 to} σ _p ) of the error locator polynomial d from the number of erasure positions j based on equation (2), and then Similar to the error correction, the coefficients (ω _{0 to} ω _p-1 ) of the error evaluation polynomial e are derived from the error locator polynomial d and the syndrome b based on the equation (10).

The error position polynomial d and the error evaluation polynomial e derived by the polynomial generator 11 are sent to the polynomial evaluation unit 12.

Since the subsequent processing is the same as the case of error correction, the description will be omitted below.

FIG. 2 shows an example of the configuration of the polynomial generator 11 of FIG.

The polynomial generator 11 of FIG. 2 has a syndrome register-20, an erasure position number register-21, a data bus 22 ...
26, input registers 27 to 30, arithmetic circuit 31, arithmetic circuit 32, instruction read only memory (RO
M) 33, a program counter 34, an error position polynomial register 35, an error evaluation polynomial register 36, and a check register 37.

Next, the operation of the polynomial generator 11 of FIG. 2 will be described.

The syndrome b and the disappearance position number j output from the input unit 10 (see FIG. 1) are held in the syndrome register-20 and the disappearance position number register-21, respectively.

These data are the instruction R
It is selected by the instruction n stored in the OM 33 and output to the data buses 22 to 26.

The data buses 22 to 25 are connected to the input registers 27 to 30 of the arithmetic circuits 31 and 32, respectively.
28 is an arithmetic circuit 31, and the input registers 29 and 30 are processed by an arithmetic circuit 32.

Arithmetic elements 31e and 32e in the arithmetic circuits 31 and 32
Can perform addition and multiplication on the Galois field based on the instruction, and the operation result is stored in a specified address in the operation registers -31r and 32r based on the instruction.

The outputs of the operation registers 31r and 31r are connected to the data buses 22 to 26, and the read address is determined by the instruction independently for each bus.

The data bus 26 outputs the coefficient of each degree of the error locator polynomial d, the error evaluation polynomial e, the number of errors c, and the check syndrome q.

The address of the instruction ROM 33 is given by the program counter-34. Also, the program counter-34 is an instruction RO
Branch control is performed by M33, and the absolute or relative jump address for this is given from the instruction ROM33.

Several kinds of correction algorithms are prepared in the instruction ROM 33, and the correction mode, the code configuration, the number of erasures, and the number of errors c calculated by the polynomial generator 11 are stored.
It is possible to perform the correction processing at a high speed and flexibly to cope with an error situation by appropriately branching with, for example.

FIG. 3 shows an example of the configuration of the polynomial evaluation unit 12 shown in FIG.

The polynomial evaluation unit 12 of FIG. 3 is connected to the error position polynomial evaluation unit 40, the error position output unit 41 connected to the error position polynomial evaluation unit 40, the error position polynomial evaluation unit 40, and the error position output unit 41. Error value output unit 42, error value output unit 42
Syndrome check unit 43 and error value output unit 42 connected to
Error number output unit 44 and syndrome verification unit 43 connected to
And a check result output unit connected to the error count output unit 44
It consists of 45.

Next, the operation of the polynomial evaluation unit 12 of FIG. 3 will be described.

When evaluating the error locator polynomial d, the error locator polynomial evaluation unit 40 divides it into even-order terms and odd-order terms, and substitutes Galois field elements into each to obtain the value of the equation.

Since the error position output unit 41 finds a solution in the error position polynomial evaluation unit 40, the sum σ _e of even-numbered terms and the sum σ _o of odd-numbered terms become equal, so the Galois field to be substituted is The error position is obtained by gating the output of the error position pointer, which is synchronized with the source of, with the discovery signal.

Further, since the magnitude of the error is obtained by dividing the evaluation result ω of the error evaluation polynomial e by the sum σ _o of odd-order terms, the error value output unit 42 finds out like the error position f. An error value g is obtained by gating with a signal.

As a check of the correction result, the syndrome verification unit 43 compares the syndrome b'trial-calculated from the above error with the verification syndrome q sent from the polynomial generator 11, and if they match, the verification result is correct. to decide.

Further, the error number output unit 44 compares the counting result of the solution found by the Chien search with the error number c sent from the polynomial generating unit 11, and if they match, the error number c is determined to be correct. To do.

The check result output unit 45 displays the above-mentioned syndrome.
The logical sum of the outputs from the error check unit 43 and the error number output unit 44 is output as the check result h output from the polynomial evaluation unit 12.

[0099]

EFFECT OF THE INVENTION Reed-Solomon code decoding apparatus of the present invention
Configures each process with a separate circuit for pipeline processing.
Therefore, a Reed-Solomon code that performs decoding processing in a streamlined manner
Decoding device for the syndrome
And erase from the erasure flag at the time of erasure correction
An input unit for generating the number of positions and an input unit connected to the input unit.
Each order of a given polynomial based on the result output from the force section
Connected to the polynomial generator that finds the coefficient of
And assign Galois field elements to the given polynomial
It is equipped with a polynomial evaluator that determines the position and error values.
Therefore, it is possible to respond to the decoding strategy quickly and flexibly.
Therefore, when recording and reproducing high-speed compressed information in high-density recording
Excellent correction capability can be achieved when correcting errors that occur in
There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a Reed-Solomon code decoding apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration example of a polynomial generator that constitutes the decoding device in FIG.

FIG. 3 is a block diagram showing a configuration example of a polynomial evaluation unit that constitutes the decoding device in FIG.

FIG. 4 is a block diagram showing a configuration example of a conventional error correction circuit.

[Explanation of symbols]

 10 Input section 11 Polynomial generation section 12 Polynomial evaluation section 13 Output section 14 Delay section

Claims (1)

[Claims] 1. A Reed-Solomon code decoding device in which each process is configured by a separate circuit to perform a work flow decoding process by pipeline processing, wherein a syndrome is calculated according to input data and erasure correction is performed. An input unit that sometimes generates the number of disappearance positions from the disappearance flag, a polynomial generation unit that is connected to the input unit and calculates each coefficient of a predetermined polynomial based on the result output from the input unit, and A Reed-Solomon code decoding device, which is connected to a polynomial generator and which includes a polynomial evaluator that substitutes an element of a Galois field into the predetermined polynomial to obtain an error position and an error value.