JPH06104771A - Bit-error correction method and decoder for it - Google Patents

Abstract

PURPOSE: To provide a decoder for correcting a bit error generated in a BCH code by comparing the number of errors in an error test word, inverting the respective bits of received word with the number of bit errors in the respective work and correcting the number of errors in the received word. CONSTITUTION: An error test work generator 100 generates a large number of error test words R(j) (x), by inverting the respective bits of received word R(x). Next, a syndrome calculation circuit 200 determines a number D of bit errors in the work R(x) corresponding to a syndrome Si. At the same time, a matrix calculation circuit and a zero checking circuit 300 and 400, respectively determine the number D of bit errors corresponding to the error test word R(j), and a comparator circuit 500 successively compares it with the number D of bit errors in the received word R(x). In the comparison result, when the number D of bit errors in one error test word R(j) is less than the number D of bit errors in the received word R(x) just for '1', an error bit correction circuit 600 corrects the bit of received word R(x) corresponding to the error test word R(j) as an error bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder used in a receiving end of a data communication system for correcting a bit error of received digital data and a decoder implementing the error method.
In particular, the received digital data is BCH before it is transmitted.
(Bose-Chaudhuri-Hocquengh
em) coded.

[0002]

2. Description of the Prior Art In digital data communication systems that transmit digital information over a channel to a receiver, the received digital information often contains many bit errors due to noise and / or distortion. BCH to overcome this problem
Coding and decoding techniques are often used. The BCH encoding and decoding techniques are Bose-Caud and independently.
Developed by huri-Hocquenghem.

Referring to FIG. 1, a schematic diagram of a digital communication system is shown. In digital communication systems,
The transmitter includes a BCH encoder 1 and a modulator 2, and the receiver includes a demodulator 4 and a BCH decoder 5. The message information to be transmitted is first converted into a series of binary words, each having a bit length of k as shown in FIG. Binary words of message information are often represented by the polynomial I (x) of degree:

I (x) = I ₀ + I ₁ · x + I ₂ · x ² +
... + I _k-1 · x ^k-1 where I _p , p = 0, 1, 2, ..., K-1 are bits forming a binary word, I ₀ is a least significant bit, and I _k-1 is the most significant bit. Each binary word I
(X) is processed by the BCH encoder 1 in such a way that a number of check bits are added to the least significant bit I ₀ to form a codeword having a bit length of n, and the following polynomial C (x) It is represented by.

C (x) = c ₀ + c ₁ · x + c ₂ · x ² +
... + c _n-1 · x ^n-1 where c ₀ to c _nk-1 are check bits, and c
_nk to _{cn -1} are information bits. The codeword is then modulated by the modulator 2 for transmission and transmitted via channel 3 to the receiver of the communication system. The modulator 4 demodulates the received signal into a series of binary words, each corresponding to a codeword. If the received word is free of bit errors, the bit pattern is the same as the corresponding codeword. Otherwise, the bit pattern of the received word is different from the corresponding codeword, and the difference between them is called the error pattern of the received word. The error pattern can be represented by a polynomial of the following equation: E (x) = e ₀ + e ₁ · x + e ₂ · x ² + ... + e _n−1 ·
x ^n-1 Therefore, the received word R (x) can be represented by the following formula: R (x) = C ( x) + E (x) = r 0 + r 1 · x + r 2 · x 2 + ... + r n _-1.xn ^-1 A BCH decoder 5 is used which detects whether a bit error has occurred in each of the received words and performs the necessary corrective action on the error bit.

If the BCH decoder technique used here allows the BCH decoder 5 to detect and correct at most t error bits in each received word, the codeword is [n, k, t] represented as a binary BCH code,
Where n is the block length of the codeword and n = 2
^m -1, m is an integer

[0007]

[Equation 1]

K is the number of information bits of the codeword

[0009]

[Equation 2]

T is the maximum number of bit errors to be corrected. For a fuller and more detailed understanding of the BCH code, the reader is Shurin and Daniel J. Costello.
See the book Error Control Coding: Basics and Applications, written by Jr. and published in Prentice Hall.

If the total number of bit errors is less than or equal to t, where t is a predetermined number, then the bit error generated in the received binary word encoded in the t error correction binary BCH codeword is: , All can be corrected faithfully. The larger t is selected, the longer the check bit length in the codeword and the more complex the decoding process. The methods of decoding the binary BCH code include the iterative algorithm proposed by Berlekamp, the search algorithm proposed by Chen and the step-by-step decoding method proposed by Massy et al. However, hardware decoders using these methods are considered to be very complicated in structure and slow in decoding. Therefore, there is still a need for a method that is less complicated to construct a hardware decoder and that enables more efficient decoding.

[0012]

DISCLOSURE OF THE INVENTION The object of the present invention is BCH.
It is to provide a more efficient decoding method for decoding codewords.

[0013]

According to the object of the present invention,
When receiving one of the received words R (x), j = 0,
N error trial word R for 1, 2, ..., N-1
^(j) (x) is generated by inverting each bit of the received word R (x). For example, R ^(j) (x) = R (x)
+ X ^j . Bit error number of received word R (x) and error trial word R ^(j) (x), j = 0, 1, 2, ..., N-
1 is determined in parallel when implemented in hardware, for example. If it is found that one error trial word, eg R ^(p) (x), has one less bit error number than the received word R (x), then R (x)
Bit x ^{p of} is an error bit and is therefore inverted.

[0014]

The present invention can be more fully understood by the detailed description of the preferred embodiments with reference to the accompanying drawings. α
Is a basic element in the Galois region GF (2 ^m ), (n,
k, t) The following generator polynomial G (x) of the binary BCH code, G (x) = g ₀ + g ₁ · x + g ₂ · x ² + ... + g _m · _t
X ^{m · t} has roots of α ¹ , α ² , ... α ^2t and is selected from the group of polynomials with minimum degree. M _i (x) = M _{i, 0} + M _{i, 1} · x + M _{i, 2} · x ² + ... +
Let M _{i, m} · x ^{m be} the minimum polynomial of α ¹ . Where the coefficient M _{i, p} ∈GF
(2), p = 0, 1, ..., M, and then G (x) is M
The least common multiple (LCM) of ₁ (x), M ₂ (x), ..., M _2t (x), for example G (x) ≡LCM {M ₁ (x), M ₂ (x), ..., M _2t
(X)}.

Since M _{i · 2p} (x) = M _i (x), p = 1, 2, ..., T, i = 1, 3, ..., 2t−1 are known, the generator polynomial G (x) Is simplified as shown below. G (x) ≡LCM {M ₁ (x), M ₃ (x), ..., M
_2t-1 (x)} The maximum degree of each minimum polynomial is m, and thus the degree of G (x) is at most m · t. For example, when t = 2, the degree of the generator polynomial G (x) is 2 m, and when t = 3, the degree of the generator polynomial G (x) is 3 m when m> 3.

As shown in FIG. 2, when I (x) is a polynomial corresponding to binary information and C (x) is a polynomial of BCH code of binary information, a code of I (x) to C (x). The conversion can be expressed mathematically as C (x) = I (x ) · x nk + Mod {I (x) · x nk / G (x)} = c 0 + c 1 · x + c 2 · x 2 + ... + c n-1 · x n-1 where And Mod {I (x) · x ^nk / G (x)} is G
It represents a remainder polynomial of I (x) · x ^nk divided by (x) and corresponds to the check bits [c ₀ , c ₁ , ..., C _nk-1 ] added to the binary information I (x). . Clearly C
(X) can be divided by G (x). Codewords encoded in the above manner are called systematic codewords.

Since R (x) = C (x) + E (x), the syndrome value of the received word R (x) can be calculated as:

[0018]

[Equation 3]

Syndrome values S _i , i = 1, 3, ..., 2
Each t-1 can be represented equivalently in the m-bit binary form as the polynomial S _i (x) S _i (x) = S _{i, 0} + S _{i, 1} · x + S _{i, 2} · x ² + ...
+ S _{i, m-1} · x ^m-1 First, the theorem that is the theoretical basis of the decoding method of the present invention will be described.

[0020]theoremFor [n, k, t] binary BCH code
Then, the syndrome matrix L _p,

[0021]

[Equation 4]

If is defined as:

[0023]

[Equation 5]

Here, p = 1, 2, ..., T, L _p is a singular number when the number of bit errors is p−1 or less, and
Not singular if the number of bit errors is exactly equal to p or p + 1. Therefore, there is a relationship between the number of bit errors and the syndrome value. That is, the number of bit errors of the t error correction binary BCH code is det (L ₁ ), det (L ₂ ),
,, det (L _t ). For example, d
If et (L ₄ ) = 0, it means that the number of bit errors must be less than or equal to 3. Therefore, the exact number of bit errors is det (L ₁ ), det
It can be determined by determining the zero of (L ₂ ), ..., Det (L _t ).

For example, in the double error correction BCH code,
For example, when t = 2, the determinant d for the number of error bits
The values of et (L ₁ ) and det (L ₂ ) are as follows: (1) In case of no bit error det (L ₁ ) = 0, det (L ₂ ) = 0; (2) One bit error If there is, det (L ₁ ) ≠ 0 det (L ₂ ) = 0; (3) If there are two bit errors det (L ₁ ) ≠ 0 det (L ₂ ) ≠ 0; Example of triple error correction BCH code , For example, at t = 3, the determinant for the number of error bits det (L ₁ )
The values of (L ₂ ) and det (L ₃ ) are as follows: (1) When there is no bit error det (L ₁ ) = 0, det (L ₂ ) = 0 and det (L ₃ ) = 0 (2) If there is one bit error, det (L ₁ ) ≠ 0, det (L ₂ ) = 0 and det (L ₃ ) = 0 (3) If there are two bit errors, det (L ₁ ). ≠ 0, det (L ₂ ) ≠ 0 and det (L ₃ ) = 0 (4) When there are three bit errors, det (L ₁ ) = x, det (L ₂ ) ≠ 0 and det (L ₃ ). ≠ 0; where x is any value that is either zero or non-zero and is not relevant to determining the weight of the error pattern.

The decision vector D consisting of t decision bits is defined as follows: D = [d ₁ , d ₂ , ..., D _t ] where p = 1, 2 ,. When det (L _p ) = 0, d _p = 0, and det (L _p ) ≠ 0 d _p = 1 Therefore, for the double error correction binary BCH code,
The decision vector may be expressed as: D = [0,0]; if there is no bit error; D = [1,0]; if there is one bit error; D = [1,1] For a triple error-correcting binary BCH code, the decision vector can be expressed as: D = [0,0,0]; If there is, D = [1,0,0]; if there are two bit errors, D = [1,1,0]; if there are three bit errors, D = [x, 1,1] four Decision vector [0,0,0], [1,0,0],
Since [1,1,0] and [x, 1,1] are different and distinguishable from each other, the number of bit errors in the received word can be determined accordingly. However, one important thing to note is that the above theorem is valid only if the total number of bit errors in the received binary word is less than or equal to t. The decoding method is not valid for received binary words with bit errors greater than t.

Before continuing the following description, the displays used thereafter will be described first. To represent a stream of 1 n identical bits,
The notation “1 ⁿ ”, and the notation “0 ^m ” are used to represent a stream of 0 m identical bits. Therefore, for the general case of t-error-correcting binary BCH codes, if there is no bit error, D = [0 ^t ]; if there is one bit error, D = [1,0 ^t-1 ]; If there are two bit errors, D = [1,1,0 ^t-2 ]; p bit errors, where

[0028]

[Equation 6]

D = [x ^p- 2,1,1,0 ^tp ]; If there is a bit error of t, D = [x ^t-2 , 1,1]; where the symbol "X" Indicates a don't care bit.

According to the invention, the received word R (x)
Each bit of is inverted to form an error trial word R ^(j) (x) that can be mathematically represented as: R ^(j) (x) = R (x) + ^xj , j = 0. , 1, 2, ...
n-1 By this operation, if the number of bit errors of the received word R (x) is w, and if the bit x ^j-1 of R (x) is the correct bit, then the error trial word R ^(j) ( The number of bit errors in x) is increased by 1 to w + 1; if bit x ^j-1 of R (x) is an error bit, then error trial word R
^(j) The number of bit errors in (x) is reduced by 1 to w-1.

The number of bit errors R ^(j) (x), j = 0, 1, 2, ..., N-1 corresponding to the error trial word can also be determined by the principle of Theorem 1. Therefore, the syndrome matrix L _p ^(j) corresponding to R ^(j) (x) is given by:

[0032]

[Equation 7]

Here, p = 1, 2, ..., T, j = 0,
1, 2, ..., N-, and S₁ ^(j), S ₂ ^(j),… Is wrong
Trial word R^(j)It represents the syndrome of (x). error
Trial word R^(j)Decision vector D for (x)^(j)Is below
Defined as the formula: D^(j)= [D₁ ^(j), D₂ ^(j), ..., d_t ^(j)], Where p = 1, 2, ..., T and j = 0, 1, 2 ,.
For n-1, det (L_p ^(j)) = 0, d_p ^(j)= 0 det (L_p ^(j)) ≠ 0, d_p ^(j)= 1.

Therefore, comparing the decision vector D ^(j) with the decision vector D, bit x of the received word R (x)
^j can be determined such that the correct bit is the error bit. Based on the above deduction, the decoding method of the present invention can be summarized as an algorithm including the following steps: Step (0): [n, k, t] BCH before being transmitted.
Receive a binary word R (x) encoded into a binary codeword; step (1): for j = 0,1,2, ..., n-1 n trial error words R ^(j) = R (x) + x ^j-1 ; Step (2): Syndrome S _{i of} received word R (x), i = 1, 2, ..., 2t and n error trial word R
^(j) , the syndrome of j = 0, 1, 2, ..., N-1, S
_i ^(j) , i = 1, 2, ..., 2t; Step (3): Determinant det (L _p ), p for the received word R (x) according to the matrix relation of Theorem 1
= 1, 2, ..., T and error trial word R ^(j) (x), j
Determinant det (L _p for = 0, 1, 2, ..., N-1
⁽ⁱ⁾ ), p = 1, 2, ..., t; Step (4): Determine the decision vector D of the received word R (x), where D = [d ₁ , d ₂ , , D _t ], in the case of det (L _p ) = 0, in the case of d _p = 0 det (L _p ) ≠ 0, d _p = 1 and the error trial word R ^(j) (x), j = 0 , 1, 2,
..., n-1 decision vector D ^(j) , j = 0, 1, 2,
..., n-1 is determined, where D ^(j) = [d ₁ ^(j) , d ₂ ^(j) , ..., d _t ^(j) ] det (L _p ^(j) ) = 0 , D ^(j) = 0 det (L _p ^(j) ) ≠ 0, d ^(j) = 1 step (5): The number of bit errors indicated by D is w and indicated by D ^(j) If the number of the bit errors is w-1, to perform the bit inversion to the bit x ^j of the received word R (x).

In the above decoding method of the present invention, the received word R (x) is converted into an error trial word R ^(j) , j = 0,
1, 2, ..., N-1 syndromes and decision vector determination can be performed together. The architecture of the parallel BCH decoder constructed by the decoding method will be described below. Hardware Implementation Decoder Structure of Decoding Method Referring to FIGS. 3 and 4, there is shown a schematic block system diagram of a parallel BCH decoder constructed according to the present invention. [N,
k, t] A BCH decoder for decoding a binary BCH code is shown.

The received word R (x) is the received word R (x), for example j = 0, 1, 2, ..., N-1.
In contrast, n error trial words R ⁽⁰⁾ (x), R ⁽¹⁾ (x), ... Formed by inverting one bit of R ^(j) (x) = R (x) + x ^j . It is first processed by error trial word generator 100 to generate R ^(n-1) (x).

Next, the word R (x) received according to the error trial words R ^(j) (x), j = 0, 1, 2, ...
00 is input. As shown in FIG. 4, the syndrome calculation circuit 200 is composed of an array of n + 1 identical syndrome calculation cells 210, each of which can generate the output of the syndrome of the input word.

The matrix calculation circuit 300 consisting of an array of n + 1 identical matrix calculation cells 310 obtains the syndrome value generated in the syndrome calculation circuit 200, and the determinant value det for the received word R (x).
(L _p ), p = 1, 2, ..., T and error trial word R
^(j) (x), used to generate determinant values det (L _p ^(j) ), p = 1, 2, ..., T for j = 0, 1, 2 ,. To be A zero check circuit 400 consisting of an array of zero check cells 410 is used to check if each determinant value is 0 or not. A binary signal of 0 is output when one determinant value is zero, and a binary signal of 1 is output when the determinant value is not zero. Each zero check cell 410 representing the decision vector of the input word is provided with an output bus consisting of t bit lines.

The decision vectors D and D ^(j) , j = 0, 1,
2, ..., N-1 are sequentially input together to a comparison circuit 500 including an array of n identical comparison cells 510. Each comparison cell 51
0 is the decision vector D decision vector D ^(j) , j = 0,
, 1, ..., N-1.
A decision vector, eg D ^(p) ,

[0040]

[Equation 8]

If it is found that any one of the corresponds to a bit error number that is one less than the decision vector D, then E
A binary signal with C _p = 1 is output, otherwise EC _p =
A binary signal of 0 is output. Bit [EC ₀ , EC ₁ ,
The bit vector consisting of EC ₂ , ..., EC _n-1 ] is nG
F (2) is added to the bits {r ₀ , r ₁ , r ₂ , ... R _n-1 } of the word R (x) received by the error bit correction circuit 600 including the array of the adder 610, and an error is generated, for example. The output word of the bit correction circuit 600 is the following arithmetic operation, output word = r ₀ + r ₁ · x + r ₂ · x ² + ... + r _n-1 · x ^n-1 + EC ₀ + EC ₁ · x + EC ₂ · x ² + ... + EC ^{_{n-1 · x n-1}} = (r 0 + EC 0) + (r 1 + EC 1) · x + (r 2 + EC 2) · x 2 + ... + (r n-1 + EC n-1) · x n The result is ^-1 .

The detailed circuit of the block consisting of the parallel BCH decoder of FIG. 3 will now be described together with an example invented to decode a (15,7,2) BCH code. (15,7,2) a schematic circuit diagram of a BCH code for the syndrome generating cell (15,7,2) syndrome generating cell for generating a syndrome of BCH code shown in FIG. S
_{Since 2} = (S ₁ ) ² is a known property, the syndrome-generating cells of FIG. 5 need only generate the syndrome values S ₁ and S ₃ . The circuit of FIG. 5 is a conventional syndrome calculation circuit, and its details will not be described.

(15, 7, 2) BCH code matrix
Calculus cell According to the matrix relation above,

[0044]

[Equation 9]

Therefore, det (L ₁ ) = S ₁ and det (L ₂ ) = (S ₁ )  (S ₂ ) + S ₃ = (S ₁ ) ³ + S _{3 are} derived.

As shown in FIG. 6, det (L₂) Is calculated
Matrix calculation cell is GF (2 ^Four) Cubic value generator 3
11 and GF (2^Four) Adder 312 may be used. GF
(2 ^Four) Cubic value generator 311 and GF (2^Four) Adder 31
The logical structure of 2 is a well-known technique, and its details are not described.
Yes.Zero check cell for (15,7,2) BCH code det (L₁) Value is equal to zero or not
To set, det (L₁) Is 4 bits
t (L₁If all bits of) are 0, advance to 0
Force, or det (L₁) Any one of the bits
First four inputs producing a binary output of one if is one
It is input to the OR gate 411. Similarly, the second four inputs
The OR gate 412 is det (L₂) Of determining zero
Used for. Therefore, the first 4-input OR gate 411
Output bit is d₁And the second 4-input OR gate 41
2 output bits are d₂Is.

The (15,7,2) BCH code comparison circuit decision vector D = [d ₁ , d ₂ ] is the error trial word R.
⁽⁰⁾ (x), R ⁽¹⁾ (x), R ⁽²⁾ (x), ..., R ⁽¹⁴⁾
Decision vectors D ⁽⁰⁾ , D ^{(1 )} , D corresponding to (x) respectively
⁽²⁾ , ..., D are input to all 15 comparison cells to be compared with ⁽¹⁴⁾ . For example, in one comparison cell corresponding to R ^(p) (x), E only if the following two conditions are satisfied:
C _p = 1: (1) Number of bit errors for R (x) = 1 R ^(p) Number of bit errors for (x) = 0 For example, D = [1,0] and D ^{(p )} = [0,0]; or (2) Number of bit errors for R (x) = 2 Number of bit errors for R ^(p) (x) = 1 For example, D = [1,1] and D ^(p) = [1,0].

The decision vectors D and D ^(p) are given by the following equations: D = [d ₁ , d ₂ ] and D ^(p) = [d ₁ ^(p) ,
d ₂ ^(p) ], the error correction bit EC _p is

[0049]

[Equation 10]

Can be represented by a Boolean function as EC _p
A comparator circuit constructed according to the above Boolean function for is shown in FIG. The comparator circuits corresponding to error trial words other than the exemplary R ^(p) (x) above are all the same as shown in FIG. The invention has been described with reference to exemplary preferred embodiments. However, it should be understood that the scope of the invention need not be limited to the preferred embodiments described. On the contrary, various modifications and similar arrangements are included within the scope defined by the claims. The claims should be construed broadly to include all such modifications and similar arrangements.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a digital communication system.

FIG. 2 is a diagram showing a bit pattern of a binary message word, a BCH codeword of the binary message word, and a received word corresponding to the BCH codeword.

FIG. 3 is a system diagram of a parallel BCH decoder invented by the present invention.

FIG. 4 is a system diagram showing a detailed configuration of a parallel BCH decoder shown in FIG.

FIG. 5 is a system diagram of a syndrome generator used in a (15,7,2) BCH decoder.

FIG. 6 is a system diagram of a matrix calculation cell and a zero check cell of a (15,7,2) BCH decoder.

FIG. 7 is a logic diagram of a comparison cell used in a (15,7,2) BCH decoder.

[Explanation of symbols]

 1 BCH encoder 2 modulator 3 channel 4 demodulator 5 BCH decoder 100 error trial word generator 200, 210 syndrome calculation circuit 300, 310 matrix calculation circuit 311 cubic value generator 312 adder 400, 410 zero-checking circuit 411, 412 4-input OR gate 500, 510 comparison circuit 600 error bit correction circuit

Claims (3)

[Claims] 1. In a system for transmitting digital information encoded in [n, k, t] binary BCH codewords from one location to another, (a) each received word R (x) By inverting the bits, n for j = 0, 1, 2, ..., N-1
Generate an error trial word R ^(j) (x); (b) received word R (x) and n error trial word R
^(j) Determine the number of bit errors in each of (x), j = 0, 1, 2, ..., N; (c) n error trial word R ^(j) (x), j = 0, 1,
2, ..., n-1 respectively comparing the number of bit errors of the received word R (x) with the number of bit errors of the received word R (x); (d) the received word R (x) in response to the comparison resulting from step (c). ), The method for correcting bit errors that occur in a word received during transmission. 2. In combination with a system for transmitting digital information encoded in [n, k, t] binary BCH codewords from one location to another (a) one received word R (x ), By inverting each bit, n = 0 for j = 0, 1, 2, ..., N-1
Means for generating an error trial word R ^(j) (x); (b) received word R (x) and n error trial word R
^(j) means for determining together the number of bit errors in each of (x), j = 0, 1, 2, ..., N-1; (c) n error trial word R ^(j) (x), j = 0, 1,
Means for comparing the respective bit error numbers of 2, ..., N-1 with the bit error number of the received word R (x); (d) received according to the comparison performed by the bit error number comparing means. A decoder for correcting errors in the word received during transmission, comprising means for correcting bit errors in the word R (x). 3. The bit error number determining means comprises an array of n + 1 identical bit error number determining cells, each bit error number determining cell having: a) a syndrome generating means for generating a syndrome of an input word; and b) an input word. 3. The decoder according to claim 2, further comprising means for generating the decision vector according to the syndrome in accordance with the syndrome generated by the syndrome generating means.