JPH03110869A - Semiconductor device - Google Patents

Abstract

PURPOSE:To surely prevent a load from acting by a reverse voltage by a method wherein a second MOSFET is formed between a source and a channel region of a first MOSFET and, when the first MOSFET is turned off, the second MOSFET is also turned off. CONSTITUTION:A second MOSFET 32 is formed between a first diffusion layer 3 of a second conductivity type as a channel region of a first MOSFET 31 and a second diffusion layer 4 of a first conductivity type as a source. Since the second MOSFET 32 owns the channel region jointly with the first MOSFET 31, it coincides with an ON-OFF operation of the first MOSFET 31. Consequently, when the first MOSFET 31 is turned off. also the second MOSFET 32 is turned off. As a result, even when a reverse voltage is applied by an external noise or the like when the first MOSFET 31 is turned off, it is possible to restrain an electric current from flowing between the source and a drain. Thereby, it is possible to surely prevent an electric load from acting on the first MOSFET at an OFF operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having a power MO3FET structure suitable as an element for controlling an on-vehicle load or the like.

(Prior Art) As a conventional semiconductor device of this type, there is one shown in FIG. 3, for example. Figure (a) shows a vertical DMO8FET.
FIG.

In the figure, N-type semiconductor substrates 1 and 2 as drains are shown.
A gate electrode G is provided thereon via a gate oxide film 11, and a P-type diffusion layer 3, which is a channel region, is formed in the substrate 2. In this P type diffusion layer 3, an N0 type diffusion layer 4 which is a source and a P medium type diffusion layer 5 which is a channel contact region are formed adjacent to each other. 3 and the N0 type diffusion layer 4 are short-circuited, and the channel voltage and source voltage are fixed to each other. Furthermore, a source electrode S insulated from the gate electrode G via an intermediate insulating film 14 is provided at this point.

The equivalent circuit diagram of a MOSFET with such a configuration is as follows:
Generally, it is expressed as shown in FIG. 3(b), but more precisely, it is expressed as shown in FIG. 3(C).

That is, a parasitic diode 21 is formed between the N-type diffusion layer 4 and the P-type diffusion layer 3, and a parasitic diode 22 is formed between the P-type diffusion layer 3 and the N- type semiconductor substrate 2 of the epitaxial layer. is formed. Of these, the former diode 2
1 is shorted, but the latter diode 22 is a MOS
It has a structure in which the source and drain of the FET are connected in parallel.

(Problem to be Solved by the Invention) However, in a semiconductor device having a -42 power MO8FET, the parasitic diode 22 is
Since the structure is such that the source voltage is higher than the drain voltage due to incorrect connection or external noise, the gate is switched from on to off. However, since current flows from the source to the drain through the parasitic diode 22, there is a problem that the load operates.

The present invention has been made in view of these conventional problems, and its purpose is to provide a semiconductor device that can prevent the load from operating even if the source voltage becomes high when the gate is turned off.

(Means for Solving the Problems) In order to achieve the above objects, the present invention includes a semiconductor substrate of a first conductivity type, which is a drain provided with a first gate electrode; A first MOSFET including a first diffusion layer of a second conductivity type, which is a channel region formed therein, and a second diffusion layer of a first conductivity type, which is a source formed in this diffusion layer, A third diffusion layer of the first conductivity type and a fourth diffusion layer of the second conductivity type are formed adjacent to each other in the first diffusion layer, and the second diffusion layer and the third diffusion layer are formed adjacent to each other. A second gate electrode is formed between the third diffusion layer and the fourth diffusion layer, and the third diffusion layer and the fourth diffusion layer are connected by a metal electrode, so that the first diffusion layer is a channel and the second diffusion layer is a channel. drain, third diffusion layer as source,
a second M in which the fourth diffusion layer is a channel contact region;
The present invention is characterized in that an OSFET is formed between the source and channel region of the first MOSFET.

(Function) According to the above configuration, the first diffusion layer of the second conductivity type, which is the channel region of the first MOSFET, and the second diffusion layer of the first conductivity type, which is the source, are provided. 2 MOSFET
is formed, and this second MOSFET is connected to the first MOSFET.
In order to share the channel area with the ET, the first MOSFE
This corresponds to the on/off operation of T. Therefore, the first MOSF
When the ET is off, the second MOSFET is also off, so even if the source voltage becomes higher than the drain voltage due to external noise etc. and a reverse voltage is applied when the first MOSFET is off, the source This can prevent current from flowing between the drain and the drain.

Thereby, it is possible to reliably prevent an electrical load from acting on the first MOSFET during off-operation.

(Example) The present invention will be explained below based on the drawings.

FIG. 1(a) is a sectional view showing an embodiment of the present invention. This embodiment is applied to a MOSFET that controls an on-vehicle load. Note that the same members as in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

First, to explain the structure, as shown in the figure, an N0 type diffusion layer 6 is formed in the P type diffusion layer 3 which is a channel region, and a second type diffusion layer 6 is formed between this and the N0 type diffusion layer 4. Gate electrode G
2 is formed, and as a result, the first
A second vertical MO8FET 32 is formed between the source and channel region of the MO3FET 31. That is, in the structure of the second MO8FET 32, the N0 type diffusion layer 4 serves as a drain, the N0 type diffusion layer 6 serves as a source, the P0 type diffusion layer 5 serves as a channel contact region, and the N+ type diffused layer 6 serves as a channel contact region. A source (metal) electrode S2 is provided. Therefore, the N-type diffusion layer 4, which is the source of the first MO3FET 31, is substantially separated from the P-type diffusion layer 3 in the channel region, and connects to the P-type diffusion layer 3 in the channel region via the second MO8FET 32. It is connected. In this example, the second M
The gate electrode G2 of O8FET32 is the first MO8FE
It is connected to the gate electrode G1 of T31, and therefore the first
, 2 MO3FETs 31 and 32 are both turned on and off at the same time.

This semiconductor device consisting of the following two configurations is shown in FIG. 1(b).
As shown in FIG.
31.32 functions as a channel region.

Next, the operation of this embodiment will be explained.

In the case of this embodiment, a positive gate voltage is applied and the first M
When the O8FET 31 is turned on, the second MO8FET 32 is also turned on as described above. At this time, the channel potential in the P-type diffusion layer 3 is
Since it is fixed at the source potential of the first MO8FET 31 at , it operates in the same way as a normal MOSFET.

Then, the voltage between the gate and source is set to 0, and the first MO8
When the FET 31 is turned off, the second MO8FET 32 is also turned off at the same time. In this way, in this embodiment, the second
The MO8FET 32 operates on and off in the same way as the first MO8FET 31, and the parasitic diodes 21 and 22 are connected in series in opposite directions between the source and drain of the first MO8FET 31 to form an equivalent circuit, so that the drain-source voltage The flow of current can be blocked regardless of whether it is positive or negative.

Therefore, even if the source voltage becomes higher than the drain voltage,
Since no current flows through the parasitic diode 22, the load does not operate. For example, if the on-vehicle load is controlled by this MO8FET element structure, even if the positive and negative terminals of the MOSFET are connected reversely to the positive and negative terminals of the battery, the on-vehicle load can be reliably prevented from operating.

In this embodiment, when the first MO8FET 31 is in the off state, the P type diffusion layer 3 in the channel region is
From the natural diffusion layer 4 to the drain region N- type semiconductor substrate 2
It is also in an electrically unstable state. Therefore, when a large voltage that exceeds the withstand voltage of the parasitic diode 22 or a pulse voltage that rises extremely quickly is applied between the drain and source, current flows through the parasitic diode 22 and the device is destroyed due to secondary breakdown. There are concerns.

゛Another example for improving this is shown in Figure 2 (
As shown in a), the gate electrode G of the second MOSFET
2 may be connected not to the gate electrode G1 of the first MOSFET but to the N'''' type semiconductor substrate 2 which is the drain region via the aluminum electrode 17 and the N0 type diffusion layer 7 which will be the drain contact region. In this way, the first M
As long as the drain-source voltage of the O3FET 31 is positive, the P-type diffusion layer 3 in the channel region is connected to the N+ type scattering layer 4 in the source region, so the parasitic diode 22 operates against fluctuations in the drain voltage. This eliminates the problem of element destruction caused by this.

In this way, even when the first MO3FET 31 is off, as long as the drain-source voltage is positive, the channel potential is fixed at the source potential, which effectively prevents element breakdown due to pulse voltage applied to the drain electrode. can be prevented.

In this example, if the drain-source voltage is positive regardless of whether the first MO3FET 31 is on or off, the second MO3FET31
Since O8FET32 is on and off when negative,
It goes without saying that the current blocking ability can be exhibited against the reverse voltage between the drain and the source as in the above embodiment.

(Effects of the Invention) As described above, according to the present invention, the second MOSFET is formed between the source and channel region of the first MOSFET, and when the first MOSFET is off, the second MOSFET is Since the configuration is such that the second MOSFET is also turned off, the first
Even if a reverse voltage is applied between the drain and source due to incorrect connection or external noise when the MOSFET is off, current can be prevented from flowing between the drain and source, and the load will therefore not operate due to the reverse voltage. This has the effect of being able to reliably prevent this from happening.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a sectional view, an equivalent circuit diagram, and a second embodiment of a semiconductor device according to the present invention, respectively.
3(a) and 3(b) are a sectional view and an equivalent circuit diagram respectively showing other embodiments of the semiconductor device according to the present invention, and FIG. 3(a) is a sectional view showing a conventional semiconductor device, and FIG. ),
(c) is an equivalent circuit diagram of the same semiconductor device. 1... N-type semiconductor substrate 2... N- type semiconductor substrate (drain of first MOSFET) 3... P-type diffusion layer (channel region of first and second MOSFET) 4... N0 type diffusion layer (first MOSFET source,
(drain of second MOSFET) 5...P-type diffusion layer (channel contact region of first and second MOSFET) 6...N+ type diffusion layer (source region of second MOSFET) 7...・N0 type diffusion layer (drain contact region) C7
+G + +G2...Gate electrode S, S4. S2
...Source (metal) electrode D...Drain electrode

Claims (1)

[Claims] 1. A first drain which is a drain provided with a first gate electrode.
A semiconductor substrate of a conductivity type, a first diffusion layer of a second conductivity type which is a channel region formed on this substrate, and a second diffusion layer of a first conductivity type which is a source formed in this diffusion layer. a third diffusion layer of a first conductivity type and a fourth diffusion layer of a second conductivity type are formed adjacent to each other in the first diffusion layer; , a second gate electrode is formed between the second diffusion layer and the third diffusion layer, the third diffusion layer and the fourth diffusion layer are connected by a metal electrode, and the first A second MOSFET in which the diffusion layer is a channel, the second diffusion layer is a drain, the third diffusion layer is a source, and the fourth diffusion layer is a channel contact region;
1. A semiconductor device formed between a source and a channel region of a MOSFET.