JP3146650B2 - Power integrated circuit - Google Patents
Power integrated circuitInfo
- Publication number
- JP3146650B2 JP3146650B2 JP18717292A JP18717292A JP3146650B2 JP 3146650 B2 JP3146650 B2 JP 3146650B2 JP 18717292 A JP18717292 A JP 18717292A JP 18717292 A JP18717292 A JP 18717292A JP 3146650 B2 JP3146650 B2 JP 3146650B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- switching element
- zener diode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電力用半導体素子とそ
の両端に加わる過電圧サージ吸収回路を同一半導体素体
に一体に集積したパワー集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power integrated circuit in which a power semiconductor element and an overvoltage surge absorbing circuit applied to both ends of the power semiconductor element are integrated into the same semiconductor body.
【０００２】[0002]
【従来の技術】ソレノイド等の誘導性負荷を有する回路
で電流をスイッチングオフしたとき、電力用半導体素子
の両端に過電圧サージが加わり、半導体素子が破壊する
ことがある。このような破壊を防止するために、スイッ
チング用半導体素子の耐圧よりも低い降伏電圧を有する
ツエナダイオードを用いることにより過電圧サージを吸
収することが行われており、図３はそのような回路を示
す。すなわち、電力用スイッチング素子としてのパワー
ＭＯＳＦＥＴ11は、ソース端子が接地され、ドレイン端
子と電源13の間に誘導性負荷12が接続される。ＭＯＳＦ
ＥＴ11のゲートには、小電源14により給電される駆動回
路15が、ドレイン端子との間にツエナダイオード16が、
またソース端子との間には抵抗17およびそれと並列にゲ
ートへの過電圧吸収用のツエナダイオード18がそれぞれ
接続されている。図４はこの回路のスイッチング波形の
タイムチャートを示す。波形21はパワーＭＯＳＦＥＴ11
のゲート電圧、波形22、23はＭＯＳＦＥＴ11のドレイン
電位で波形23はツエナダイオード16を接続しない場合で
ある。素子11がオフの時に電源13によって印加される電
圧ＶO は、波形21に示すようにゲート電圧を小電源14か
ら駆動回路15を介して印加することにより順電圧まで低
下する。そしてまた、ゲート電圧を０に戻すことによっ
て行われるターンオフの際に、誘導性負荷12に蓄積され
たエネルギーにより急上昇する。ツエナダイオード16が
接続された場合には、ツエナダイオード16のツエナ電圧
とＭＯＳＦＥＴ11のしきい値電圧との和Ｖ1 を超える電
圧は吸収され、22のような波形を示すがツエナダイオー
ド16の接続されない場合は23のように高いサージ電圧Ｖ
2 が発生する。2. Description of the Related Art When a current is switched off in a circuit having an inductive load such as a solenoid, an overvoltage surge is applied to both ends of a power semiconductor element, and the semiconductor element may be destroyed. In order to prevent such destruction, the overvoltage surge is absorbed by using a zener diode having a breakdown voltage lower than the breakdown voltage of the switching semiconductor element. FIG. 3 shows such a circuit. . That is, the source terminal of the power MOSFET 11 as the power switching element is grounded, and the inductive load 12 is connected between the drain terminal and the power supply 13. MOSF
A drive circuit 15 powered by a small power supply 14 has a gate of the ET 11 and a zener diode 16 between the gate and the drain terminal.
A resistor 17 and a Zener diode 18 for absorbing an overvoltage to the gate are connected between the resistor 17 and the source terminal. FIG. 4 shows a time chart of the switching waveform of this circuit. Waveform 21 is power MOSFET11
The waveforms 22 and 23 are the drain potential of the MOSFET 11 and the waveform 23 is the case where the Zener diode 16 is not connected. The voltage V O applied by the power supply 13 when the element 11 is off is reduced to a forward voltage by applying a gate voltage from the small power supply 14 via the drive circuit 15 as shown in a waveform 21 . Also , at the time of turn-off performed by returning the gate voltage to 0, the voltage rises sharply due to the energy stored in the inductive load 12. Tsu when Ena diode 16 is connected, the voltage exceeding the sum V 1 of the threshold voltage of the Zener voltage and the MOSFET11 of the Zener diode 16 is absorbed, but shows a waveform such as 22 are not connected to the Zener diode 16 High surge voltage V like 23
2 occurs.
【０００３】このような保護作用を行うツエナダイオー
ドはｎ形の半導体基板にｐ形の領域を形成してその間の
ＰＮ接合を利用することにより形成することができる。
そしてそのツエナダイオードとＭＯＳＦＥＴ11のゲート
およびドレインとを接続する配線が半導体基板上に絶縁
して設けられる。A Zener diode having such a protective function can be formed by forming a p-type region on an n-type semiconductor substrate and using a PN junction therebetween.
A wiring connecting the Zener diode to the gate and drain of MOSFET 11 is provided on the semiconductor substrate in an insulated manner.
【０００４】[0004]
【発明が解決しようとする課題】しかし、そのようなツ
エナダイオードのためのｐ形領域とスイッチング素子の
ｐ形領域がそれぞれソース、ドレインとして働く寄生Ｍ
ＯＳＦＥＴが生じたり、ｐｎｐｎ構造の寄生サイリスタ
が構成されたり、また各部の導電形が逆の場合はｎチャ
ネルＭＯＳＦＥＴが生じたりする。両領域の間の表面に
形成される絶縁膜上の配線あるいはゲート電極の延長部
の電位変動があると、そのようなｐチャネルＭＯＳＦＥ
ＴあるいはｎチャネルＭＯＳＦＥＴが動作したり、寄生
サイリスタのターンオンによるラッチアップ動作を起こ
したりするので、回路全体として不都合が生じる場合が
ある。However, the p-type region for such a zener diode and the p-type region of the switching element serve as a source and a drain, respectively.
An OSFET occurs, a parasitic thyristor having a pnpn structure is formed, and an n-channel MOSFET occurs when the conductivity type of each part is reversed. If there is a potential change in the wiring on the insulating film formed on the surface between the two regions or the extension of the gate electrode, such a p-channel MOSFE
Since the T or n-channel MOSFET operates or a latch-up operation occurs due to the turning on of the parasitic thyristor, inconvenience may occur in the entire circuit.
【０００５】本発明の目的は、上述の問題を解決し、寄
生素子の動作するのを防止したパワー集積回路を提供す
ることにある。An object of the present invention is to provide a power integrated circuit which solves the above-mentioned problems and prevents the operation of a parasitic element.
【０００６】[0006]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は、第一導電形の半導体層の表面層に形成さ
れた第二導電形の第一領域を少なくとも有するスイッチ
ング素子への過電圧印加防止用のツエナダイオードが前
記半導体層の表面層に形成された第二導電形の第二領域
を用いてなるものにおいて、スイッチング素子の第二導
電形の第一領域とツエナダイオードの第二導電形の第二
領域の間の半導体層の表面上に、絶縁膜のみが存在し、
スイッチング素子の電極に接続され電位変動のある金属
導体が存在しないものとする。そして、ツエナダイオー
ドの第二導電形の第二領域に接触する電極と、スイッチ
ング素子の電極とを接続する金属配線がスイッチング素
子の第二導電形の第一領域の表面を迂回して設けられた
ことが有効である。また、スイッチング素子がその第二
導電形の第一領域上に絶縁膜を介して設けられたゲート
電極を有し、ツエナダイオードの第二導電形の第二領域
に接触する電極とそのゲート電極とを接続する金属配線
が、スイッチング素子の第二導電形の第一領域とツエナ
ダイオードの第二導電形の第二領域の間の半導体層の表
面上を経由しないことが有効である。Means for Solving the Problems] To achieve the above object, the present invention is to at least have a switching element a first region of a second conductivity type formed on the semiconductor layer surface layer of the first the one conductivity type A Zener diode for preventing overvoltage application using a second region of the second conductivity type formed on the surface layer of the semiconductor layer, wherein the first region of the second conductivity type of the switching element and the second region of the Zener diode On the surface of the semiconductor layer between the second regions of the conductivity type, there is only an insulating film,
Is connected to the electrode of the switching element shall not exist metal <br/> conductor with potential variation. An electrode in contact with the second region of the second conductivity type of the Zener diode and a metal wiring connecting the electrode of the switching element are provided to bypass the surface of the first region of the second conductivity type of the switching element. It is effective. In addition, the switching element has a gate electrode provided on the first region of the second conductivity type via an insulating film, and an electrode that contacts the second region of the second conductivity type of the Zener diode and the gate electrode. metal wires connecting it, it is effective to not go through the upper surface of the semiconductor layer between the second region of the second conductivity type first region and the Zener diode of the second conductivity type of the switching element.
【０００７】[0007]
【作用】スイッチング素子とツエナダイオードの間の半
導体層の上にスイッチング素子の主電極あるいはゲート
電極に接続される金属配線などの導体が存在しないた
め、半導体層の表面層にチャネルを形成するような作用
を生ずる電位変動がその表面上に起こらないので、寄生
のＭＯＳＦＥＴ構造が生ぜず、また寄生サイリスタ構造
が動作することもない。Since there is no conductor such as a metal wiring connected to the main electrode or the gate electrode of the switching element on the semiconductor layer between the switching element and the Zener diode, a channel is formed in the surface layer of the semiconductor layer. No parasitic potential MOSFET structure occurs and no parasitic thyristor structure operates because no potential fluctuations occur on its surface that cause an effect.
【０００８】[0008]
【実施例】図１は本発明の一実施例のパワー集積回路を
示し、図３の回路のパワーＭＯＳＦＥＴ11は図の右側
に、ツエナダイオード16は図の左側に形成されている。
すなわち、一側にｎ+ 層２を有するｎ- 層１の表面層に
ｐ- 領域３が形成され、さらにそのｐ- 領域３の表面層
にｎ+ ソース領域４が形成されている。また、ｐ- 領域
３の中央部にｐ+ ウエル51が重ねられる。そして、ｐ-
領域３のｎ- 層１の露出部およびｎ+ ソース領域４には
さまれた部分にチャネルを形成するため、ゲート酸化膜
６を介してゲート電極７が設けられ、そのゲート電極７
と層間絶縁膜８で絶縁されるソース電極91はソース領域
４およびｐ+ ウエル51に共通に接触し、ｎ+ 層２にドレ
イン電極92が接触することによりたて型のパワーＭＯＳ
ＦＥＴが構成される。一方ツエナダイオード16は、ｎ+
層２、ｎ- 層１およびその表面層にｐ+ ウエル51と同じ
拡散工程で形成されるｐ+ ウエル52から構成されてい
る。このツエナダイオードのカソード領域（ｎ + 層２）
にパワーＭＯＳＦＥＴ11のドレイン電極92が接触し、ア
ノード領域（ｐ + ウエル52）にAlからなる配線（電極）
10が接触してこれがＭＯＳＦＥＴ11のゲート電極７と接
続されることにより、図３に示すようにドレイン・ゲー
ト間ツエナダイオード16の接続ができる。その配線は、
図２の平面図に示すように、パワーＭＯＳＦＥＴ11のソ
ース電極91の外側を迂回する配線（Al層）20により形成
される。従ってこの配線20は、ＭＯＳＦＥＴ11のｐ- 領
域３あるいはｐ+ ウエル51とツエナダイオード16のｐ+
ウエル52との間の半導体層１の表面上には存在しない。
またゲート電極７の延長部もこの区域には存在しない。
従ってｐ+ ウエル52とｐ+ ウエル51あるいはｐ- 領域３
との間にチャネルが形成されることがなく、寄生ＭＯＳ
ＦＥＴが生じない。なお、図１、図２にはパワーＭＯＳ
ＦＥＴ11とツエナダイオード16の集積部分のみを示した
が、同一半導体素子に制御回路、駆動回路を集積するこ
とができる。FIG. 1 shows a power integrated circuit according to an embodiment of the present invention. In the circuit of FIG. 3, a power MOSFET 11 is formed on the right side of the figure, and a zener diode 16 is formed on the left side of the figure.
That is, the p − region 3 is formed in the surface layer of the n − layer 1 having the n + layer 2 on one side, and the n + source region 4 is formed in the surface layer of the p − region 3. Further, ap + well 51 is superimposed on the center of the p − region 3. Then, p -
A gate electrode 7 is provided via a gate oxide film 6 in order to form a channel in the region 3 between the exposed portion of the n − layer 1 and the n + source region 4.
A source electrode 91 insulated by the interlayer insulating film 8 and the source region 4 and the p + well 51 are in common contact, and the drain electrode 92 is in contact with the n + layer 2 to form a vertical power MOS.
An FET is configured. On the other hand, the Zener diode 16 has n +
It is composed of the layer 2, the n − layer 1 and a p + well 52 formed on the surface layer thereof in the same diffusion step as the p + well 51. The cathode region of this Zener diode (n + layer 2)
Contact with the drain electrode 92 of the power MOSFET 11 and the wiring (electrode) made of Al in the anode region (p + well 52 )
The contact between the drain electrode 10 and the gate electrode 7 of the MOSFET 11 allows the connection of the drain-gate zener diode 16 as shown in FIG. The wiring is
As shown in the plan view of FIG. 2, the power MOSFET 11 is formed by a wiring (Al layer) 20 which bypasses the outside of the source electrode 91. Therefore, the wiring 20 is connected to the p − region 3 or the p + well 51 of the MOSFET 11 and the p +
It does not exist on the surface of semiconductor layer 1 between well 52.
Also, the extension of the gate electrode 7 does not exist in this area.
Therefore, p + well 52 and p + well 51 or p − region 3
No channel is formed between the
No FET occurs. 1 and 2 show the power MOS.
Although only the integrated portion of the FET 11 and the Zener diode 16 is shown, a control circuit and a drive circuit can be integrated on the same semiconductor element.
【０００９】[0009]
【発明の効果】本発明によれば、電力用スイッチング素
子とそれと同一半導体素体に集積されるツエナダイオー
ドとの同一導電形領域間の高抵抗半導体層上に絶縁膜の
みが存在し、電位変動のある金属導体が存在しないよう
にすることにより、寄生ＭＯＳＦＥＴが形成されず、寄
生サイリスタも動作しないため、支障なく過電圧保護動
作が行われるパワー集積回路が得られた。According to the present invention, only the insulating film is present on the high-resistance semiconductor layer between the power switching element and the same conductivity type region of the Zener diode integrated with the same semiconductor element, and the potential fluctuation occurs. By avoiding the presence of a metal conductor having no, no parasitic MOSFET is formed and the parasitic thyristor does not operate, so that a power integrated circuit capable of performing the overvoltage protection operation without any trouble is obtained.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一実施例のパワー集積回路の図２のＡ
−Ａ線断面図FIG. 1A shows a power integrated circuit according to an embodiment of the present invention; FIG.
-A line sectional view
【図２】図１のパワー集積回路の一部の平面図FIG. 2 is a plan view of a part of the power integrated circuit of FIG. 1;
【図３】図１、図２に示したパワー集積回路の回路図FIG. 3 is a circuit diagram of the power integrated circuit shown in FIGS. 1 and 2;
【図４】図３のパワー集積回路およびそのツエナダイオ
ードが接続されない場合のターンオン、ターンオフ時の
ゲート電圧およびドレイン電位の波形図FIG. 4 is a waveform diagram of gate voltage and drain potential at turn-on and turn-off when the power integrated circuit of FIG. 3 and its Zener diode are not connected.
１ ｎ- 層 ２ ｎ+ 層 ３ ｐ- 領域 ４ ｎ+ ソース領域 ５１ ｐ+ ウエル ５２ ｐ+ ウエル ６ ゲート酸化膜 ７ ゲート電極 ９１ ソース電極 ９２ ドレイン電極 １０ 配線 ２０ 配線 １１ パワーＭＯＳＦＥＴ １２ ツエナダイオードReference Signs List 1 n − layer 2 n + layer 3 p − region 4 n + source region 51 p + well 52 p + well 6 gate oxide film 7 gate electrode 91 source electrode 92 drain electrode 10 wiring 20 wiring 11 power MOSFET 12 zener diode
Claims (3)
た第二導電形の第一領域を少なくとも有するスイッチン
グ素子への過電圧印加防止用のツエナダイオードが前記
半導体層の表面層に形成された第二導電形の第二領域を
用いてなるものにおいて、スイッチング素子の第二導電
形の第一領域とツエナダイオードの第二導電形の第二領
域の間の半導体層の表面上に、絶縁膜のみが存在し、ス
イッチング素子の電極に接続され電位変動のある金属導
体が存在しないことを特徴とするパワー集積回路。1. A formed on the surface layer Zener diode of the semiconductor layer for overvoltage prevention to the switching element having at least a first region of a second conductivity type formed in the surface layer of the semiconductor layer of the first the one conductivity type in those obtained by using the second region of the second conductivity type which is the semiconductor layer between the second territory <br/> region of the second conductivity type first region and the Zener diode of the second conductivity type switching element on the surface, only the insulating film is present, power integrated circuits metal conductive <br/> body is connected to the electrode of the switching element with a potential variation is characterized and go not exist.
に接触する電極と、スイッチング素子の電極とを接続す
る金属配線がスイッチング素子の第二導電形の第一領域
の表面を迂回して設けられた請求項１記載のパワー集積
回路。2. A metal wiring connecting an electrode in contact with the second region of the second conductivity type of the Zener diode and an electrode of the switching element bypasses the surface of the first region of the second conductivity type of the switching element. The power integrated circuit according to claim 1 provided.
領域上に絶縁膜を介して設けられたゲート電極を有し、
ツエナダイオードの第二導電形の第二領域に接触する電
極とそのゲート電極とを接続する金属配線が、スイッチ
ング素子の第二導電形の第一領域とツエナダイオードの
第二導電形の第二領域の間の半導体層の表面上を経由し
ない請求項１あるいは２記載のパワー集積回路。3. The switching element has a gate electrode provided on the first region of the second conductivity type via an insulating film.
Tsu metal wiring that connects the electrode in contact with the second region of the second conductivity type Energizing diode and its gate electrode, a second region of a second conductivity type first region and the Zener diode of the second conductivity type switching element The power integrated circuit according to claim 1, wherein the power integrated circuit does not pass through the surface of the semiconductor layer between the power integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18717292A JP3146650B2 (en) | 1992-07-15 | 1992-07-15 | Power integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18717292A JP3146650B2 (en) | 1992-07-15 | 1992-07-15 | Power integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637320A JPH0637320A (en) | 1994-02-10 |
| JP3146650B2 true JP3146650B2 (en) | 2001-03-19 |
Family
ID=16201373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18717292A Expired - Lifetime JP3146650B2 (en) | 1992-07-15 | 1992-07-15 | Power integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3146650B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252477A (en) * | 1999-03-02 | 2000-09-14 | Fuji Electric Co Ltd | Semiconductor device |
| WO2016170706A1 (en) | 2015-04-22 | 2016-10-27 | 三菱電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
-
1992
- 1992-07-15 JP JP18717292A patent/JP3146650B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0637320A (en) | 1994-02-10 |
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