JPH0637320A - Power integrated circuit - Google Patents
Power integrated circuitInfo
- Publication number
- JPH0637320A JPH0637320A JP18717292A JP18717292A JPH0637320A JP H0637320 A JPH0637320 A JP H0637320A JP 18717292 A JP18717292 A JP 18717292A JP 18717292 A JP18717292 A JP 18717292A JP H0637320 A JPH0637320 A JP H0637320A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- region
- conductivity type
- mosfet
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電力用半導体素子とそ
の両端に加わる過電圧サージ吸収回路を同一半導体素体
に一体に集積したパワー集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power integrated circuit in which a power semiconductor element and an overvoltage surge absorbing circuit applied to both ends of the power semiconductor element are integrated in the same semiconductor element.
【０００２】[0002]
【従来の技術】ソレノイド等の誘導性負荷を有する回路
で電流をスイッチングオフしたとき、電力用半導体素子
の両端に過電圧サージが加わり、半導体素子が破壊する
ことがある。このような破壊を防止するために、スイッ
チング用半導体素子の耐圧よりも低い降伏電圧を有する
ツエナダイオードを用いることにより過電圧サージを吸
収することが行われており、図３はそのような回路を示
す。すなわち、電力用スイッチング素子としてのパワー
ＭＯＳＦＥＴ11は、ソース端子が接地され、ドレイン端
子と電源13の間に誘導性負荷12が接続される。ＭＯＳＦ
ＥＴ11のゲートには、小電源14により給電される駆動回
路15が、ドレイン端子との間にツエナダイオード16が、
またソース端子との間には抵抗17およびそれと並列にゲ
ートへの過電圧吸収用のツエナダイオード18がそれぞれ
接続されている。図４はこの回路のスイッチング波形の
タイムチャートを示す。波形21はパワーＭＯＳＦＥＴ11
のゲート電圧、波形22、23はＭＯＳＦＥＴ11のドレイン
電位で波形23はツエナダイオード16を接続しない場合で
ある。素子11がオフの時に電源13によって印加される電
圧Ｖ0 は、波形21に示すようにゲート電圧を小電源14か
ら駆動回路15を介して印加することにより順電圧まで低
下するか、ゲート電圧を０に戻すことによって行われる
ターンオフの際に、誘導性負荷12に蓄積されたエネルギ
ーにより急上昇する。ツエナダイオード16が接続された
場合には、ツエナダイオード16のツエナ電圧とＭＯＳＦ
ＥＴ11のしきい値電圧との和Ｖ1 を超える電圧は吸収さ
れ、22のような波形を示すがツエナダイオード16の接続
されない場合は23のように高いサージ電圧Ｖ2 が発生す
る。2. Description of the Related Art When current is switched off in a circuit having an inductive load such as a solenoid, an overvoltage surge is applied to both ends of a power semiconductor element, which may damage the semiconductor element. In order to prevent such a breakdown, a zener diode having a breakdown voltage lower than the breakdown voltage of the switching semiconductor element is used to absorb an overvoltage surge, and FIG. 3 shows such a circuit. . That is, in the power MOSFET 11 as a power switching element, the source terminal is grounded, and the inductive load 12 is connected between the drain terminal and the power supply 13. MOSF
A driving circuit 15 fed by a small power supply 14 is connected to the gate of ET11, and a zener diode 16 is connected between the gate and the drain terminal.
A resistor 17 and a zener diode 18 for absorbing an overvoltage to the gate are connected in parallel with the source terminal. FIG. 4 shows a time chart of switching waveforms of this circuit. Waveform 21 is power MOSFET 11
, The waveforms 22 and 23 are the drain potential of the MOSFET 11, and the waveform 23 is the case where the Zener diode 16 is not connected. The voltage V 0 applied by the power supply 13 when the element 11 is off is lowered to the forward voltage by applying the gate voltage from the small power supply 14 through the drive circuit 15 as shown by the waveform 21, or the gate voltage is changed. During the turn-off performed by returning to 0, the energy stored in the inductive load 12 causes the surge. When the Zener diode 16 is connected, the Zener voltage of the Zener diode 16 and the MOSF
A voltage exceeding the sum V 1 of the threshold voltage of ET 11 is absorbed, and a surge voltage V 2 having a waveform like 22 is generated but a surge voltage V 2 as high as 23 is generated when the zener diode 16 is not connected.
【０００３】このような保護作用を行うツエナダイオー
ドはｎ形の半導体基板にｐ形の領域を形成してその間の
ＰＮ接合を利用することにより形成することができる。
そしてそのツエナダイオードとＭＯＳＦＥＴ11のゲート
およびドレインとを接続する配線が半導体基板上に絶縁
して設けられる。A Zener diode which performs such a protection action can be formed by forming a p-type region on an n-type semiconductor substrate and utilizing a PN junction therebetween.
Then, a wiring connecting the Zener diode and the gate and drain of MOSFET 11 is provided on the semiconductor substrate in an insulated manner.
【０００４】[0004]
【発明が解決しようとする課題】しかし、そのようなツ
エナダイオードのためのｐ形領域とスイッチング素子の
ｐ形領域がそれぞれソース、ドレインとして働く寄生Ｍ
ＯＳＦＥＴが生じたり、ｐｎｐｎ構造の寄生サイリスタ
が構成されたり、また各部の導電形が逆の場合はｎチャ
ネルＭＯＳＦＥＴが生じたりする。両領域の間の表面に
形成される絶縁膜上の配線あるいはゲート電極の延長部
の電位変動があると、そのようなｐチャネルＭＯＳＦＥ
ＴあるいはｎチャネルＭＯＳＦＥＴが動作したり、寄生
サイリスタのターンオンによるラッチアップ動作を起こ
したりするので、回路全体として不都合が生じる場合が
ある。However, the p-type region for such a Zener diode and the p-type region of the switching element serve as a source and a drain, respectively, which acts as a parasitic M.
An OSFET may be generated, a parasitic thyristor having a pnpn structure may be formed, or an n-channel MOSFET may be generated when the conductivity type of each part is opposite. If there is a potential change in the wiring on the insulating film formed on the surface between the both regions or the extension of the gate electrode, such p-channel MOSFE
Since the T or n channel MOSFET operates or the latch-up operation occurs due to the turn-on of the parasitic thyristor, inconvenience may occur in the entire circuit.
【０００５】本発明の目的は、上述の問題を解決し、寄
生素子の動作するのを防止したパワー集積回路を提供す
ることにある。An object of the present invention is to solve the above-mentioned problems and to provide a power integrated circuit in which parasitic elements are prevented from operating.
【０００６】[0006]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は、少なくとも第一導電形の半導体層の表面
層に形成された第二導電形の領域を有するスイッチング
素子への過電圧印加防止用のツエナダイオードが前記半
導体層とその表面層に形成された第二導電形の領域とよ
りなるパワー集積回路において、スイッチング素子の第
二導電形の領域とツエナダイオードの第二導電形の領域
の間の半導体層の表面上に絶縁膜のみが存在し、スイッ
チング素子の電極に接続される導体が存在しないものと
する。そして、ツエナダイオードの第二導電形の領域に
接触する電極と、スイッチング素子の電極とを接続する
配線がスイッチング素子の第二導電形の領域の表面を迂
回して設けられたことが有効である。また、スイッチン
グ素子がその第二導電形の領域上に絶縁膜を介して設け
られたゲート電極を有し、ツエナダイオードの第二導電
形の領域に接触する電極とそのゲート電極とを接続する
配線が、スイッチング素子の第二導電形の領域とツエナ
ダイオードの第二導電形の領域の間の半導体層の表面上
を経由しないことが有効である。In order to achieve the above object, the present invention provides an overvoltage application to a switching element having at least a region of a second conductivity type formed in a surface layer of a semiconductor layer of a first conductivity type. In a power integrated circuit in which a Zener diode for prevention is formed of the semiconductor layer and a region of the second conductivity type formed on the surface layer thereof, a region of the second conductivity type of the switching element and a region of the second conductivity type of the Zener diode. It is assumed that only the insulating film exists on the surface of the semiconductor layer between and the conductor connected to the electrode of the switching element does not exist. Then, it is effective that the wiring that connects the electrode contacting the second conductivity type region of the Zener diode and the electrode of the switching element is provided so as to bypass the surface of the second conductivity type region of the switching element. . Further, the switching element has a gate electrode provided on the region of the second conductivity type via an insulating film, and a wiring connecting the electrode contacting the region of the second conductivity type of the Zener diode and the gate electrode. However, it is effective not to pass on the surface of the semiconductor layer between the region of the second conductivity type of the switching element and the region of the second conductivity type of the Zener diode.
【０００７】[0007]
【作用】スイッチング素子とツエナダイオードの間の半
導体層の上にスイッチング素子の主電極あるいはゲート
電極に接続される配線などの導体が存在しないため、半
導体層の表面層にチャネルを形成するような作用を生ず
る電位変動がその表面上に起こらないので、寄生のＭＯ
ＳＦＥＴ構造が生ぜず、また寄生サイリスタ構造が動作
することもない。[Function] Since there is no conductor such as a wiring connected to the main electrode or the gate electrode of the switching element on the semiconductor layer between the switching element and the Zener diode, a function of forming a channel in the surface layer of the semiconductor layer is obtained. Since the potential fluctuation that causes the noise does not occur on the surface, the parasitic MO
The SFET structure does not occur, and the parasitic thyristor structure does not operate.
【０００８】[0008]
【実施例】図１は本発明の一実施例のパワー集積回路を
示し、図３の回路のパワーＭＯＳＦＥＴ11は図の右側
に、ツエナダイオード16は図の左側に形成されている。
すなわち、一側にｎ+ 層２を有するｎ- 層１の表面層に
ｐ- 領域３が形成され、さらにそのｐ- 領域３の表面層
にｎ+ ソース領域４が形成されている。また、ｐ- 領域
３の中央部にｐ+ ウエル51が重ねられる。そして、ｐ-
領域３のｎ- 層１の露出部およびｎ+ ソース領域４には
さまれた部分にチャネルを形成するため、ゲート酸化膜
６を介してゲート電極７が設けられ、そのゲート電極７
と層間絶縁膜８で絶縁されるソース電極91はソース領域
４およびｐ+ ウエル51に共通に接触し、ｎ+ 層２にドレ
イン電極92が接触することによりたて型のパワーＭＯＳ
ＦＥＴが構成される。一方ツエナダイオード16は、ｎ+
層２、ｎ- 層１およびその表面層にｐ+ ウエル51と同じ
拡散工程で形成されるｐ+ ウエル52から構成されてい
る。このツエナダイオードのカソード領域２にパワーＭ
ＯＳＦＥＴ11のドレイン電極92が接触し、アノード領域
52にAlからなる電極10が接触してこれがＭＯＳＦＥＴ11
のゲート電極７と接続されることにより、図３に示すよ
うにドレイン・ゲート間ツエナダイオード16の接続がで
きる。その配線は、図２の平面図に示すように、パワー
ＭＯＳＦＥＴ11のソース電極91の外側を迂回するAl層20
により形成される。従ってこの配線20は、ＭＯＳＦＥＴ
11のｐ- 領域３あるいはｐ+ ウエル51とツエナダイオー
ド16のｐ+ ウエル52との間の半導体層１の表面上には存
在しない。またゲート電極７の延長部もこの区域には存
在しない。従ってｐ+ ウエル52とｐ+ ウエル51あるいは
ｐ- 領域３との間にチャネルが形成されることがなく、
寄生ＭＯＳＦＥＴが生じない。なお、図１、図２にはパ
ワーＭＯＳＦＥＴ11とツエナダイオード16の集積部分の
みを示したが、同一半導体素子に制御回路、駆動回路を
集積することができる。1 shows a power integrated circuit according to an embodiment of the present invention, in which the power MOSFET 11 of the circuit of FIG. 3 is formed on the right side of the figure and the Zener diode 16 is formed on the left side of the figure.
Ie, n has an n + layer 2 on one side - region 3 is formed, the p further - - p in the surface layer of the layer 1 n + source region 4 in the surface layer of the region 3 is formed. Further, the p + well 51 is overlapped with the central portion of the p − region 3. Then, p -
In order to form a channel in the exposed portion of the n − layer 1 in the region 3 and the portion sandwiched between the n + source regions 4, a gate electrode 7 is provided via the gate oxide film 6, and the gate electrode 7 is provided.
The source electrode 91 insulated by the interlayer insulating film 8 and the source region 4 and the p + well 51 are in common contact with each other, and the drain electrode 92 is in contact with the n + layer 2 so that the vertical power MOS is formed.
The FET is configured. On the other hand, the Zener diode 16 has n +
The layer 2, the n − layer 1 and the p + well 52 formed in the surface layer thereof in the same diffusion step as the p + well 51. The power M is applied to the cathode region 2 of this Zener diode.
The drain electrode 92 of the OSFET 11 contacts and the anode region
The electrode 10 made of Al is in contact with 52 and this is MOSFET 11
By connecting the gate electrode 7 to the drain-gate zener diode 16 as shown in FIG. The wiring is, as shown in the plan view of FIG. 2, an Al layer 20 that bypasses the outside of the source electrode 91 of the power MOSFET 11.
Is formed by. Therefore, this wiring 20 is a MOSFET
It does not exist on the surface of the semiconductor layer 1 between the p − region 3 of 11 or the p + well 51 and the p + well 52 of the Zener diode 16. The extension of the gate electrode 7 does not exist in this area either. Therefore, no channel is formed between the p + well 52 and the p + well 51 or the p − region 3,
No parasitic MOSFET occurs. Although only the integrated portion of the power MOSFET 11 and the Zener diode 16 is shown in FIGS. 1 and 2, the control circuit and the drive circuit can be integrated in the same semiconductor element.
【０００９】[0009]
【発明の効果】本発明によれば、電力用スイッチング素
子とそれと同一半導体素体に集積されるツエナダイオー
ドとの同一導電形領域間の高抵抗半導体層上に絶縁膜の
みが存在し、電位変動のある導体が存在しないようにす
ることにより、寄生ＭＯＳＦＥＴが形成されず、寄生サ
イリスタも動作しないため、支障なく過電圧保護動作が
行われるパワー集積回路が得られた。According to the present invention, only the insulating film exists on the high resistance semiconductor layer between the regions of the same conductivity type of the power switching element and the Zener diode integrated in the same semiconductor element body, and the potential fluctuation occurs. Since the parasitic MOSFET is not formed and the parasitic thyristor does not operate by eliminating the presence of the conductor having the electric field, the power integrated circuit in which the overvoltage protection operation is performed without trouble is obtained.
【図１】本発明の一実施例のパワー集積回路の図２のＡ
−Ａ線断面図FIG. 1A of FIG. 2 of a power integrated circuit of one embodiment of the present invention.
-A line sectional view
【図２】図１のパワー集積回路の一部の平面図2 is a plan view of a portion of the power integrated circuit of FIG.
【図３】図１、図２に示したパワー集積回路の回路図FIG. 3 is a circuit diagram of the power integrated circuit shown in FIGS. 1 and 2.
【図４】図３のパワー集積回路およびそのツエナダイオ
ードが接続されない場合のターンオン、ターンオフ時の
ゲート電圧およびドレイン電位の波形図FIG. 4 is a waveform diagram of gate voltage and drain potential at turn-on and turn-off when the power integrated circuit of FIG. 3 and its Zener diode are not connected.
１ ｎ- 層 ２ ｎ+ 層 ３ ｐ- 領域 ４ ｎ+ ソース領域 ５１ ｐ+ ウエル ５２ ｐ+ ウエル ６ ゲート酸化膜 ７ ゲート電極 ９１ ソース電極 ９２ ドレイン電極 １０ 配線 ２０ 配線 １１ パワーＭＯＳＦＥＴ １２ ツエナダイオード1 n - layer 2 n + layer 3 p - region 4 n + source region 51 p + well 52 p + well 6 gate oxide film 7 gate electrode 91 source electrode 92 drain electrode 10 wiring 20 wiring 11 power MOSFET 12 zener diode
Claims (3)
に形成された第二導電形の領域を有するスイッチング素
子への過電圧印加防止用のツエナダイオードが前記半導
体層とその表面層に形成された第二導電形の領域とより
なるものにおいて、スイッチング素子の第二導電形の領
域とツエナダイオードの第二導電形の領域の間の半導体
層の表面上に絶縁膜のみが存在し、スイッチング素子の
電極に接続される導体が存在しないことを特徴とするパ
ワー集積回路。1. A Zener diode for preventing overvoltage application to a switching element having at least a region of a second conductivity type formed in a surface layer of a semiconductor layer of a first conductivity type is formed in the semiconductor layer and its surface layer. And a second conductivity type region, the insulating film exists only on the surface of the semiconductor layer between the second conductivity type region of the switching element and the second conductivity type region of the Zener diode, and the switching element A power integrated circuit, characterized in that there is no conductor connected to the electrodes of.
触する電極と、スイッチング素子の電極とを接続する配
線がスイッチング素子の第二導電形の領域の表面を迂回
して設けられた請求項１記載のパワー集積回路。2. A wiring for connecting an electrode in contact with a region of the second conductivity type of a Zener diode and an electrode of a switching element is provided bypassing a surface of the region of the second conductivity type of the switching element. 1. The power integrated circuit according to 1.
上に絶縁膜を介して設けられたゲート電極を有し、ツエ
ナダイオードの第二導電形の領域に接触する電極とその
ゲート電極とを接続する配線が、スイッチング素子の第
二導電形の領域とツエナダイオードの第二導電形の領域
の間の半導体層の表面上を経由しない請求項１あるいは
２記載のパワー集積回路。3. A switching element has a gate electrode provided on an area of the second conductivity type via an insulating film, and an electrode contacting the area of the second conductivity type of a Zener diode and the gate electrode thereof. 3. The power integrated circuit according to claim 1, wherein the connecting wiring does not pass through the surface of the semiconductor layer between the second conductivity type region of the switching element and the second conductivity type region of the Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18717292A JP3146650B2 (en) | 1992-07-15 | 1992-07-15 | Power integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18717292A JP3146650B2 (en) | 1992-07-15 | 1992-07-15 | Power integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637320A true JPH0637320A (en) | 1994-02-10 |
| JP3146650B2 JP3146650B2 (en) | 2001-03-19 |
Family
ID=16201373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18717292A Expired - Lifetime JP3146650B2 (en) | 1992-07-15 | 1992-07-15 | Power integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3146650B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6346740B1 (en) * | 1999-03-02 | 2002-02-12 | Fuji Electric Co., Ltd. | Semiconductor device |
| US10475920B2 (en) | 2015-04-22 | 2019-11-12 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor device manufacturing method |
-
1992
- 1992-07-15 JP JP18717292A patent/JP3146650B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6346740B1 (en) * | 1999-03-02 | 2002-02-12 | Fuji Electric Co., Ltd. | Semiconductor device |
| US10475920B2 (en) | 2015-04-22 | 2019-11-12 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3146650B2 (en) | 2001-03-19 |
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