JPH0279463A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JPH0279463A
JPH0279463A JP63230817A JP23081788A JPH0279463A JP H0279463 A JPH0279463 A JP H0279463A JP 63230817 A JP63230817 A JP 63230817A JP 23081788 A JP23081788 A JP 23081788A JP H0279463 A JPH0279463 A JP H0279463A
Authority
JP
Japan
Prior art keywords
wiring layer
bit line
point metal
melting point
high melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63230817A
Other languages
English (en)
Japanese (ja)
Inventor
Yoshiki Okumura
奥村　喜紀
Takayuki Matsukawa
隆行 松川
Ikuo Ogawa
育夫 小河
Masao Nagatomo
長友　正男
Hideki Genjiyou
源城　英毅
Atsushi Hachisuga
敦司 蜂須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63230817A priority Critical patent/JPH0279463A/ja
Priority to US07/404,528 priority patent/US5153689A/en
Priority to DE3930639A priority patent/DE3930639A1/de
Publication of JPH0279463A publication Critical patent/JPH0279463A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
JP63230817A 1988-09-14 1988-09-14 半導体記憶装置 Pending JPH0279463A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP63230817A JPH0279463A (ja) 1988-09-14 1988-09-14 半導体記憶装置
US07/404,528 US5153689A (en) 1988-09-14 1989-09-08 Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines
DE3930639A DE3930639A1 (de) 1988-09-14 1989-09-13 Halbleiterspeichervorrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63230817A JPH0279463A (ja) 1988-09-14 1988-09-14 半導体記憶装置

Publications (1)

Publication Number Publication Date
JPH0279463A true JPH0279463A (ja) 1990-03-20

Family

ID=16913743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63230817A Pending JPH0279463A (ja) 1988-09-14 1988-09-14 半導体記憶装置

Country Status (3)

Country Link
US (1) US5153689A (enExample)
JP (1) JPH0279463A (enExample)
DE (1) DE3930639A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192357A (ja) * 1990-07-23 1992-07-10 Matsushita Electron Corp 半導体記憶装置
US5302538A (en) * 1992-08-04 1994-04-12 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing field effect transistor
KR100230367B1 (ko) * 1996-08-19 1999-11-15 윤종용 반도체 디바이스의 제조방법

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600162A (en) * 1992-08-10 1997-02-04 Siemens Aktiengesellschaft DRAM-type memory cell arrangement on a substrate
US5334802A (en) * 1992-09-02 1994-08-02 Texas Instruments Incorporated Method and configuration for reducing electrical noise in integrated circuit devices
JP2976842B2 (ja) * 1995-04-20 1999-11-10 日本電気株式会社 半導体記憶装置の製造方法
US5926359A (en) * 1996-04-01 1999-07-20 International Business Machines Corporation Metal-insulator-metal capacitor
US20010013660A1 (en) * 1999-01-04 2001-08-16 Peter Richard Duncombe Beol decoupling capacitor
KR100532941B1 (ko) * 1999-06-21 2005-12-02 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP4818578B2 (ja) * 2003-08-06 2011-11-16 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置およびその製造方法
US7366046B2 (en) * 2005-08-16 2008-04-29 Novelics, Llc DRAM density enhancements
JP4887802B2 (ja) * 2006-01-26 2012-02-29 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP4658977B2 (ja) * 2007-01-31 2011-03-23 エルピーダメモリ株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3304651A1 (de) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München Dynamische halbleiterspeicherzelle mit wahlfreiem zugriff (dram) und verfahren zu ihrer herstellung
JPS59154027A (ja) * 1983-02-21 1984-09-03 Mitsubishi Electric Corp 金属パタ−ンの形成方法
GB2145243B (en) * 1983-08-18 1987-08-26 Gen Electric Optical lithographic processes
JPH0618257B2 (ja) * 1984-04-28 1994-03-09 富士通株式会社 半導体記憶装置の製造方法
DE3435750A1 (de) * 1984-09-28 1986-04-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzielen einer konstanten masshaltigkeit von leiterbahnen in integrierten schaltkreisen
US4810619A (en) * 1987-08-12 1989-03-07 General Electric Co. Photolithography over reflective substrates comprising a titanium nitride layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192357A (ja) * 1990-07-23 1992-07-10 Matsushita Electron Corp 半導体記憶装置
US5302538A (en) * 1992-08-04 1994-04-12 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing field effect transistor
KR100230367B1 (ko) * 1996-08-19 1999-11-15 윤종용 반도체 디바이스의 제조방법

Also Published As

Publication number Publication date
US5153689A (en) 1992-10-06
DE3930639C2 (enExample) 1993-01-21
DE3930639A1 (de) 1990-05-17

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