JPH027781A - Synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE:To obtain a stable framing output by comparing the polarity of a signal being the result of frequency-dividing a vertical synchronizing signal with that of a framing signal and correcting the state of a frequency divider circuit only when the polarity of the both is dissident consecutively for a prescribed time or over. CONSTITUTION:The title circuit has a frequency divided circuit 5 inverting the output at each leading of a vertical synchronizing signal and a framing discrimination circuit 6 discriminating the polarity of the framing signal and that of the output of the frequency divider circuit 5, and an H pulse is outputted at an output terminal 63 if the dissidence of the plurality is consecutive for a prescribed time or over, the internal state of the frequency divider circuit 5 is corrected and the polarities at two input terminals 61, 62 of the framing discrimination circuit 6 are made coincident. After the polarity is coincident, since a set input terminal 53 of the frequency divider circuit 5 goes to an L level, the framing output 7 is single frequency division of the vertical synchronizing signal. Thus, even if a signal including noise is given to a video signal input, a stable framing output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization signal separation circuit used in magnetic recording/reproducing devices and the like.

2. Description of the Related Art In recent years, video recording and reproducing devices have greatly developed and are being used in a variety of places. In these video recording/reproducing devices, the synchronization signal is separated from the video signal to control the phase of the motor, and a synchronization signal separation circuit that is less affected by noise contained in the video signal is desired.

An example of the conventional synchronization signal separation circuit described above will be described below with reference to the drawings.

In the conventional synchronization signal separation circuit, as shown in the block diagram of FIG. 4 and the waveform diagram of FIG.
As shown in the figure, a composite synchronization signal is obtained at the output. The output of the composite synchronization signal separation circuit 2 enters the vertical synchronization signal separation circuit 3 and the falling edge detection circuit 4.
A vertical synchronizing signal as shown in FIG. 5C is obtained at the output of , and an output waveform shown in FIG. 6 is obtained at the output of the falling edge detection circuit 4. The output of the falling edge detection circuit 4 is further input to the o, eH monomulti 6.

This o, eH monomulti is a non-retrigger pull type, and the output waveform shown in Fig. 5d is obtained. The output of the 0.6H monomulti 6 and the output of the vertical synchronizing signal separation circuit 3 are input to the D input and clock input of the D flip-flop 6, respectively, and the output waveform shown in FIG. 6e is obtained as a framing output.

Problems to be Solved by the Invention In such a conventional configuration, noise is mixed into the video signal, and the output of the vertical synchronizing signal separation circuit 3 shown in FIG. 5C or as shown in FIG. 5D. When a disturbance occurs in the output waveform of the sH monomulti, the framing output shown in FIG. 5e is easily reversed, resulting in problems such as disturbance of motor phase control.

In view of this, an object of the present invention is to provide a synchronization signal separation circuit that can obtain a stable framing output even when a video signal containing noise is connected.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a composite synchronization signal separation circuit that separates a composite synchronization signal from an input video signal, and a composite synchronization signal separation circuit that separates a composite synchronization signal from the separated composite synchronization signal. A vertical synchronization signal separation circuit that separates a vertical synchronization signal, a framing signal detection circuit that detects a framing signal from a composite synchronization signal, a frequency division circuit that inverts the output every time the vertical synchronization signal rises, and a framing signal and frequency division circuit. and a framing discrimination circuit for discriminating the polarity of the output of the frame detection circuit, and the frequency dividing circuit is set according to the output of the framing discrimination circuit.

According to the above-described configuration, the present invention compares the polarities of a signal obtained by frequency-dividing a vertical synchronizing signal and a framing signal detected from a video signal, and only when the polarities of the two do not match for a certain period of time or more continues. Since the state of the frequency dividing circuit is corrected by the framing signal, even if the framing signal is disturbed by noise, if the disturbance subsides within a certain period of time, the framing output will not be affected in any way and a stable output can be obtained.

Embodiment FIG. 1 is a block diagram showing an embodiment of the synchronization signal separation circuit of the present invention. In FIG. 1, 1 is a video signal input terminal, and 2 is a composite synchronization signal separation circuit. The video signal input from the video signal input terminal 1 is sent to the composite synchronization signal separation circuit 2.
is input to the input terminal 21 of the . Composite synchronization signal separation circuit 2
, the composite synchronization signal is separated from the video signal, output to the output terminal 22, and input to the input terminal 31 of the vertical synchronization signal separation circuit 3. The vertical synchronization signal is separated from the composite synchronization signal in the vertical synchronization signal separation circuit 3, and the vertical synchronization signal is sent to the output terminal 3.
2, and further input to the input terminal 61 of the frequency dividing circuit 6. The frequency divider circuit 6 inverts the level of the output terminal 62 every time the vertical synchronization signal rises, and
2, a signal having a frequency that is one-half that of the vertical synchronizing signal is outputted from the terminal 2 as a framing output, and is also input to one input terminal 61 of the framing discrimination circuit 6.

On the other hand, the output 22 of the composite synchronization signal separation circuit 2 is also input to the input terminal 41 of the framing signal detection circuit 4. The framing signal detection circuit 4 extracts the framing information included in the composite synchronization signal and outputs it from the output terminal 42 as a framing signal. The output framing signal is sent to another input terminal 62 of the framing discrimination circuit 6.
to go into.

In the framing discrimination circuit 6, input terminals 61 and 62
The polarities of the input signals are compared, and if the two polarities match, an L pulse is sent to the output terminal 63, and if the mismatch between the two continues for a certain period of time or more, an L pulse is sent to the output terminal 63.
3, an H pulse is output. The signal at this output terminal 63 enters the cent input terminal 53 of the frequency dividing circuit 6. When the signal level of the input terminal 63 is L, the frequency dividing circuit 5 simply continues frequency division, but the mismatch in polarity between the output of the 1-minute circuit 6 and the output of the framing signal detection circuit 4 continues for a certain period of time. If so, set input terminal 5 of frequency divider circuit 6
An H pulse is generated at the two input terminals 61 .
It operates to match the polarity of 62. After the polarities match, the set input terminal 63 of the frequency divider circuit 5 becomes L level, and the framing output cuff becomes the vertical synchronization signal simply frequency-divided, and the output 42 of the framing signal detection circuit 4
Stable output can be obtained as long as there is no disturbance for a certain period of time.

FIG. 2 shows another embodiment of the present invention, in which a video signal is input from a video signal input terminal 1, and a composite synchronization signal separation circuit 2
is input. Here, the composite synchronization signal is separated, and the waveform shown in FIG. 3a is obtained at the output terminal 22. The separated composite synchronizing signal is input to the vertical synchronizing signal separation circuit 3, where the vertical synchronizing signal is separated, and the waveform shown in FIG. 3 is obtained at the output terminal 32. Furthermore, the vertical synchronizing signal of the output terminal 32 is inputted to the input terminal 51 of the frequency dividing circuit 6. The frequency dividing circuit 6 is composed of a T flip-flop 501, and the level of the output 62 is inverted every time the vertical synchronizing signal rises, so that the waveform shown in FIG. 3d is obtained at the framing output.

On the other hand, the composite synchronization signal is also input to the framing signal detection circuit 4, which determines whether or not there is a horizontal synchronization signal at 3H from the trailing edge of the vertical synchronization signal, and outputs an upward pulse if it exists, and an L if not. Output to terminal 42. That is, the waveform shown in FIG. 3C is obtained.

The output 62 of the frequency dividing circuit 6 and the output 42 of the framing signal detection circuit 4 are input to input terminals 61 and 62 of the framing discrimination circuit 6, respectively. When the input terminal 61 is at the H level as shown in FIG. 3D at the moment when the H pulse is generated at the input terminal 62 as shown in FIG. 3C, the output of the D flip-flop 601 is at the H level. Since the transistor 602 is conductive, the analog comparator 6
The output of 0B is at L level, the output terminal 63 is also at L level, and the frequency dividing circuit 5 continues to divide the frequency. Suppose that for some reason an H pulse is generated at the input terminal 62 in the field opposite to that shown in FIG. 3C, that is, in the right side. At this time, since the level of the input terminal 61 is L, the output of the D flip-flop 601 becomes L level, and the transistor 602 becomes open. Then, the voltage at the plus (+) input terminal of the cosparator eos is the resistor 604.
and increases with a time constant determined by the capacitor 605. If such a state continues for a certain period of time or more, the voltage at the plus input terminal of comparator 608 will be lower than the power supply voltage 6.
07 voltage is exceeded, the output of the comparator 608 becomes H, and the pulse at the input terminal 62 is directly inputted to the cent input terminal 53 of the frequency dividing circuit 5 through the AND gate 609, and the polarity of the output 62 is changed to the H pulse at the input terminal 62. It is corrected so that it becomes H the moment it occurs. If that happens,
When the next H pulse occurs at the input terminal 62, the input terminal 6
1 becomes H level, the output of the D flip 70 knob 601 is H level, the transistor 602 becomes conductive, and the output of the comparator 608 is L level, the set input terminal 63
is also at L level. That is, after that, the frequency dividing circuit 5 performs a simple division operation.

However, it is unlikely that the output pulse of the framing signal detection circuit 4 continues to appear in the opposite field for a certain period of time or longer, except in cases where the video signal input is switched and a discontinuity occurs in the framing. , if it is just a noise, the framing signal detection circuit 4
Even if the output is disturbed, the comparator θ0
The output of No. 8 remains at L, and the framing output cuff always maintains continuity and is stable.

Effects of the Invention As described above, according to the present invention, it is possible to obtain a stable framing output even when a signal containing noise is connected to the video signal input, and is extremely useful in practice. It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchronization signal separation circuit in one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, and FIG. 3 is a block diagram showing a synchronization signal separation circuit in the embodiment of FIG. 2. A waveform diagram of the main parts of the circuit, and FIG. 4 is a block diagram of a conventional synchronization signal separation circuit. FIG. 5 is a waveform diagram of the same main part. 1... Video signal input terminal, 2... Composite synchronization signal separation circuit, 3... Vertical synchronization signal separation circuit, 4... Framing signal detection circuit, 6...
...Frequency divider circuit, 6...Framing discrimination circuit, 7...Framing output terminal, 61.82
...Framing discrimination signal input terminal, 51...
. . . Frequency division input terminal, 62 . . . Frequency division output terminal, 53 . . . Set input terminal. Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

[Claims] A composite synchronization signal separation circuit that separates a composite synchronization signal from an input video signal, a vertical synchronization signal separation circuit that separates a vertical synchronization signal from the composite synchronization signal, and a framing signal detection that detects a framing signal from the composite synchronization signal. circuit, a frequency dividing circuit that inverts the output every time the vertical synchronization signal rises, and a framing discrimination circuit that discriminates the polarity of the framing signal and the output of the frequency dividing circuit, and according to the output of the framing discrimination circuit. A synchronous signal separation circuit characterized in that the frequency dividing circuit is set.