JPS60250780A - Horizontal synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain a horizontal synchronizing circuit having high noise eliminating ability by using a transmission gate realizable by CMOS-IC as a phase comparator. CONSTITUTION:A composite video signal of negative synchronism is impressed to a signal input terminal 51 and synchronizing separated by an amplitude separating transistor TR52, and a positive synchronizing signal is supplied to an input terminal 54 of a transmission gate made up of CMOS-IC through a buffer 53. Further, a comparison signal from a frequency divider is supplied from a comparison input terminal 56 to a control input terminal 55 of a transmission gate. An LPF is connected to an output terminal 57 of the transmission gate. The comparison signal from the frequency divider controls the transmission gate, and takes in the synchronizing signal when the comparison signal is ''H'' level, and does not make phase comparison while the transmisstion gate is off. Thus, the influences of noise included in the synchronizing signal are excluded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a horizontal synchronization circuit used in television equipment, particularly a television receiver.

[Prior art]

In a television receiver, it is necessary to synchronize the receiver with the timing of transmitting the JAL image signal on the transmitting side (7), so a synchronization signal is extracted from the composite video signal and used as a reference signal for horizontal and vertical scanning. .

Since the vertical synchronization signal has a wide pulse width, it is less affected by noise components than the horizontal synchronization signal, so a simple low-pass filter is usually used to separate the vertical synchronization signal.
The vertical oscillator is directly synchronized.

Also, in receivers that do not have a separate vertical lifter, the vertical counter is directly reset.

On the other hand, the horizontal synchronization signal has a pulse width of 5. Since the horizontal oscillator is not directly synchronized with the horizontal synchronization signal, the phase-locked loop (P
LL) and is used as its reference signal.

In a liquid crystal TV that uses a liquid crystal panel as a display device, the configuration of the horizontal synchronization system is similar, and the necessary timing signal is obtained using the output of a frequency divider (counter) included in the PLL system.

In LCD TVs, the logic circuit S is usually 0MO8 in order to effectively utilize the low power consumption, which is a feature of the LCD panel.
Since it takes the configuration, the PLL system is C! It is necessary to realize this in MO8-0.

In the 0MO8-Ikko C, the analog circuit format used in the Biborae C cannot be used in many cases because the development of analog circuits is not sufficient.

Therefore, it is recommended that the constituent elements of the PLL thread be realized using logic elements as much as possible.

FIG. 1 shows an example of a phase comparator that has been put to practical use, and this is composed entirely of logic elements.

The phase ratio S2 device shown in FIG. 1 is the charge pump (54) in FIG.
used with

As shown in FIG. 2, this phase comparator is operated by the output terminals U(13) and D based on the phase difference between the two signals applied to the reference signal input terminal R(11) and the comparison signal input terminal V(12).
(14) A phase comparison output is generated.

Looking at the timing diagram in FIG. 2, it can be seen that the operation is based on the phase difference between the edges (falling edges) of the reference signal R and the comparison signal V.

Generally, there is a lot of noise mixed into the received composite synchronization signal, so it is required for a PLL system to remove the noise component, but the phase comparator shown in FIG. 1 cannot satisfy this requirement.

This is because the phase comparator shown in FIG. 1 operates using only edge information of the input signal, and therefore has no ability to discriminate between noise and synchronization signals.

Therefore, it is inappropriate to employ it in a TV receiver that is expected to be used in a noisy environment.

If this phase comparator is to be employed, noise (pulse nature) must be removed in advance from the composite synchronization signal that is to be the reference signal.

Since this noise removal means requires a considerably large circuit scale, it is impossible to adopt one with sufficient capability, at least at the stage of consumer products.

〔the purpose〕

The present invention has been proposed to solve the above-mentioned drawbacks.It is an object of the present invention to provide a horizontal synchronization circuit with high noise rejection ability by employing a phase comparator that is less likely to malfunction due to noise. .

〔overview〕

According to the present invention, the circuit is simplified because the transmission gate, which can be easily realized with 0MO8-IC, is used with a phase ratio of [6], and its operation is also taken in as pulse width information of the input signal, so the noise resistance performance is good. A horizontal synchronous circuit can be realized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of the horizontal synchronization circuit σ) of the present invention,
FIG. 5 shows an embodiment around the phase comparator.

First, in FIG. 4, a composite synchronization signal is separated by a synchronization separation circuit (42) from a composite video signal input to a video signal input terminal (41), and is supplied as a reference signal to a phase comparator (45).

The phase comparator (46) compares the phases of the horizontal period pulse generated by the frequency divider (46) and the composite synchronization signal, and supplies the phase comparison output to the Z low-pass filter (44).

The phase difference signal filtered by the low pass filter (44) controls the oscillation frequency of the voltage controlled oscillator (45).

A frequency divider (46) divides the output frequency of the voltage controlled oscillator (45) and outputs a group of timing signals necessary for the liquid crystal Hanel driver to a timing signal output terminal (47).

In addition, the frequency divider (46) has the same function as the phase comparator (46).
It also outputs a comparison signal, but its period is a horizontal period,
The pulse width is equal to or less than the horizontal synchronization signal.

FIG. 5 shows an embodiment of the fourth synchronous separation circuit (42), phase comparator (43), and low-pass filter (44).

A synchronous quality composite video signal is applied to the video signal input terminal (51), is synchronously separated by an amplitude separation transistor (52), and is sent to a buffer (55)'? After that, it becomes a positive synchronization signal and is sent to the signal input terminal (5) of the transmission gate.
4).

The comparison signal input terminal (56) is connected to the above-mentioned branching device (40).
A comparison signal from the transmission gate is input to the control input terminal (55) of the transmission gate.

A low pass filter is connected to the output terminal (57) of the transmission gate.

The input/output relationship of this transmission gate is shown in FIG. (It is in a synchronous state.) The transmission gate is controlled by the comparison signal (62) from the branching device (46), and when the comparison signal (62) is at H level, the synchronization signal which is the reference signal (61) is taken in.

The level of the synchronization signal during the period when the transmission gate is on is the comparison output (66).

During the period when the transmission gate is off, that is, when the comparison signal (62) is at L level, the potential held in the low-pass filter becomes the potential of the comparison output (63).

In order to obtain the synchronized state as shown in FIG. 6, the control timing of the voltage controlled oscillator (45) must have the characteristics shown in FIG. 7.

The transmission gate performs a phase comparison operation as shown in FIG. 6, but the feature of the operation of this phase comparator is that the phase comparison operation is not performed while the transmission gate is off.

In other words, it is not affected by noise contained in the synchronization signal (reference signal (62)).

Even during the period when the transmission gate is on, the pulse width of the noise pulse is usually one of the pulse width of the horizontal synchronization signal.
Since it is sufficiently small compared to 72, it does not have a large influence on the comparative output (63).

From these facts, it can be seen that the comparison output (63) is not affected by the noise contained in the synchronization signal, and therefore, a stable synchronization state is maintained even as a PLL system.

In order to obtain the best phase comparison operation of the present invention, there is an optimum value for the comparison signal (62), ie, the ON period of the transmission gate.

As can be seen from Figure 6, the range of phase comparison operation is the maximum phase difference up to ±1 times the pulse width of the horizontal synchronization signal, and at this time the pulse width of the comparison signal is equivalent to that of the horizontal synchronization signal. It is necessary.

If it is less than that, the phase tracking range becomes narrow and the influence of noise becomes large.

Moreover, if it exceeds this, a stable synchronization state cannot be guaranteed.

〔effect〕

According to the present invention, it can be configured with a transmission gate that can be easily implemented with the phase comparator '%' CMO8-No, and the number of elements is very small compared to the conventional one.
It is expected that the horizontal synchronization system will be cheaper and its reliability will be improved.

Furthermore, the above-mentioned advantages are furthered because a noise removal circuit is not required for good noise resistance performance.

At the same time, it has the effect of improving the synchronization performance of television reception.

[Brief explanation of drawings]

FIG. 1 is a conventional phase comparator, FIG. 2 is its operation timing diagram, the third quotient is a block diagram of a horizontal synchronization circuit of a conventional television receiver, and FIG. 4 is a block diagram of a horizontal synchronization circuit of the present invention. FIG. 5 shows an embodiment around the phase comparator, FIG. 6 shows an operation timing diagram of the phase comparator, and FIG. 7 shows control characteristics of the voltage controlled oscillator. (11) Reference signal input terminal R1 (12) Comparison signal input terminal V (16)/(14) Output terminals U/D (51)/(41) Video signal input terminals (32)/(42) Sync separation circuit ( 33) (43) phase comparator, (34) charge pump (55) (44) low pass filter (36) (
45) Voltage controlled oscillator, (37)/(46) Frequency divider (3
8)・(47) Timing signal output terminal (51) Video signal input terminal (52) Amplitude separation transistor (53) Buffer, (54) Signal input terminal (55) Control manual terminal, (515) Comparison signal input terminal (57) ) output terminal, (58) comparison output terminal (61) reference signal, (62
) comparison signal, (63) comparison output. Applicant: Tsutomu Mogami, Patent Attorney Suwa Kozukosha Co., Ltd. Figure 1 Figure 3

Claims (1)

[Claims] In the horizontal synchronization circuit of television equipment, an amplitude-limited composite synchronization signal and a pulse wave having pulses equal to or less than the horizontal synchronization signal generated from the output of the voltage controlled oscillator are respectively used at 0MO8) at the transmission gate. A horizontal synchronization circuit characterized in that a phase comparison operation is performed by applying voltage to a signal input terminal and a control input terminal.