JPH0275739U - - Google Patents
Info
- Publication number
- JPH0275739U JPH0275739U JP15574888U JP15574888U JPH0275739U JP H0275739 U JPH0275739 U JP H0275739U JP 15574888 U JP15574888 U JP 15574888U JP 15574888 U JP15574888 U JP 15574888U JP H0275739 U JPH0275739 U JP H0275739U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- package
- transistor
- sealed
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図は本考案の一実施例の下面図、第２図は
本考案の一実施例をプリント基板にハンダ付けし
た場合の断面図、第３図は従来のトランジスタの
下面図、第４図は従来のトランジスタをプリント
基板にハンダ付けした場合の断面図である。
１，１Ａ…トランジスタ、２Ａ〜２Ｃ…リード
、３…パツケージ、４…ソルダーレジスト膜、５
…プリント基板、６…パターン、７…ハンダ。
Fig. 1 is a bottom view of an embodiment of the present invention, Fig. 2 is a sectional view of an embodiment of the present invention soldered to a printed circuit board, Fig. 3 is a bottom view of a conventional transistor, and Fig. 4 is a cross-sectional view of a conventional transistor soldered to a printed circuit board. 1, 1A...Transistor, 2A-2C...Lead, 3...Package, 4...Solder resist film, 5
...Printed circuit board, 6...pattern, 7...solder.
Claims (1)
ジの下面より十字形状に引き出されたリードとを
有するトランジスタにおいて、リード引き出し部
近傍の前記リードの表面は絶縁膜で覆われている
ことを特徴とするトランジスタ。 1. A transistor comprising a package in which a semiconductor element is sealed and a lead drawn out in a cross shape from the bottom surface of the package, wherein the surface of the lead near the lead lead-out part is covered with an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15574888U JPH0275739U (en) | 1988-11-29 | 1988-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15574888U JPH0275739U (en) | 1988-11-29 | 1988-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0275739U true JPH0275739U (en) | 1990-06-11 |
Family
ID=31433648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15574888U Pending JPH0275739U (en) | 1988-11-29 | 1988-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0275739U (en) |
-
1988
- 1988-11-29 JP JP15574888U patent/JPH0275739U/ja active Pending