JPH0272561U - - Google Patents
Info
- Publication number
- JPH0272561U JPH0272561U JP15204988U JP15204988U JPH0272561U JP H0272561 U JPH0272561 U JP H0272561U JP 15204988 U JP15204988 U JP 15204988U JP 15204988 U JP15204988 U JP 15204988U JP H0272561 U JPH0272561 U JP H0272561U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit element
- resin layer
- sealing resin
- external leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は、本考案に利用するリードフレームの
上面図、第２図は、このリードフレームにより製
造した樹脂封止型集積回路素子の断面図、第３図
は、第２図の回路の等価回路図、第４図は、従来
の樹脂封止型集積回路素子により利用するリード
フレームの上面図、第５図は、第４図のリードフ
レームにより製造した樹脂封止型集積回路素子の
断面図、第６図ａ，ｂは、この集積回路素子に取
付ける外囲器のリード配置を示す図、第７図は、
第４図の樹脂封止型集積回路素子の等価回路図、
第８図の回路図は、第７図の応用例、第９図は、
外囲器のリードの配列とインダクタンスの関係を
示す曲線図である。
１〜１２：リード、１４：平坦なベツド、１４
：封止樹脂層、Ｇ１〜Ｇ３：インバータ、Ａ，Ｂ
，Ｃ：出力リード。
Fig. 1 is a top view of the lead frame used in the present invention, Fig. 2 is a cross-sectional view of a resin-sealed integrated circuit element manufactured using this lead frame, and Fig. 3 is an equivalent circuit of the circuit shown in Fig. 2. Circuit diagram, FIG. 4 is a top view of a lead frame used with a conventional resin-sealed integrated circuit element, and FIG. 5 is a cross-sectional view of a resin-sealed integrated circuit element manufactured using the lead frame of FIG. 4. , FIGS. 6a and 6b are diagrams showing the lead arrangement of the envelope attached to this integrated circuit element, and FIG.
An equivalent circuit diagram of the resin-sealed integrated circuit element shown in FIG.
The circuit diagram in Figure 8 is an application example of Figure 7, and the circuit diagram in Figure 9 is
FIG. 3 is a curve diagram showing the relationship between the arrangement of leads of the envelope and inductance. 1-12: Lead, 14: Flat bed, 14
: Sealing resin layer, G1 to G3: Inverter, A, B
, C: Output lead.
Claims (1)
路素子と電気的に接続し、封止樹脂層外に導出す
る複数の外部リードと、この外部リードのうち、
複数の接地リードに隣接して配置する出力リード
を具備することを特徴とする樹脂封止型集積回路
。 A sealing resin layer that covers the integrated circuit element, a plurality of external leads electrically connected to the integrated circuit element and led out of the sealing resin layer, and among these external leads,
A resin-sealed integrated circuit comprising an output lead disposed adjacent to a plurality of ground leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15204988U JPH0272561U (en) | 1988-11-22 | 1988-11-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15204988U JPH0272561U (en) | 1988-11-22 | 1988-11-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0272561U true JPH0272561U (en) | 1990-06-01 |
Family
ID=31426634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15204988U Pending JPH0272561U (en) | 1988-11-22 | 1988-11-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0272561U (en) |
-
1988
- 1988-11-22 JP JP15204988U patent/JPH0272561U/ja active Pending