JPH0272536U - - Google Patents
Info
- Publication number
- JPH0272536U JPH0272536U JP1988150745U JP15074588U JPH0272536U JP H0272536 U JPH0272536 U JP H0272536U JP 1988150745 U JP1988150745 U JP 1988150745U JP 15074588 U JP15074588 U JP 15074588U JP H0272536 U JPH0272536 U JP H0272536U
- Authority
- JP
- Japan
- Prior art keywords
- circuit electrode
- metal plate
- wiring board
- printed wiring
- electrode portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案による金属板の回路電極部の斜
視図、第２図は上記の回路電極部にめつき処理を
施した模式的断面図、第３図は上記の回路電極部
にボンデイング装置のキヤピラリーが降下する模
様を模式的に示す図、第４図は上記のボンデイン
グ後の拡散層形成の模様を示す模式図、第５図は
ワイヤボンデイング法による半導体チツプの実装
部分の断面概念図、第６図は従来例の回路電極部
とボンデイングワイヤとの拡散接合面を示す模式
図、第７図は従来例の回路電極部上のめつき層の
曲面化を示す断面図である。
１：金属板、１ａ：回路電極部、１ｂ：脚部、
１ｃ：切割部、２：絶縁基板、３：半導体チツプ
、４：ボンデイングワイヤ。
Figure 1 is a perspective view of the circuit electrode part of the metal plate according to the present invention, Figure 2 is a schematic cross-sectional view of the circuit electrode part subjected to plating treatment, and Figure 3 is a bonding device attached to the circuit electrode part. FIG. 4 is a schematic diagram showing the pattern of diffusion layer formation after bonding, FIG. 5 is a cross-sectional conceptual diagram of the part where the semiconductor chip is mounted by wire bonding, FIG. 6 is a schematic diagram showing a diffusion bonding surface between a circuit electrode part and a bonding wire in a conventional example, and FIG. 7 is a sectional view showing a curved surface of a plating layer on a circuit electrode part in a conventional example. 1: metal plate, 1a: circuit electrode part, 1b: leg part,
1c: Cut portion, 2: Insulating substrate, 3: Semiconductor chip, 4: Bonding wire.
Claims (1)
らなり、該金属板の回路電極部に半導体チツプと
を直接ワイヤボンドすることにより実装するプリ
ント配線板において、上記回路電極部が長さ方向
に平行した２本の脚部が形成されるように切割部
が設けられてなることを特徴とするプリント配線
板。 In a printed wiring board consisting of an insulating substrate and a conductive metal plate that forms a circuit, and in which a semiconductor chip is mounted by direct wire bonding to the circuit electrode portion of the metal plate, the circuit electrode portion is A printed wiring board characterized in that a cut portion is provided to form two parallel leg portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988150745U JPH0272536U (en) | 1988-11-21 | 1988-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988150745U JPH0272536U (en) | 1988-11-21 | 1988-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0272536U true JPH0272536U (en) | 1990-06-01 |
Family
ID=31424160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988150745U Pending JPH0272536U (en) | 1988-11-21 | 1988-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0272536U (en) |
-
1988
- 1988-11-21 JP JP1988150745U patent/JPH0272536U/ja active Pending