JPH02116741U - - Google Patents
Info
- Publication number
- JPH02116741U JPH02116741U JP2639989U JP2639989U JPH02116741U JP H02116741 U JPH02116741 U JP H02116741U JP 2639989 U JP2639989 U JP 2639989U JP 2639989 U JP2639989 U JP 2639989U JP H02116741 U JPH02116741 U JP H02116741U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- integrated circuit
- electrically connected
- external electrode
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は集積回路パツケージの斜視図、第２図
は第１図のＡ視図である。
図中、１……集積回路パツケージ、２……スル
ーホール、３……多層セラミツク基板、４……配
線パターン、５……突起電極（外部電極）、６…
…内部配線、７……鍍金引き出し線。
FIG. 1 is a perspective view of the integrated circuit package, and FIG. 2 is a view from A in FIG. In the figure, 1... integrated circuit package, 2... through hole, 3... multilayer ceramic substrate, 4... wiring pattern, 5... protruding electrode (external electrode), 6...
...Internal wiring, 7...Plated lead wire.
Claims (1)
めの多層セラミツク基板の主面上に、前記半導体
素子の電極と電気的に接接続される配線パターン
が形成されるとともに、前記基板の裏面に、前記
基板の各層に形成された内部配線およびスルーホ
ールを介して前記配線パターンと電気的に接続さ
れた外部電極を有する集積回路パツケージにおい
て、 前記内部配線と電気的に接続された鍍金引き出
し線を、前記基板の主面上に露出させたことを特
徴とする集積回路パツケージ。[Claims for Utility Model Registration] A wiring pattern electrically connected to the electrodes of the semiconductor element is formed on the main surface of a multilayer ceramic substrate for mounting a semiconductor element on which an integrated circuit is formed, and , an integrated circuit package having, on the back surface of the substrate, an external electrode electrically connected to the wiring pattern via internal wiring and through holes formed in each layer of the substrate, the external electrode being electrically connected to the internal wiring. An integrated circuit package characterized in that a plated lead wire is exposed on the main surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2639989U JPH02116741U (en) | 1989-03-08 | 1989-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2639989U JPH02116741U (en) | 1989-03-08 | 1989-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02116741U true JPH02116741U (en) | 1990-09-19 |
Family
ID=31247986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2639989U Pending JPH02116741U (en) | 1989-03-08 | 1989-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02116741U (en) |
-
1989
- 1989-03-08 JP JP2639989U patent/JPH02116741U/ja active Pending