JPH02120865U - - Google Patents
Info
- Publication number
- JPH02120865U JPH02120865U JP2919489U JP2919489U JPH02120865U JP H02120865 U JPH02120865 U JP H02120865U JP 2919489 U JP2919489 U JP 2919489U JP 2919489 U JP2919489 U JP 2919489U JP H02120865 U JPH02120865 U JP H02120865U
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- resin layer
- polymer resin
- circuit board
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002952 polymeric resin Substances 0.000 claims description 3
- 229920003002 synthetic resin Polymers 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の実施例の斜視図、第２図は本
考案の実施例の断面図、第３図は従来例の断面図
である。
図において、１はチツプ部品、２は電極、４は
半田、５はセラミツクス基板、６は高分子樹脂層
、７はパターン、９は電源／アースパターン、１
０はパツド、１５は孔をそれぞれ示す。
FIG. 1 is a perspective view of an embodiment of the present invention, FIG. 2 is a cross-sectional view of the embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional example. In the figure, 1 is a chip component, 2 is an electrode, 4 is solder, 5 is a ceramic substrate, 6 is a polymer resin layer, 7 is a pattern, 9 is a power supply/earth pattern, 1
0 indicates a pad, and 15 indicates a hole.
Claims (1)
形成してなる回路基板に、チツプ部品１を搭載す
る回路基板装置であつて、 該高分子樹脂層６の表面に形成された、該チツ
プ部品１を半田付け搭載するパツド１０の所望の
個所に、該高分子樹脂層６の表面に通ずる孔１５
が設けられたことを特徴とするチツプ部品実装用
パツド。[Scope of Claim for Utility Model Registration] A circuit board device in which a chip component 1 is mounted on a circuit board formed by forming a polymer resin layer 6 on the surface of a ceramic substrate 5, which comprises: A hole 15 communicating with the surface of the polymer resin layer 6 is provided at a desired location of the formed pad 10 on which the chip component 1 is mounted by soldering.
A chip component mounting pad characterized by being provided with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2919489U JPH02120865U (en) | 1989-03-15 | 1989-03-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2919489U JPH02120865U (en) | 1989-03-15 | 1989-03-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02120865U true JPH02120865U (en) | 1990-09-28 |
Family
ID=31253193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2919489U Pending JPH02120865U (en) | 1989-03-15 | 1989-03-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02120865U (en) |
-
1989
- 1989-03-15 JP JP2919489U patent/JPH02120865U/ja active Pending