JPH0260130A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable silicon nitride film/oxide film to be thinned while reducing the ion implanting energy by a method wherein polysilicon/silicon nitride film/ oxide film are used as ion-implanting masks to form an outer base region. CONSTITUTION:An oxide film 2 in specified thin thickness and a silicon nitride film 3 are formed on an N type semiconductor substrate 1. Next, a polysilicon 4 is formed in specified thickness and then polysilicon 4 and a silicon nitride film 3 are selectively removed except at a region A whereon an emitter is to be formed. Then, after covering the part excluding a base forming region with a resist 5, boron is implanted using the resist 5 and polysilicon 4/silicon nitride film 3/oxide film 2 as masks to implant boron for forming a region 9 in the silicon. Furthermore, after selectively removing the polysilicon 4, boron is introduced through silicon nitride film 3/oxide film 2 to form an inner base region 10. Through these procedures, the energy in case of ion implantation can be notably reduced, enabling the depth of the outer base region 9 to be thinned.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a high frequency, high speed bipolar transistor having a shallow base region.

<Conventional technology> In recent years, high speed and high frequency characteristics have become increasingly required for bipolar transistors, and it has become necessary to control the base and emitter of transistors and form them into extremely shallow structures. It's getting worse. An example of a conventional transistor formation method to meet these requirements is shown in the second section.
Shown in Figures (a) to (d).

An oxide film 2 of about 500X is grown on an N-type semiconductor substrate 1, and then an oxidation-resistant silicon nitride film 3 of about 1000X is grown. Thereafter, the nitride film 3 is selectively removed, leaving the region where the emitter will be formed.

Next, the oxide film in the region surrounding the emitter region that will become the base region is selectively removed using a photo-etching method, and using the resist 5 and the two-layer film of silicon nitride film 3/oxide film 2 as a mask, for example, 20KeV.

2×11)+5 ions/7 boron are introduced into the silicon exposed portion by ion implantation to form the external base region 9.

Next, about 150KeV, lX1013ioy/cr
Boron A is introduced into the silicon substrate using the resist 5 as a mask. At this time, this impurity is introduced not only into the external base region 9 but also into the silicon substrate below this two-layer film through the two-layer film of silicon nitride film 3/oxide film 2, thereby forming an internal base region 10. . Thereafter, impurities are diffused in an oxidizing atmosphere, and then the two-layer film of silicon nitride film 3/oxide film 2 is removed.

Next, arsenic-doped polysilicon 7 is molded and grown.
Impurities are selectively introduced into the emitter region 11.

<Problems to be Solved by the Invention> In the conventional manufacturing method described above, the external base and internal base are separately formed using a two-layer film of silicon nitride film/oxide film.
The thickness of the two-layer film is designed so that it can be used as a mask when forming an external base.

Therefore, the film thickness needs to be about 1500λ or more, and the ion implantation for forming the internal base needs to be 100 KeV or more, which makes the impurity profile gentle. In order to prevent this, a method of further lowering the external base ion implantation energy can be considered, but this method has drawbacks such as poor current throughput during ion implantation and a tendency to cause channeling effects. It is also conceivable to use a heavy r impurity such as BF2, but this is not practical because leakage occurs due to crystal defects.

In other words, with the above method, the internal base profile becomes gentle, making it difficult to fabricate an extremely shallow transistor with an active base width of 0.1 μm or less.

<Means for Solving the Problems> In order to solve the problems of the above-mentioned conventional methods, the present invention introduces externally based impurities using a three-layer structure film of polysilicon/silicon nitride film/oxide film as a mask. Thereafter, the polysilicon film is removed and impurities are applied internally through the two-layer film of silicon nitride film/oxide film to form the impurity region of the bipolar transistor.

In the present invention, in order to use the three-layer film of polysilicon/silicon nitride film/oxide film as a mask for ion implantation for forming an external base, the film thickness of the two-layer film of silicon nitride film/oxide film is reduced. This makes it possible to reduce the acceleration energy of ion implantation for forming the internal base 2, and the internal base profile becomes steep.

As a result, a transistor with an extremely shallow structure having an active pitch width of about 0.05 μm can be manufactured with good reproducibility.

<Example> The present invention will be described in detail using an example of an npn transistor in FIGS. 1(a) to 1(f).

As shown in FIG. 1(a), 300 nm
After growing a thin oxide film 2 of about 300λ, a silicon nitride film 3 of about 300λ is grown.

Next, polysilicon 4 is further grown to an extent of zoooX using the CVD method.

As shown in FIG. 1(b), the polysilicon 4 and the silicon nitride film 3 are selectively removed by photo-etching, leaving at least the region A where the emitter is to be formed, and removing the polysilicon 4 and the silicon nitride film 3 in other regions.

Next, as shown in FIG. 1C, after covering the area other than the area where the base will be formed with a resist 5 using photolithography, the resist 5 and the polysilicon 4/silicon nitride film 3/oxide film 2 are formed. Using the three-layer film as a mask, ion implantation is used to implant boron 2X1 at an acceleration energy of approximately 20KeV.
A region 9 is formed by introducing 0.015 ion/d into the silicon.

Next, as shown in FIG. 1(d), after selectively removing the polysilicon 4 by wet etching or dry etching, boron is exposed to iX with an acceleration energy of about 30 KeV.
About 1013 ions/d are introduced into the substrate through the two-layer film of silicon nitride film 3/oxide film 2 to form an internal base region 10.
form. At this time, the ion implantation into the central base region 10 is performed through the two-layer film of the silicon nitride film 3/oxide film 2, which is thinner than the conventional method in which the polysilicon 4 is removed, so the energy at the time of implantation is as described above. It is significantly smaller than the conventional method. Therefore, the depth of impurities in the external base region 9 itself becomes thinner.

After implanting impurity ions as described above, the resist is removed as shown in FIG. 1(e), and then the oxide film 6 is formed by thermal oxidation.
is grown to about 1500λ.

As shown in Figure 1(f), after removing the two-layer film of silicon nitride film 3/oxide film 2 that covered the substrate surface in the area that would become the emitter region, arsenic was doped onto the area that would become the emitter region. After forming a polysilicon film 7 and patterning it by photo-etching, a CVD oxide film 8 is grown, and arsenic is diffused into the substrate from the remaining polysilicon film 7 to form a nitrogen film on the active space region 12 of the silicon substrate. An emitter region 11 is formed. In the figure, reference numeral 13 indicates an electrode that is in contact with the impurity region.

Effect> In the present invention as described above, the implantation energy for forming the internal paste can be as low as about 30 KeV, so that the impurity profile of the internal base can be extremely shallow and steep, and the junction depth can be reduced. The thickness can be about 0.1 μm. Since the junction depth of arsenic diffusion from polysilicon can be controlled to about 0.05 μm, the pace width directly below the emitter, that is, the active pace width, can be precisely controlled to about 0.05 μm, realizing ultra-high speed and ultra-high frequency transistors. be done.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are sectional views at each step of an embodiment of the present invention, and FIGS. 2(a) to 2(d) are sectional views at each step of a conventional example. 1. N-type semiconductor substrate 2. Thin oxide film 3. Silicon nitride film 4. Polysilicon 5. Resist 6 Oxide film 7. Arsenic doped polysilicon 8CVD oxide film 9. P+ external pace area io, P- internal pace area 11. N+ Eminoku region 12° active base region
13. Electrode agent Patent attorney Takeshi Sugiyama (1 other person) +4-A
-+1 Figure 2! 111! ! 11

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor device in which a bipolar transistor is formed on a substrate of one conductivity type, a thin oxide film, an oxidation-resistant film, or a polysilicon film is formed on the substrate at least in a region where an emitter is formed. Then, using the three-layer film as a mask, impurities of the second conductivity type are selectively introduced into the substrate outside the region where the emitter will be formed. After the above process, the polysilicon film is selectively removed and acid-resistant 1. A method for manufacturing a semiconductor device, which comprises selectively introducing impurities of a second conductivity type into a substrate through a two-layer film of an oxide film and a thin oxide film.