JPH0253032A - Wiring pattern - Google Patents

Abstract

PURPOSE:To prevent a defect phenomenon such as a short circuit due to the breaking of a wiring path which is large in line width and the resticking of a peeled broken piece by providing a pattern defective part to the wiring path. CONSTITUTION:The floating and separation of a wiring layer are caused at the border between a 1st amorphous silicon layer 18' which contains no impurity and a 2nd amorphous silicon layer 20' which contains phosphorus as impurities. For the purpose, the wiring layer consisting of the amorphous silicon layers 18' and 20', a heat-resisting barrier layer 23, and conductive thin films 26 and 27 is provided and an in-pattern removed part 28 is interposed in the wide area of the wiring layer. Therefore, there is none of A as a wiring material, MoSi2 for the heatresisting barrier layer 23, and 1st and 2nd amorphous silicon layers 18' and 20' present at the pattern defective part 28 in a five-mask process and the flank of those thin films is exposed in the section of its opening part. Consequently, degassing and strain relieving are accelerated to prevent the wiring layer from being peeled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal panel having an image display function, and an active matrix substrate having a built-in switching element for each pixel.

Conventional technology Advances in microfabrication technology, liquid crystal materials, packaging technology, etc. have made it possible to obtain television images at a commercial pace with a small screen size of about 2 to 6 inches on a liquid crystal panel that does not pose any problem in practical use. .

By forming an RGB colored layer on one of the two glass plates that make up the liquid crystal panel, color display can be easily realized, and in so-called active type liquid crystal panels in which each pixel has a built-in switching element, An image with low crosstalk and high contrast ratio is ensured.

Such a liquid crystal panel has 120 to 240 scanning lines.
There are approximately 240 to 720 main and signal lines.Ma) Substation J
For example, as shown in FIG. 2, a semiconductor integrated circuit supplies drive signals to a group of scanning line terminals (not shown) formed on one glass substrate 2 constituting a liquid crystal panel 1. COG (chip/
The liquid crystal display can be mounted using the on-glass method, or by mounting means such as fixing a connection film 4 based on a polyimide resin thin film and having a group of gold-plated copper foil terminals on the terminal group 5 of the signal line while press-fitting it. An electric signal is supplied to the image display section of the middle man on the panel 1. Note that 6.7 is a wiring path that connects the image display section and the signal line terminal group 6 and the scanning line terminal group, and does not necessarily need to be made of the same conductive material as the terminal group. .

8 is another glass plate that has a common counter electrode for all pixels on its opposing surface, and the two glass plates 2 and 8 face each other with a predetermined distance apart, and the gap is filled with a sealing material and a sealing material. It is a closed space sealed with liquid crystal and filled with liquid crystal. In most cases, an organic thin film containing a coloring material such as a dye or a pigment, called a colored layer, is applied to the closed space side of the glass plate 8 to provide a color display function. It's called a color filter. Then, depending on the properties of the liquid crystal material, a polarizing plate is pasted on either the upper surface of the glass plate 8 or the lower surface of the glass plate 2, or on both surfaces to function as an electro-optical element.

FIG. 3 is an equivalent circuit diagram of an active liquid crystal panel in which an insulated gate transistor 9 is arranged for each pixel as a switching element, and the solid line is formed on one substrate 2 and the dotted line is formed on the other substrate 8. There is. FIG. 4 is an example of a plan view of the unit picture elements of the active matrix substrate 2. As shown in FIG. The scanning line 1o and the signal line 11 serve as the gate and source of a thin film transistor 9 whose semiconductor layer is, for example, amorphous silicon and whose gate insulating film is a silicon nitride film, and whose drain is connected to a transparent conductive picture element electrode 13. ing. The liquid crystal cell 12 consists of a pixel electrode 13, a transparent conductive counter electrode 14 formed on the color filter 8, and a liquid crystal that fills a closed space made up of two glass plates. It is treated the same as a capacitor.

Note that in FIG. 3, the storage capacitor 16 is not necessarily an essential component of an active liquid crystal panel, but it is useful for improving the utilization efficiency of the driving signal source, leak resistance when the thin film transistor is turned off, and liquid crystal material. It is appropriately adopted because it has the function of maintaining characteristics against an increase in resistance.

Problems to be Solved by the Invention Coupled with its novelty, an insulated gate transistor that uses amorphous silicon as a semiconductor layer and a silicon nitride film as a gate insulating film offers a flexible degree of freedom in device structure and manufacturing method. In addition, since there are loose restrictions on electrode materials, various conductive materials are used.A cross-sectional view of the process along the Moum' line in FIG. 4 will be explained with reference to FIG. First, as shown in FIG. 5 (2L), on one main surface of the glass substrate 2, a transparent conductive thin film such as ITO is selectively deposited to form a pixel electrode 13 with a film thickness of about 1000. CvD SiO2 film 16 on the entire surface.

Deposit with a film thickness comparable to that of a human body. Next, as shown in FIG. 5('b), a wiring pattern 1Q serving as a gate electrode and a scanning line is formed.
is selectively deposited with an orifice having a film thickness of about 1,000 people. Then, as shown in FIG. 5(0), a SiNx layer 17 that becomes a gate insulating film, a first amorphous silicon layer 18 that contains almost no impurities that becomes a semiconductor layer, and a SiNx layer 19 that becomes an etching stopper are etched with a film thickness of, for example, 4000. people-500
After depositing a film with a thickness of about 1000 people, the top layer of Si
Only the Nx layer is selectively left as 19'. then the fifth
As shown in Figure (d), after depositing the second amorphous silicon layer 2o containing impurities on the entire surface, the first and second amorphous silicon layers are deposited only in the region where the transistor is to be formed. Leave it as an island and make it 20.18'. Continue with Figure 5 (+
As shown in 5), the SiNx layer 17 on the picture element electrode 13
Then, an opening 21 is formed in the SiO2 layer 16 and an opening (not shown) is formed in the SiNx layer 17 on the scanning line 10 in an area outside the image display area to expose a part of the picture element electrode 13 and the scanning line 10. The final process is as shown in Figure 5 (0), after depositing Mo512 as a heat-resistant barrier layer and Moβ as a source/drain wiring layer to a film thickness of about 1 μm on the entire surface, 1,000 layers each and a film thickness of about 1 μm are applied. Leave source (signal line) 1
1. Drain 22 and continue using Ml as a mask! An active matrix substrate forming a liquid crystal panel is completed by leaving MoSi 223 and second amorphous silicon 2d only under the wiring 11.21. Although not shown, there are people in the opening above the scanning line 1o! A wiring path is formed.

The above-mentioned matrix substrate can be obtained by performing the photomask process six times, but it is extremely important to rationalize this process to five times from the viewpoint of improving productivity. This process will be explained below.

The point of change is that after the second amorphous silicon layer 2Q is deposited on the entire surface, as shown in FIG. 2 amorphous silicon layers f8, 20 and Si, N4 layers 17 and 5i02
Although the process is carried out all at once for the multilayer film consisting of layer 16, the details thereof will be omitted here.

Thereafter, the matrix substrate 2 shown in FIG. 6 is obtained by going through the same steps as in the previous example.

As can be seen from the comparison between Figure 6(f) and Figure 6<b), 6
21 MoSi workers were involved in the mask process! All of the source/drain wirings 11 and 22 are present on the 5iNX layer 17 via the second and first amorphous silicon layers 201' and 18', and in the six mask process, the second
The difference is that a first amorphous silicon layer 20.degree.

This difference does not cause any trouble in the image display area, but as shown in FIG.
It has been found that in severe cases, local peeling of the wiring layer can cause significant damage.

However, such a phenomenon occurs very rarely in the human e wiring path 26, which is not wide, and no lifting of the AJ wiring path was observed throughout the entire matrix substrate 2 in the 6-mask process.

In the image display section, the line width of the signal line 11 is changed because there is no need to flow large currents or high-speed frequency components, the resistance of the human β is low, and in addition, a wide line width causes a decrease in the aperture ratio. need not exceed 20 μm. However, when COG mounting is adopted, a large number of semiconductor integrated circuit chips are arranged around the matrix substrate 2 in order to supply driving signals to the image display section, and high-speed It is necessary to send and receive clock signals, and V
Since a considerable amount of current also flows through power lines such as Sg and van, unless wiring paths with a certain large line width are prepared, there is a risk that the semiconductor integrated circuit will malfunction due to clock noise and the displayed image will be distorted. In addition, it is not always necessary to use low-resistance MuE for the source/drain wiring, and transparent conductive rTo thin films are often used to streamline the manufacturing process, but in this case, within the allowable range. If the line width is not widened, the resistance value will increase, which is disadvantageous.

Analysis of the lifting and peeling 26 of the wiring layer shown in FIG. 7 (IL) reveals that the cross-sectional view along the line B-B' shows that the first amorphous layer does not contain impurities as shown in FIG. 7 (b). silicon layer 1
8′ and a second amorphous silicon layer 2 containing the adjacent layer as an impurity.
It was found that this occurs at the boundary with 0'. As mentioned earlier, the first and second amorphous silicon layers 18 and 20 are formed by discontinuous deposition due to the manufacturing process, and both contain a large amount of hydrogen to maintain their film quality. It is thought that hydrogen degassing occurs due to heating, and the accompanying lattice rearrangement at the interface causes strain and causes peeling. In particular, the heat-resistant barrier layer 23 and the source/drain wiring 11
When ゜22 is present on the second amorphous silicon 20',
It was also found that the cap action rapidly promoted peeling.

Means for Solving the Problems Based on the above-mentioned analysis results, the present invention proposes a method to eliminate pattern defects in wiring paths with wide line widths in order to alleviate strain during lattice rearrangement and to alleviate degassing suppression due to the cap effect. It is something to give.

In the 6-mask process, the wiring material Mut1 heat-resistant barrier layer MoSi2 and the first and second amorphous silicon layers are not present in the working pattern defective part, and the side surfaces of these thin films are not present in the cross section of the opening. is exposed. As a result, degassing and strain relaxation are promoted and peeling of the wiring layer is prevented.

EXAMPLE As shown in FIG. 1, openings 28 of 40 μm square were arranged as defective portions at appropriate intervals in a wiring layer 27 with a line width of 80 μm, and 2oO Even when the finished product was subjected to heating treatment at temperatures below .degree. C. and baking at 260.degree. C. for 1 hour to stabilize the transistor characteristics, no peeling or lifting was observed in the 20 .mu.m wiring layer 26.

Note that the present invention avoids the physical principle caused by the interface between an amorphous silicon layer containing impurities and an amorphous silicon layer not containing impurities, and is also effective for devices and processes other than the above embodiments. Needless to say, although the differences are different, they are effective.

Effects of the Invention As described above, by using the wiring pattern of the present invention, defective phenomena such as disconnection of wiring paths and short circuits due to reattachment of peeled fragments are eliminated, and the cleanliness of the manufacturing process is also maintained. In addition, it has become possible to arrange a wide pattern with a low resistance value on the matrix substrate, resulting in significant effects such as shielding effect and ensuring low impedance.

[Brief explanation of the drawing]

Fig. 1 is a wiring pattern diagram according to an embodiment of the present invention, Fig. 2 is a mounting diagram on a liquid crystal panel, Fig. 3 is an equivalent circuit diagram of an active type liquid crystal panel, and Fig. 4 is a diagram of a unit pixel on a matrix substrate. The plan view, FIGS. 5 and 6 are cross-sectional views of the main parts along the line 5--6 in FIG. 4, and FIG. 7 is a wiring pattern diagram according to a conventional example. 1...Liquid crystal panel, 2...Matrix substrate, 9...Insulated gate transistor, 1o
...Scanning line, 11...Signal line, 12.
...Liquid crystal cell, 13...Picture element electrode, 17
・・・・・・5i5N4 layer, 18・Amorphous silicon layer containing no impurities, 19・・・Si, N4f
l, 20...Amorphous silicon layer containing impurities,
23...Heat-resistant barrier layer, 24, 27...
. . . Wiring layer with thick line width, 26 . . . Wiring layer with thin line width, 28 . . . Defected portion in wiring pattern. Name of agent: Patent attorney Shigetaka Awano and 1 other person17
---Blade, 3N4屡/-m-Liquid crystal spring, ν 1 figure δ-color fumerta! q-Ichitsu sphere gate type transsonuk/Z-Ichiro crystal gel diagram? Figure (α) ? (b) /Q -11 friend review//---5th training chart/'7--1, 5i3NaJ (C)? (ct) 3 Heat-resistant buff J Figure (a) (b)

Claims (1)

[Claims] It has a wiring layer formed of an impurity-free amorphous silicon layer provided on a silicon nitride film, an impurity-containing amorphous silicon layer, a heat-resistant barrier layer, and a conductive thin film, and the wiring layer has a wide width. A wiring pattern characterized by having a deletion portion in a region.