JPH0252464A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPH0252464A
JPH0252464A JP63203640A JP20364088A JPH0252464A JP H0252464 A JPH0252464 A JP H0252464A JP 63203640 A JP63203640 A JP 63203640A JP 20364088 A JP20364088 A JP 20364088A JP H0252464 A JPH0252464 A JP H0252464A
Authority
JP
Japan
Prior art keywords
bypass capacitor
memory device
semiconductor memory
container
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63203640A
Other languages
Japanese (ja)
Inventor
Nobuhiko Eguchi
信彦 江口
Yuji Negishi
祐二 根岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63203640A priority Critical patent/JPH0252464A/en
Publication of JPH0252464A publication Critical patent/JPH0252464A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To eliminate a need to mount a bypass capacitor and to reduce a production cost by a method wherein the bypass capacitor is built inside a semiconductor memory device. CONSTITUTION:A semiconductor memory device where a bypass capacitor 1 is inserted between a power-supply terminal 2 and a ground terminal 3 is sealed in a container 6 identical to that of a semiconductor chip 6. That is to say, the bypass capacitor 1 is connected to a suspension pin 4 connected to an island 5 (which is connected to the ground terminal 3) where the semiconductor chip 6 has been loaded and to an inner lead 21 (which is connected to the power supply terminal 2) adjacent to it; these are sealed in the container 7. Since the container is much larger as compared with the semiconductor chip, in many cases there is sufficient room to mount a small-sized capacitor.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体記憶装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

〔従来の技術〕[Conventional technology]

従来半導体記憶装置は、バイパスコンデンサを内蔵して
いないので、プリント基板に実装する場合は、１個あた
りに必ず１個の電源ラインのバイパスコンデンサを実装
していた。Conventional semiconductor memory devices do not have built-in bypass capacitors, so when they are mounted on a printed circuit board, one power line bypass capacitor is always mounted on each semiconductor memory device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このなめメモリパッケージを製造する場合には、必ず一
組の半導体記憶装置とバイパスコンデンサを実装しなけ
ればならないので、実装密度が低くなってしまうという
欠点がある。When manufacturing this diagonal memory package, it is necessary to mount one set of a semiconductor memory device and a bypass capacitor, so there is a drawback that the packaging density becomes low.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体記憶装置は、電源端子と接地端子との間
にバイパスコンデンサが挿入されて半導体チップと同じ
容器に封止されているというものである。In the semiconductor memory device of the present invention, a bypass capacitor is inserted between a power supply terminal and a ground terminal, and the semiconductor memory device is sealed in the same container as a semiconductor chip.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing one embodiment of the present invention.

この実施例は、半導体チップ６が搭載されたアイランド
５く接地端子３につながっている）と連結する吊りビン
４とその隣りの内部リード２１（電源端子２につながっ
ている）にバイパスコンデンサ１が接続され、容器７に
封止されている。半導体チップに比べて容器の方がかな
り大きいので、小型のコンデンサを取りつける余裕は、
多くの場合、十分にある。In this embodiment, a bypass capacitor 1 is connected to a hanging bottle 4 connected to an island 5 on which a semiconductor chip 6 is mounted (connected to a ground terminal 3), and an internal lead 21 next to it (connected to a power supply terminal 2). connected and sealed in the container 7. The container is much larger than the semiconductor chip, so there is plenty of room to install a small capacitor.
Often there is enough.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は半導体記憶装置の内部にバ
イパスコンデンサを内蔵することにより、バイパスコン
デンサを実装する必要がなくなり、製造コストが下る。As explained above, in the present invention, by incorporating a bypass capacitor inside a semiconductor memory device, there is no need to mount a bypass capacitor, and manufacturing costs are reduced.

また電気的特性もバイパスコンデンサがメモリ素子の近
傍に置れるなめ、性能が向上するという利点もある。In addition, since the bypass capacitor can be placed near the memory element, the electrical characteristics also have the advantage of improved performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の平面図である。 １・・・バイパスコンデンサ、２・・・電源端子、２・
・・内部リード、３・・・接地端子、４・・・吊りビン
、・アイランド、６・・・半導体チップ、７・・・容器
。FIG. 1 is a plan view of one embodiment of the present invention. 1... Bypass capacitor, 2... Power supply terminal, 2...
...Internal lead, 3...Grounding terminal, 4...Hanging bottle, -Island, 6...Semiconductor chip, 7...Container.

Claims (1)

【特許請求の範囲】[Claims] 電源端子と接地端子との間にバイパスコンデンサが挿入
されて半導体チップと同じ容器に封止されていることを
特徴とする半導体記憶装置。A semiconductor memory device characterized in that a bypass capacitor is inserted between a power supply terminal and a ground terminal and is sealed in the same container as a semiconductor chip.
JP63203640A 1988-08-15 1988-08-15 Semiconductor memory device Pending JPH0252464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63203640A JPH0252464A (en) 1988-08-15 1988-08-15 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63203640A JPH0252464A (en) 1988-08-15 1988-08-15 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH0252464A true JPH0252464A (en) 1990-02-22

Family

ID=16477396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63203640A Pending JPH0252464A (en) 1988-08-15 1988-08-15 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH0252464A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62210661A (en) * 1986-03-12 1987-09-16 Hitachi Micro Comput Eng Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62210661A (en) * 1986-03-12 1987-09-16 Hitachi Micro Comput Eng Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors

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