JPH04177870A - Pga package - Google Patents

Pga package

Info

Publication number
JPH04177870A
JPH04177870A JP2306568A JP30656890A JPH04177870A JP H04177870 A JPH04177870 A JP H04177870A JP 2306568 A JP2306568 A JP 2306568A JP 30656890 A JP30656890 A JP 30656890A JP H04177870 A JPH04177870 A JP H04177870A
Authority
JP
Japan
Prior art keywords
package
chip
lead
fixed
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2306568A
Other languages
Japanese (ja)
Other versions
JP2841841B2 (en
Inventor
Toshiyuki Ota
敏行 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2306568A priority Critical patent/JP2841841B2/en
Publication of JPH04177870A publication Critical patent/JPH04177870A/en
Application granted granted Critical
Publication of JP2841841B2 publication Critical patent/JP2841841B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable thermal resistance to be low, multiple pins to be provided, and switching noise to be reduced by providing a second lamination substrate where an external lead is provided on a lower surface and an upper surface is connected to a lead within a package and a chip capacitor which is sealed to a recessed part of the lamination substrate. CONSTITUTION:A lamination substrate 5 where an opening is formed at a central part and a lead within package 7 is provided on a lower surface, a cooling plate 3 which is fixed at the lamination substrate 5 by the brazing method or thermocompression method, an IC chip 4 which is adhered on a lower surface of the cooling plate 3, a heat sink 1 which is fixed on an upper surface of the cooling plate 3 through an adhesive 2, a lamination substrate 8 where there is a recessed part at the center, an external lead 10 is provided on the lower surface, and it is connected to the lead within package 7, and a chip capacitor 9 which is sealed onto this recessed part are provided, thus enabling thermal resistance to be small, an external lead to be formed at a lower part of the IC chip for meeting the need for multiple pins, and the chip capacitor IC to be mounted at a lower part of the chip 4, thus allowing switching noise to be reduced without changing package dimensions.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＰＧＡパッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to PGA packages.

〔従来の技術〕[Conventional technology]

従来のセラミックパッケージとして特に多ピンに適用で
きるものとしては、ＰＧＡ（ビングリッドアレー）パッ
ケージが標準的になっている。As a conventional ceramic package particularly applicable to a large number of pins, a PGA (bin grid array) package has become standard.

ＰＧＡパッケージに関する最近の報告として「電子情報
学会報告　ｌＣＤ８９−９８　（１９８９）ＰＰ１５Ｊ
に示すものがある。A recent report on PGA packages is ``IEICE Report lCD89-98 (1989) PP15J
There is something shown below.

ＰＧＡパッケージは実装時にＩＣチップが上に向くフェ
イスアップ型と、ＩＣチップが下に向くフェイスダウン
型に分類される。PGA packages are classified into face-up type, in which the IC chip faces upward during mounting, and face-down type, in which the IC chip faces downward.

フェイスアップ型ＰＧＡパッケージは第２図に示すよう
に、下面に外部リードＩＯＡを有するセラミックの積層
基板５Ａに凹部を設け、この凹部内にＩＣチップ４を固
着し、更に積層基板５Ａ上に接着剤２を介してヒートシ
ンク１を固着した構造となっている。As shown in FIG. 2, the face-up type PGA package has a recess formed in a ceramic multilayer substrate 5A having an external lead IOA on the bottom surface, an IC chip 4 fixed in the recess, and an adhesive on the multilayer substrate 5A. It has a structure in which the heat sink 1 is fixed via the heat sink 2.

またフェイスダウン型ＰＧＡパッケージは、第３図に示
すように、下面に外部リードＩＯＡを有する積層基板５
Ｂの中央部に開口部を設け、この開口部の上面を覆うよ
うに放熱板を固着し、この放熱板の下面にＩＣチップ４
を固着し、更に放熱板３の上面に接着剤２を介してヒー
トシンク１を固着した構造となっている。Furthermore, as shown in FIG. 3, the face-down type PGA package has a multilayer substrate 5 with an external lead IOA on the bottom surface.
An opening is provided in the center of B, a heat sink is fixed so as to cover the top surface of this opening, and an IC chip 4 is placed on the bottom surface of this heat sink.
The heat sink 1 is further fixed to the upper surface of the heat dissipation plate 3 via an adhesive 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のフェイスアップ型のＰＧＡパッケージは、チップ
の下にピンを立てることができるなめ多ビンに向いてい
るが熱の経路が長くなり、熱抵抗が高くなるという欠点
があった。Conventional face-up PGA packages are suitable for multi-bin applications because pins can be placed under the chip, but they have the disadvantage of requiring a long heat path and high thermal resistance.

また、従来のフェイスダウン型ＰＧＡパッケージは、熱
抵抗を小さくできるという利点はあるが、ＩＣチップの
下部に外部リードを形成することができないため、多ビ
ンに応用するためには、パッケージサイズを大きくする
か、もしくはピン間ピッチを小さくするかの方法がとら
れていた。In addition, although the conventional face-down type PGA package has the advantage of reducing thermal resistance, it is not possible to form external leads under the IC chip, so the package size must be increased in order to apply it to multiple bins. The method used was either to increase the pitch between the pins, or to reduce the pitch between the pins.

しかしながら前者は高密度実装が出来ず、後者は特殊な
実装技術が必要で特にＡＳＩＣ対応のパッケージでは実
装する側の対応が困難であるという問題点があった。However, the former does not allow high-density mounting, and the latter requires special mounting technology, which is difficult for the mounting side to handle, especially in ASIC compatible packages.

また、最近高速デバイス用のパッケージではスイッチン
グノイズ（デルタＩノイズ）が問題になっており、この
対策として電源部のインダクタンスを下げるか、チップ
コンデンサを内蔵するかの方法が採られている。前者の
方法には限度があるため、最近はチップコンデンサを内
蔵したＬＳＩパッケージが多くなっている。しかしなが
ら、従来のＰＧＡ型のパッケージでは、チップコンデン
サをキャビティー内のチップの横に配置する等の方法で
行われているため、キャビティーの寸法だけでなく、パ
ッケージの寸法も大きくなるという大きな問題点を有し
ていた。Furthermore, switching noise (delta I noise) has recently become a problem in packages for high-speed devices, and as a countermeasure to this problem, methods have been adopted such as lowering the inductance of the power supply section or incorporating chip capacitors. Since the former method has limitations, recently there have been an increasing number of LSI packages with built-in chip capacitors. However, in conventional PGA type packages, the chip capacitor is placed next to the chip in the cavity, which causes a big problem in that not only the cavity size but also the package size increases. It had a point.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のＰＧＡパッケージは、中央部に開口部を有しか
つ下面にパッケージ内リードが設けられた第１の積層基
板と、前記開口部の上面を覆うように設けられ下面にＩ
Ｃチップが固着された放熱板と、この放熱板の上面に固
着されたヒートシンクと、上面の中央部に凹部を有し下
面に外部リードが設けられ、かつ上面が前記パッケージ
内リードに接続された第２の積層基板と、この第２の積
層基板の凹部に固着されたチップコンデンサとを有する
ものである。The PGA package of the present invention includes a first laminated substrate having an opening in the center and an in-package lead provided on the lower surface, and an I/O layer provided on the lower surface so as to cover the upper surface of the opening.
A heat sink to which a C chip is fixed, a heat sink fixed to the upper surface of the heat sink, a recessed portion in the center of the upper surface, an external lead provided on the lower surface, and the upper surface connected to the lead in the package. The device includes a second multilayer substrate and a chip capacitor fixed in a recessed portion of the second multilayer substrate.

〔実施例〕〔Example〕

次に本発明を図面を用いて説明する。 Next, the present invention will be explained using the drawings.

第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

第１図においてＰＧＡパッケージは、中央部に開口部が
形成され下面にパッケージ内リード７が設けられたセラ
ミックからなる第１の積層基板５と、この開口部の上面
を覆うように第１の積層基板５にロー付は法や熱圧着法
により固定された放熱板３と、この放熱板３の下面に固
着されたＩＣチップ４と、放熱板３の上面に接着剤２を
介して固定されたヒートシンク１と、中央部に凹部を有
し下面に外部リード１０が設けられ、かつパッケージ内
リード７に接続するセラミックからなる第２の積層基板
８と、この凹部上に固着されたチップコンデンサ９とか
ら主に構成されている。尚第１図において６はキャップ
である。In FIG. 1, the PGA package includes a first laminated substrate 5 made of ceramic with an opening formed in the center and an in-package lead 7 provided on the lower surface, and a first laminated substrate 5 that covers the upper surface of this opening. A heat sink 3 is fixed to a substrate 5 by brazing or thermocompression, an IC chip 4 is fixed to the bottom surface of the heat sink 3, and an IC chip 4 is fixed to the top surface of the heat sink 3 via an adhesive 2. A heat sink 1, a second laminated substrate 8 made of ceramic having a recess in the center and having an external lead 10 on the lower surface and connected to the package internal lead 7, and a chip capacitor 9 fixed on the recess. It is mainly composed of. In FIG. 1, 6 is a cap.

本実施例に示したＰＧＡパッケージでは、パッケージ内
リード７はピン間隔が１．２７ｍｍと狭くなっているが
、外部リード１０はピン間隔が２．５４ｍｍと広くして
いる。パッケージ内り−ド７の接続には高度の接続技術
と専用の設備が必要であるが、それはＬＳＩメーカー等
の専用メーカーで生産するため問題は無い。また外部リ
ード１０の接続は汎用のＰＧＡパッケージと同じである
ため実装は容易である。In the PGA package shown in this embodiment, the internal leads 7 of the package have a narrow pin interval of 1.27 mm, but the external leads 10 have a wide pin interval of 2.54 mm. Although advanced connection technology and special equipment are required to connect the inside of the package to the card 7, there is no problem because it is produced by a dedicated manufacturer such as an LSI manufacturer. Furthermore, since the connection of the external leads 10 is the same as that of a general-purpose PGA package, mounting is easy.

また、本実施例ではＩＣチップ４の下部に外部リード１
０を形成できるなめ、多ピンパツケージに適している。In addition, in this embodiment, an external lead 1 is provided at the bottom of the IC chip 4.
Since it can form 0, it is suitable for multi-pin packages.

実際に従来と同一数の多ピンパツケージに本発明を適用
した場合、パッケージ面積を７０％以下にすることがで
きた。またＩＣチップ４の下部にチップコンデンサ９を
搭載できるため、パッケージ寸法を広げる事なくスイッ
チングノイズを低減できる。When the present invention was actually applied to a multi-pin package with the same number as the conventional one, the package area could be reduced to 70% or less. Furthermore, since the chip capacitor 9 can be mounted below the IC chip 4, switching noise can be reduced without increasing the package size.

このように本実施例は、フェイスダウン型ＰＧＡでかつ
多ビンパッケージであるため、低熱抵抗でかつ多ピン対
応の汎用パッケージであり、しかもスイッチングを少な
くすることができる。As described above, since this embodiment is a face-down type PGA and a multi-bin package, it is a general-purpose package that has low thermal resistance and supports a large number of pins, and can reduce switching.

尚、上記実施例では、第１の積層基板としてセラミック
基板を用いた場合について説明したが、プリント基板を
用いてもよい。この場合、より低コストＰＧＡパッケー
ジを形成できるというメリットがある。In the above embodiment, a ceramic substrate is used as the first laminated substrate, but a printed circuit board may also be used. In this case, there is an advantage that a lower cost PGA package can be formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明のＰＧＡパッケージでは、フ
ェイスダウン型ＰＧＡパッケージであるため熱抵抗が小
さく、ＩＣチップの下部に外部リードを形成できるため
多ピン対応が可能であり、更にチップコンデンサＩＣを
チップの下部に搭載できるため、パッケージ寸法を変化
させずにスイッチングノイズを低減できるという効果が
ある。As explained above, the PGA package of the present invention has low thermal resistance because it is a face-down type PGA package, and can support a large number of pins because external leads can be formed at the bottom of the IC chip. Since it can be mounted at the bottom of the package, it has the effect of reducing switching noise without changing the package dimensions.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の断面図、第２図及び第３図
は従来例の断面図である。 １・・・ヒートシンク、２・・・接着剤、３・・・放熱
板、４・・・ＩＣチップ、５・・・第１の積層基板、５
Ａ、５Ｂ・・・積層基板、６・・・キャップ、７・・・
パッケージ内リード、８・・・第２の積層基板、９・・
・チップコンデンサ、１０．ＩＯＡ・・・外部リード。FIG. 1 is a sectional view of one embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a conventional example. DESCRIPTION OF SYMBOLS 1... Heat sink, 2... Adhesive, 3... Heat sink, 4... IC chip, 5... First laminated board, 5
A, 5B...Laminated substrate, 6...Cap, 7...
Leads in the package, 8... Second laminated board, 9...
・Chip capacitor, 10. IOA...External lead.

Claims (1)

【特許請求の範囲】[Claims] 　中央部に開口部を有しかつ下面にパッケージ内リード
が設けられた第１の積層基板と、前記開口部の上面を覆
うように設けられ下面にＩＣチップが固着された放熱板
と、この放熱板の上面に固着されたヒートシンクと、上
面の中央部に凹部を有し下面に外部リードが設けられ、
かつ上面が前記パッケージ内リードに接続された第２の
積層基板と、この第２の積層基板の凹部に固着されたチ
ップコンデンサとを有することを特徴とするＰＧＡパッ
ケージ。a first laminated substrate having an opening in the center and having in-package leads on the bottom surface; a heat sink provided to cover the top surface of the opening and having an IC chip fixed to the bottom surface; It has a heat sink fixed to the top surface of the board, a recess in the center of the top surface, and external leads provided on the bottom surface.
A PGA package comprising: a second multilayer substrate whose upper surface is connected to the internal lead of the package; and a chip capacitor fixed to a recess of the second multilayer substrate.
JP2306568A 1990-11-13 1990-11-13 PGA package Expired - Fee Related JP2841841B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2306568A JP2841841B2 (en) 1990-11-13 1990-11-13 PGA package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2306568A JP2841841B2 (en) 1990-11-13 1990-11-13 PGA package

Publications (2)

Publication Number Publication Date
JPH04177870A true JPH04177870A (en) 1992-06-25
JP2841841B2 JP2841841B2 (en) 1998-12-24

Family

ID=17958627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2306568A Expired - Fee Related JP2841841B2 (en) 1990-11-13 1990-11-13 PGA package

Country Status (1)

Country Link
JP (1) JP2841841B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633783A (en) * 1994-09-29 1997-05-27 Fujitsu Limited Multi-chip ceramic module for mounting electric parts on both substrate and cap connected through interconnecting pins
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633783A (en) * 1994-09-29 1997-05-27 Fujitsu Limited Multi-chip ceramic module for mounting electric parts on both substrate and cap connected through interconnecting pins
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US6101100A (en) * 1996-07-23 2000-08-08 International Business Machines Corporation Multi-electronic device package

Also Published As

Publication number Publication date
JP2841841B2 (en) 1998-12-24

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