JPS59124744A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59124744A JPS59124744A JP23378982A JP23378982A JPS59124744A JP S59124744 A JPS59124744 A JP S59124744A JP 23378982 A JP23378982 A JP 23378982A JP 23378982 A JP23378982 A JP 23378982A JP S59124744 A JPS59124744 A JP S59124744A
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- substrate
- end surfaces
- board
- capacitors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は基板上にチップキャリア、コンデンサ等を搭載
するモジュールに係り、特にコンデンサを基板の端面或
いは裏面へ実装するようにした半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a module in which a chip carrier, a capacitor, etc. are mounted on a substrate, and particularly to a semiconductor device in which a capacitor is mounted on an end surface or a back surface of a substrate.
(2)技術の背景
近年、集積回路製造技術の中心は、素子チ・ノブ自体以
外の組立実装面にも向けられてきており、またICパッ
ケージコストがICチップコストを上回るケースも増え
ているためICパッケージに対する関心も高まっている
。(2) Technology background In recent years, integrated circuit manufacturing technology has focused on assembly and mounting aspects other than the element chip/nob itself, and there are also increasing cases where IC package cost exceeds IC chip cost. Interest in IC packages is also increasing.
さらに、最近リードのない小型部品が増加する傾向にあ
る。これはチップ部品が実装を高めるための小型化に通
しているだけでなく、大量生産のための自動化に適して
おり、コストの低減にもつながるからである。Furthermore, there has recently been a trend towards the use of small parts without leads. This is because not only are chip components susceptible to miniaturization to improve packaging, but they are also suitable for automation for mass production, leading to lower costs.
そして例えば現在LCC(リードレスチップキャリア)
と呼ばれているリードのないチップを搭載したキャリア
が開発されており、このL CCをプリント基板に実装
してカードとなすための有効なモジュールの実用化が要
請されている。For example, currently LCC (leadless chip carrier)
A carrier equipped with a leadless chip called LCC has been developed, and there is a demand for the practical implementation of an effective module for mounting this LCC on a printed circuit board to form a card.
(3)従来技術と問題点
従来1cのパッケージとしては、フラットパッケージ、
デュアルインラインパッケージ(以下DIPと記す)等
各種開発されてきているが、何れのタイプも例えば放熱
或いは高密度実装等に関して問題を有している。(3) Conventional technology and problems Conventional 1c packages include flat packages,
Although various types such as dual in-line packages (hereinafter referred to as DIPs) have been developed, all types have problems with respect to heat dissipation, high-density packaging, and the like.
例えば、第1図の如きDIPの平面図の上部キャップを
取り除いた図において、セラミック等から形成される基
板1中の内リード部2の部分の占有する面積の割合がI
Cチップ3自体の大きさに比べてはるかに大きな比重を
占めているために、特に実装密度を高める上で大きなネ
ックとなっている。For example, in a plan view of a DIP with the top cap removed, as shown in FIG.
Since it occupies a much larger specific weight than the size of the C chip 3 itself, it becomes a major bottleneck especially in increasing the packaging density.
このため、前述したようにリード部のないキャリアすな
わちL CCが現在開発されている。これを第2図にて
説明する。For this reason, carriers without leads, ie, LCCs, are currently being developed as described above. This will be explained with reference to FIG.
第2図(alは従来のLCCの外観を示す側面図、第2
図(blは外観を示す底面図、第2図(C)は第2図!
a)のA−A断面矢視図を示すもので第2図tc+に示
すようにグリーンシート等の多層セラミック基板1上に
チップ3を載置して該セラミック基板1の配線バターニ
ング部分とチップをボンディングし配線端子4aをパッ
ケージの側面及び底面に沿ってはわせたもので、第2図
fal及び(blに示すように長さLX幅W×厚さtは
11.05L mmX 7.49w w X2.16L
wmで長さ方向端子ピッチp+ = 5.08m 。Figure 2 (al is a side view showing the appearance of a conventional LCC,
Figures (bl is a bottom view showing the external appearance, Figure 2 (C) is Figure 2!
This is a cross-sectional view taken along line A-A in a), and as shown in Figure 2 tc+, a chip 3 is placed on a multilayer ceramic substrate 1 such as a green sheet, and the wiring patterning portion of the ceramic substrate 1 and the chip are The wiring terminals 4a are bonded to the side and bottom of the package, and as shown in Figure 2 fal and (bl), the length L x width W x thickness t is 11.05 L mm x 7.49 w w. X2.16L
Lengthwise terminal pitch p+ = 5.08 m in wm.
幅方向端子ピンチp 2 = 1.27mと極めて小さ
く構成できて、従来のDTPの約1/3の大きさとする
ことかできる。このようなt、 CCとDIPをプリン
ト基板等にパスコン等を搭載する場合にはプリント基板
上に平面的にLCC,DIPコンデンサ等を並べて配置
するために実装密度が上がらない欠点があった。The terminal pinch p 2 in the width direction can be extremely small, ie, 1.27 m, making it approximately 1/3 the size of a conventional DTP. When a bypass capacitor or the like is mounted on a printed circuit board or the like for such T, CC, and DIP, there is a drawback that the mounting density cannot be increased because the LCC, DIP capacitor, etc. are arranged side by side on the printed circuit board.
(4)発明の目的
本発明は上記従来の欠点に鑑みなされたものであり、プ
リント基板に立体的に立てた状態で差し込み可能な基板
の表裏面にT−CCを、表裏面または端面にコンデンサ
を装着して実装密度の向上を計ることを目的とするもの
である。(4) Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks of the conventional art. The purpose is to improve the packaging density by installing the
(5)発明の構成
本発明の目的は、基体と、該基体の少なくとも一主表面
に搭載されたリードレスチップキャリアと、該基体の一
側面から導出する複数のリードピンと、該基体の他の主
表面および該基体の他の側面のうち、少なくとも一つの
面に電気素子が搭載されてなることを特徴とする半導体
装置を提供することによって達成される。(5) Structure of the Invention The object of the present invention is to provide a base body, a leadless chip carrier mounted on at least one main surface of the base body, a plurality of lead pins led out from one side of the base body, and other parts of the base body. This is achieved by providing a semiconductor device characterized in that an electric element is mounted on at least one of the main surface and the other side surface of the base.
(6)発明の実施例 以下、本発明の実施例について図面を用いて説明する。(6) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第3図(a)及び山)は本発明の一実施例の正面図と側
面図とを各々示している。Figures 3(a) and 3(a) show a front view and a side view, respectively, of an embodiment of the present invention.
第3図(81において、セラミック等の多層基板1′面
に、L CC4が例えばハンダ付は等により片面に4個
ずつ都合8個搭載されて固定されており、また前記基板
1′上の上面には電気素子、例えばコンデンサ5が同様
にして例えば3偏設けられ、半導体装置のモジュールを
形成している。この基板の大きさは DTPの1個分
に相当し前記LCC4及びコンデンサ5は基板1′内の
配線パターンを介し電気的接続がなされており、さらに
基板1′上の例えば下側端面に複数設けられたピン6を
あらかじめ設けられたボードまたはプリント基板8の端
子の接続部に基板1を立てた状態で挿入することによっ
て半導体装置のモジュールは電気的接続がなされている
。In Figure 3 (81), a total of 8 LCC4s are mounted and fixed, 4 on each side, by soldering, etc., on the surface of a multilayer board 1' made of ceramic or the like, and the upper surface of the board 1' Electric elements, such as capacitors 5, are similarly provided on three sides to form a module of a semiconductor device.The size of this board corresponds to one DTP, and the LCC 4 and capacitors 5 are arranged on the board 1. Electrical connection is made through the wiring pattern inside the board 1', and a plurality of pins 6 are provided on the lower end surface of the board 1', for example, and the board 1' is connected to the terminal connection part of the board or printed circuit board 8 that has been provided in advance. By inserting the module in an upright position, the semiconductor device module is electrically connected.
また、第3図(blにおいて、例えばセラミック等から
なる基板1′上の両面において、LCCの例5−
えば端子4aと基板1′の図示しない端子間でハンダ付
け7がなされており、これら両面間の電気的接続は複数
の多層構成されたセラミック上の多層パターンでなされ
ている。In addition, in FIG. 3 (bl), on both sides of a substrate 1' made of ceramic or the like, soldering 7 is made between, for example, the terminal 4a of the LCC and the terminal (not shown) of the substrate 1', and these The electrical connection between them is made by a multilayer pattern on a plurality of multilayered ceramics.
本発明の半導体装置のモジュールは、基板1′上の大部
分の面積を占有する表面または又は裏面にはL CC4
のみを搭載させである。また、基板1′上の表面及び裏
面以外の僅かな部分例えば上面等の端面を利用して電気
回路上不可欠な電気素子例えば(デカップリング)コン
デンサ5を搭載させているため、基板1′上に搭載する
ことが可能なLCCの数は基板の大きさに対応して定め
ることが可能でコンデンサを基板端面に持って来ただけ
高密度化が可能となっている。The module of the semiconductor device of the present invention has an L CC4 on the front surface or the back surface occupying most of the area on the substrate 1'.
It is equipped with only. In addition, since the electrical elements essential for the electric circuit, such as the (decoupling) capacitor 5, are mounted on a small portion of the substrate 1' other than the front and back surfaces, such as the top surface, the The number of LCCs that can be mounted can be determined according to the size of the board, and the density can be increased by bringing the capacitors closer to the edge of the board.
さらに、本発明の半導体装置のモジュールは、ボード上
に縦形にて実装させるためiこ実装密度は頗る向上して
いる。Furthermore, since the module of the semiconductor device of the present invention is mounted vertically on the board, the mounting density is significantly improved.
第4図(al及び(hlは本発明の他の実施例の正面図
と側面図をそれぞれ示す。FIG. 4 (al and (hl) respectively show a front view and a side view of another embodiment of the present invention.
第4図(alにおいて、セラミック等の基板1゛面6−
の表面部へには1.、 CC4が例えばハンディ」け等
により4個固定されて搭載されており、また、前記基板
1′」二の裏面Bには(デカップリング)コンデン−1
1□ 5がハンダ付は等で例えば3開設けられ、半導体
モジュールを形成している。そして、多層セラミック基
板内で配線が行われて各素子間の電気的接続がしまから
れており、さらに基板1′上の例えば下側端面に複数設
けられているビン6をあらかじめ設けられているボード
8上の端子の接続部に嵌合することにより、半導体装置
のモジュールは外部と電気的接続がなされている。In FIG. 4 (al), four CC4's are fixed and mounted on the surface of the substrate 1' surface 6-, made of ceramic or the like, by means of hand-held screws, for example, and the substrate 1' is mounted. On the second back side B (decoupling) condensate-1
1□ 5 is soldered, etc., and three openings are formed, for example, to form a semiconductor module. Then, wiring is performed within the multilayer ceramic substrate to secure electrical connections between each element, and furthermore, a plurality of bins 6 are provided in advance on the lower end surface of the substrate 1', for example. By fitting into the connecting portions of the terminals on the board 8, the semiconductor device module is electrically connected to the outside.
第4図(blにおいて、例えばセラミック等からなる基
板1′」二の表面へにおいて、T、 CC4の例えば〜
1iL7−A aと基板の図示しない端子間にハンディ
づけ7がなされて固定されており、また基板1′上の裏
面Bにおいて、コンデンサ5が例えばハンダ付け7によ
り固定されて実装されている。これら両面間の電気的接
続は複数の多層セラミック基板から構成された多層配線
9を介して行われている。In Figure 4 (bl), on the second surface of the substrate 1' made of, for example, ceramic, etc., for example ~
1iL7-Aa and a terminal (not shown) of the board are fixed by a handy attachment 7, and a capacitor 5 is fixed and mounted, for example, by soldering 7 on the back surface B of the substrate 1'. Electrical connection between these surfaces is made via multilayer wiring 9 made up of a plurality of multilayer ceramic substrates.
本発明の半導体装置のモジュールは、基板1′上の大部
分の面積を占有している表面へ及び裏面Bにはそれぞれ
例えばl−CCとコンデン+5を搭載させである。これ
は基板1′を縦形にボート′に挿入し、基板の表裏両面
すなわち2面分の面積が占有可能となっているため一板
の基板中に搭載できるI、、、 CC数は大幅に増加し
ている。また、さらに基板を縦形に利用してボード上に
実装させであるため、ボード上での実装密度も飛vM的
に増大している。In the semiconductor device module of the present invention, for example, l-CC and capacitor +5 are mounted on the front surface occupying most of the area on the substrate 1' and on the back surface B, respectively. In this case, the board 1' is inserted vertically into the boat', and the area on both the front and back sides of the board can be occupied, so the number of I... CCs that can be mounted on one board is greatly increased. are doing. Furthermore, since the substrate is mounted vertically on the board, the mounting density on the board is also increasing dramatically.
尚、本実施例では、基板中に搭載される電気素子として
コンデンサの例を示したが、その他にインダクタンス等
の素子も搭載することができる。In this embodiment, a capacitor is shown as an example of an electric element mounted on the substrate, but other elements such as an inductance can also be mounted.
(7)発明の効果
以上述べてきたように、本発明の半導体装置のモジュー
ル化によって、すなわち多層配線をなす基板を縦形にし
て表裏両面での素子の搭載を図り、且つ上下端面等にさ
らにコンデンサ及び外リード用の電気的端子を設けたこ
とによって、従来に比べて実装密度の大幅に高められた
゛P、導体装置のモジュールが可能となっている。(7) Effects of the Invention As described above, by modularizing the semiconductor device of the present invention, in other words, by making the board with multilayer wiring vertical, elements can be mounted on both the front and back surfaces, and capacitors can be mounted on the upper and lower end surfaces. By providing electrical terminals for the external leads and external leads, it is possible to create a conductor device module with greatly increased packaging density compared to the prior art.
また、さらに係る半導体装置の各モジュールをボード上
に搭載する際の実装密度に関しても、」7記の如く基板
を縦形として用いであるために高密度実装を図ることが
可能となっている。Furthermore, regarding the mounting density when mounting each module of the semiconductor device on a board, it is possible to achieve high-density mounting because the board is vertically shaped as described in item 7.
第1図は従来から用いられているデュアルインラインパ
ッケージ(DTP)の上部キャップを取り除いた際の平
面図、第2図(δ)乃至fnlはLCCの構成を示す側
面図、底面図及び第2図(8)のA−A断面図、第3図
(8)及び(b)は本発明の一実施例のそれぞれ正面図
と側面図、第4図(al及び(blも同様に本発明の他
の実施例のそれぞれ正面部と側面図である。
1.1′・・・基板、 2・・・内リード部、3・・
・ICチップ、 4・・・リードレスチップキャリ
ア、 5・・・デカソプリングコンデンザ、 6
・・・ビン、 8・・・ボード。
−〇−
” t。
第2図
(0)
第4図
うFig. 1 is a plan view of a conventionally used dual in-line package (DTP) with the top cap removed, and Fig. 2 (δ) to fnl are a side view, a bottom view, and a bottom view showing the configuration of the LCC. 3 (8) and (b) are respectively a front view and a side view of one embodiment of the present invention, and FIG. 1. They are a front part and a side view of an embodiment of the present invention. 1.1'... Board, 2... Inner lead part, 3...
・IC chip, 4...Leadless chip carrier, 5...Decaso spring capacitor, 6
...Bin, 8...Board. −〇− ”t. Figure 2 (0) Figure 4 U
Claims (1)
ドレスチップキャリアと、該基体の一側面から導出する
複数のリードピンと、該基体の他の主表面および該基体
の他の側面のうち、少なくとも一つの面に電気素子が搭
載されてなることを特徴とする半導体装置。A base, a leadless chip carrier mounted on at least one main surface of the base, a plurality of lead pins led out from one side of the base, the other main surface of the base, and the other side of the base, A semiconductor device characterized by having an electric element mounted on at least one surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23378982A JPS59124744A (en) | 1982-12-29 | 1982-12-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23378982A JPS59124744A (en) | 1982-12-29 | 1982-12-29 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59124744A true JPS59124744A (en) | 1984-07-18 |
JPH0473298B2 JPH0473298B2 (en) | 1992-11-20 |
Family
ID=16960588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23378982A Granted JPS59124744A (en) | 1982-12-29 | 1982-12-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59124744A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63141352A (en) * | 1986-12-03 | 1988-06-13 | Nec Corp | Suface-packaged integrated circuit module |
JP2001110984A (en) * | 1999-10-13 | 2001-04-20 | Hitachi Ltd | Semiconductor module and electric device using it |
JP2003110049A (en) * | 2001-09-28 | 2003-04-11 | Fujitsu Ten Ltd | High-frequency ic package and high-frequency unit using the same and manufacturing method thereof |
JP2010118639A (en) * | 2008-11-13 | 2010-05-27 | Samsung Electro-Mechanics Co Ltd | Semiconductor integrated circuit chip, laminated chip capacitor, and semiconductor integrated circuit chip package |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5719738U (en) * | 1980-07-08 | 1982-02-01 |
-
1982
- 1982-12-29 JP JP23378982A patent/JPS59124744A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5719738U (en) * | 1980-07-08 | 1982-02-01 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63141352A (en) * | 1986-12-03 | 1988-06-13 | Nec Corp | Suface-packaged integrated circuit module |
JP2001110984A (en) * | 1999-10-13 | 2001-04-20 | Hitachi Ltd | Semiconductor module and electric device using it |
JP2003110049A (en) * | 2001-09-28 | 2003-04-11 | Fujitsu Ten Ltd | High-frequency ic package and high-frequency unit using the same and manufacturing method thereof |
JP2010118639A (en) * | 2008-11-13 | 2010-05-27 | Samsung Electro-Mechanics Co Ltd | Semiconductor integrated circuit chip, laminated chip capacitor, and semiconductor integrated circuit chip package |
US8304854B2 (en) | 2008-11-13 | 2012-11-06 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor integrated circuit chip, multilayer chip capacitor and semiconductor integrated circuit chip package |
Also Published As
Publication number | Publication date |
---|---|
JPH0473298B2 (en) | 1992-11-20 |
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